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a="78109383" X-IronPort-AV: E=Sophos;i="6.18,274,1751266800"; d="scan'208";a="78109383" X-CSE-ConnectionGUID: EIBwaUZKQ7mrUGStAQpqTQ== X-CSE-MsgGUID: 6ZO2TeYdSUOMkPAlp8SnnA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,274,1751266800"; d="scan'208";a="175930290" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v6 02/22] intel_iommu: Delete RPS capability related supporting code Date: Thu, 18 Sep 2025 04:57:41 -0400 Message-ID: <20250918085803.796942-3-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250918085803.796942-1-zhenzhong.duan@intel.com> References: <20250918085803.796942-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.8; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1758185973512116600 Content-Type: text/plain; charset="utf-8" RID-PASID Support(RPS) is not set in vIOMMU ECAP register, the supporting code is there but never take effect. Meanwhile, according to VTD spec section 3.4.3: "Implementations not supporting RID_PASID capability (ECAP_REG.RPS is 0b), use a PASID value of 0 to perform address translation for requests without PASID." We should delete the supporting code which fetches RID_PASID field from scalable context entry and use 0 as RID_PASID directly, because RID_PASID field is ignored if no RPS support according to spec. This simplify the code and doesn't bring any penalty. Opportunistically, s/rid2pasid/rid_pasid and s/RID2PASID/RID_PASID as VTD spec uses RID_PASID terminology. Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 1 - hw/i386/intel_iommu.c | 49 +++++++++++++--------------------- 2 files changed, 19 insertions(+), 31 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 360e937989..6abe76556a 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -547,7 +547,6 @@ typedef struct VTDRootEntry VTDRootEntry; #define VTD_CTX_ENTRY_LEGACY_SIZE 16 #define VTD_CTX_ENTRY_SCALABLE_SIZE 32 =20 -#define VTD_SM_CONTEXT_ENTRY_RID2PASID_MASK 0xfffff #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL0(aw) (0x1e0ULL | ~VTD_HAW_MASK(aw)) #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 0xffffffffffe00000ULL =20 diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 71b70b795d..b976b251bc 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -41,8 +41,7 @@ #include "trace.h" =20 /* context entry operations */ -#define VTD_CE_GET_RID2PASID(ce) \ - ((ce)->val[1] & VTD_SM_CONTEXT_ENTRY_RID2PASID_MASK) +#define RID_PASID 0 #define VTD_CE_GET_PASID_DIR_TABLE(ce) \ ((ce)->val[0] & VTD_PASID_DIR_BASE_ADDR_MASK) =20 @@ -951,7 +950,7 @@ static int vtd_ce_get_pasid_entry(IntelIOMMUState *s, V= TDContextEntry *ce, int ret =3D 0; =20 if (pasid =3D=3D PCI_NO_PASID) { - pasid =3D VTD_CE_GET_RID2PASID(ce); + pasid =3D RID_PASID; } pasid_dir_base =3D VTD_CE_GET_PASID_DIR_TABLE(ce); ret =3D vtd_get_pe_from_pasid_table(s, pasid_dir_base, pasid, pe); @@ -970,7 +969,7 @@ static int vtd_ce_get_pasid_fpd(IntelIOMMUState *s, VTDPASIDEntry pe; =20 if (pasid =3D=3D PCI_NO_PASID) { - pasid =3D VTD_CE_GET_RID2PASID(ce); + pasid =3D RID_PASID; } pasid_dir_base =3D VTD_CE_GET_PASID_DIR_TABLE(ce); =20 @@ -1510,15 +1509,14 @@ static inline int vtd_context_entry_rsvd_bits_check= (IntelIOMMUState *s, return 0; } =20 -static int vtd_ce_rid2pasid_check(IntelIOMMUState *s, +static int vtd_ce_rid_pasid_check(IntelIOMMUState *s, VTDContextEntry *ce) { VTDPASIDEntry pe; =20 /* * Make sure in Scalable Mode, a present context entry - * has valid rid2pasid setting, which includes valid - * rid2pasid field and corresponding pasid entry setting + * has valid pasid entry setting at RID_PASID(0). */ return vtd_ce_get_pasid_entry(s, ce, &pe, PCI_NO_PASID); } @@ -1581,12 +1579,11 @@ static int vtd_dev_to_context_entry(IntelIOMMUState= *s, uint8_t bus_num, } } else { /* - * Check if the programming of context-entry.rid2pasid - * and corresponding pasid setting is valid, and thus - * avoids to check pasid entry fetching result in future - * helper function calling. + * Check if the programming of pasid setting at RID_PASID(0) + * is valid, and thus avoids to check pasid entry fetching + * result in future helper function calling. */ - ret_fr =3D vtd_ce_rid2pasid_check(s, ce); + ret_fr =3D vtd_ce_rid_pasid_check(s, ce); if (ret_fr) { return ret_fr; } @@ -2097,7 +2094,7 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *v= td_as, PCIBus *bus, bool reads =3D true; bool writes =3D true; uint8_t access_flags, pgtt; - bool rid2pasid =3D (pasid =3D=3D PCI_NO_PASID) && s->root_scalable; + bool rid_pasid =3D (pasid =3D=3D PCI_NO_PASID) && s->root_scalable; VTDIOTLBEntry *iotlb_entry; uint64_t xlat, size; =20 @@ -2111,8 +2108,8 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *v= td_as, PCIBus *bus, =20 cc_entry =3D &vtd_as->context_cache_entry; =20 - /* Try to fetch pte from IOTLB, we don't need RID2PASID logic */ - if (!rid2pasid) { + /* Try to fetch pte from IOTLB, we don't need RID_PASID(0) logic */ + if (!rid_pasid) { iotlb_entry =3D vtd_lookup_iotlb(s, source_id, pasid, addr); if (iotlb_entry) { trace_vtd_iotlb_page_hit(source_id, addr, iotlb_entry->pte, @@ -2160,8 +2157,8 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *v= td_as, PCIBus *bus, cc_entry->context_cache_gen =3D s->context_cache_gen; } =20 - if (rid2pasid) { - pasid =3D VTD_CE_GET_RID2PASID(&ce); + if (rid_pasid) { + pasid =3D RID_PASID; } =20 /* @@ -2189,8 +2186,8 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *v= td_as, PCIBus *bus, return true; } =20 - /* Try to fetch pte from IOTLB for RID2PASID slow path */ - if (rid2pasid) { + /* Try to fetch pte from IOTLB for RID_PASID(0) slow path */ + if (rid_pasid) { iotlb_entry =3D vtd_lookup_iotlb(s, source_id, pasid, addr); if (iotlb_entry) { trace_vtd_iotlb_page_hit(source_id, addr, iotlb_entry->pte, @@ -2464,20 +2461,14 @@ static void vtd_iotlb_page_invalidate_notify(IntelI= OMMUState *s, ret =3D vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus), vtd_as->devfn, &ce); if (!ret && domain_id =3D=3D vtd_get_domain_id(s, &ce, vtd_as->pas= id)) { - uint32_t rid2pasid =3D PCI_NO_PASID; - - if (s->root_scalable) { - rid2pasid =3D VTD_CE_GET_RID2PASID(&ce); - } - /* * In legacy mode, vtd_as->pasid =3D=3D pasid is always true. * In scalable mode, for vtd address space backing a PCI * device without pasid, needs to compare pasid with - * rid2pasid of this device. + * RID_PASID(0) of this device. */ if (!(vtd_as->pasid =3D=3D pasid || - (vtd_as->pasid =3D=3D PCI_NO_PASID && pasid =3D=3D rid2p= asid))) { + (vtd_as->pasid =3D=3D PCI_NO_PASID && pasid =3D=3D RID_P= ASID))) { continue; } =20 @@ -2976,9 +2967,7 @@ static void vtd_piotlb_pasid_invalidate(IntelIOMMUSta= te *s, if (!vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus), vtd_as->devfn, &ce) && domain_id =3D=3D vtd_get_domain_id(s, &ce, vtd_as->pasid)) { - uint32_t rid2pasid =3D VTD_CE_GET_RID2PASID(&ce); - - if ((vtd_as->pasid !=3D PCI_NO_PASID || pasid !=3D rid2pasid) = && + if ((vtd_as->pasid !=3D PCI_NO_PASID || pasid !=3D RID_PASID) = && vtd_as->pasid !=3D pasid) { continue; } --=20 2.47.1