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a="78109544" X-IronPort-AV: E=Sophos;i="6.18,274,1751266800"; d="scan'208";a="78109544" X-CSE-ConnectionGUID: teERsLLoQu2LVGVlWUsq5w== X-CSE-MsgGUID: MYoA7UFIStyrGTMhtAej3g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,274,1751266800"; d="scan'208";a="175930449" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Yi Sun Subject: [PATCH v6 15/22] intel_iommu: Bind/unbind guest page table to host Date: Thu, 18 Sep 2025 04:57:54 -0400 Message-ID: <20250918085803.796942-16-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250918085803.796942-1-zhenzhong.duan@intel.com> References: <20250918085803.796942-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.8; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1758186026617116600 Content-Type: text/plain; charset="utf-8" This captures the guest PASID table entry modifications and propagates the changes to host to attach a hwpt with type determined per guest IOMMU PGTT configuration. When PGTT=3DPT, attach RID_PASID to a second stage HWPT(GPA->HPA). When PGTT=3DFST, attach RID_PASID to nested HWPT with nesting parent HWPT coming from VFIO. Co-Authored-by: Yi Liu Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- include/hw/i386/intel_iommu.h | 1 + hw/i386/intel_iommu.c | 152 +++++++++++++++++++++++++++++++++- hw/i386/trace-events | 3 + 3 files changed, 154 insertions(+), 2 deletions(-) diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index ff01e5c82d..86614fbb31 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -104,6 +104,7 @@ struct VTDAddressSpace { PCIBus *bus; uint8_t devfn; uint32_t pasid; + uint32_t fs_hwpt; AddressSpace as; IOMMUMemoryRegion iommu; MemoryRegion root; /* The root container of the device */ diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 5908368c44..bfe229d0dc 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -20,6 +20,7 @@ */ =20 #include "qemu/osdep.h" +#include CONFIG_DEVICES /* CONFIG_IOMMUFD */ #include "qemu/error-report.h" #include "qemu/main-loop.h" #include "qapi/error.h" @@ -41,6 +42,9 @@ #include "migration/vmstate.h" #include "trace.h" #include "system/iommufd.h" +#ifdef CONFIG_IOMMUFD +#include +#endif =20 /* context entry operations */ #define RID_PASID 0 @@ -2398,6 +2402,125 @@ static void vtd_context_global_invalidate(IntelIOMM= UState *s) vtd_iommu_replay_all(s); } =20 +#ifdef CONFIG_IOMMUFD +static int vtd_create_fs_hwpt(HostIOMMUDeviceIOMMUFD *idev, + VTDPASIDEntry *pe, uint32_t *fs_hwpt, + Error **errp) +{ + struct iommu_hwpt_vtd_s1 vtd =3D {}; + + vtd.flags =3D (VTD_SM_PASID_ENTRY_SRE_BIT(pe) ? IOMMU_VTD_S1_SRE : 0) | + (VTD_SM_PASID_ENTRY_WPE_BIT(pe) ? IOMMU_VTD_S1_WPE : 0) | + (VTD_SM_PASID_ENTRY_EAFE_BIT(pe) ? IOMMU_VTD_S1_EAFE : 0); + vtd.addr_width =3D vtd_pe_get_fs_aw(pe); + vtd.pgtbl_addr =3D (uint64_t)vtd_pe_get_fspt_base(pe); + + return !iommufd_backend_alloc_hwpt(idev->iommufd, idev->devid, + idev->hwpt_id, 0, IOMMU_HWPT_DATA_V= TD_S1, + sizeof(vtd), &vtd, fs_hwpt, errp); +} + +static void vtd_destroy_old_fs_hwpt(HostIOMMUDeviceIOMMUFD *idev, + VTDAddressSpace *vtd_as) +{ + if (!vtd_as->fs_hwpt) { + return; + } + iommufd_backend_free_id(idev->iommufd, vtd_as->fs_hwpt); + vtd_as->fs_hwpt =3D 0; +} + +static int vtd_device_attach_iommufd(VTDHostIOMMUDevice *vtd_hiod, + VTDAddressSpace *vtd_as, Error **errp) +{ + HostIOMMUDeviceIOMMUFD *idev =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->h= iod); + VTDPASIDEntry *pe =3D &vtd_as->pasid_cache_entry.pasid_entry; + uint32_t hwpt_id; + bool ret; + + /* + * We can get here only if flts=3Don, the supported PGTT is FST and PT. + * Catch invalid PGTT when processing invalidation request to avoid + * attaching to wrong hwpt. + */ + if (!vtd_pe_pgtt_is_fst(pe) && !vtd_pe_pgtt_is_pt(pe)) { + error_setg(errp, "Invalid PGTT type"); + return -EINVAL; + } + + if (vtd_pe_pgtt_is_pt(pe)) { + hwpt_id =3D idev->hwpt_id; + } else if (vtd_create_fs_hwpt(idev, pe, &hwpt_id, errp)) { + return -EINVAL; + } + + ret =3D host_iommu_device_iommufd_attach_hwpt(idev, hwpt_id, errp); + trace_vtd_device_attach_hwpt(idev->devid, vtd_as->pasid, hwpt_id, !ret= ); + if (ret) { + /* Destroy old fs_hwpt if it's a replacement */ + vtd_destroy_old_fs_hwpt(idev, vtd_as); + if (vtd_pe_pgtt_is_fst(pe)) { + vtd_as->fs_hwpt =3D hwpt_id; + } + } else if (vtd_pe_pgtt_is_fst(pe)) { + iommufd_backend_free_id(idev->iommufd, hwpt_id); + } + + return !ret; +} + +static int vtd_device_detach_iommufd(VTDHostIOMMUDevice *vtd_hiod, + VTDAddressSpace *vtd_as, Error **errp) +{ + HostIOMMUDeviceIOMMUFD *idev =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->h= iod); + IntelIOMMUState *s =3D vtd_as->iommu_state; + uint32_t pasid =3D vtd_as->pasid; + bool ret; + + if (s->dmar_enabled && s->root_scalable) { + ret =3D host_iommu_device_iommufd_detach_hwpt(idev, errp); + trace_vtd_device_detach_hwpt(idev->devid, pasid, !ret); + } else { + /* + * If DMAR remapping is disabled or guest switches to legacy mode, + * we fallback to the default HWPT which contains shadow page tabl= e. + * So guest DMA could still work. + */ + ret =3D host_iommu_device_iommufd_attach_hwpt(idev, idev->hwpt_id,= errp); + trace_vtd_device_reattach_def_hwpt(idev->devid, pasid, idev->hwpt_= id, + !ret); + } + + if (ret) { + vtd_destroy_old_fs_hwpt(idev, vtd_as); + } + + return !ret; +} + +static int vtd_bind_guest_pasid(VTDAddressSpace *vtd_as, Error **errp) +{ + VTDPASIDCacheEntry *pc_entry =3D &vtd_as->pasid_cache_entry; + VTDHostIOMMUDevice *vtd_hiod =3D vtd_find_hiod_iommufd(vtd_as); + int ret; + + assert(vtd_hiod); + + if (pc_entry->valid) { + ret =3D vtd_device_attach_iommufd(vtd_hiod, vtd_as, errp); + } else { + ret =3D vtd_device_detach_iommufd(vtd_hiod, vtd_as, errp); + } + + return ret; +} +#else +static int vtd_bind_guest_pasid(VTDAddressSpace *vtd_as, Error **errp) +{ + return 0; +} +#endif + /* Do a context-cache device-selective invalidation. * @func_mask: FM field after shifting */ @@ -3131,6 +3254,11 @@ static inline int vtd_dev_get_pe_from_pasid(VTDAddre= ssSpace *vtd_as, return vtd_ce_get_pasid_entry(s, &ce, pe, vtd_as->pasid); } =20 +static int vtd_pasid_entry_compare(VTDPASIDEntry *p1, VTDPASIDEntry *p2) +{ + return memcmp(p1, p2, sizeof(*p1)); +} + /* * For each IOMMUFD backed device, update or invalidate pasid cache based = on * the value in memory. @@ -3143,6 +3271,8 @@ static void vtd_pasid_cache_sync_locked(gpointer key,= gpointer value, VTDPASIDCacheEntry *pc_entry =3D &vtd_as->pasid_cache_entry; VTDPASIDEntry pe; uint16_t did; + const char *err_prefix; + Error *local_err =3D NULL; =20 /* Ignore emulated device or legacy VFIO backed device */ if (!vtd_find_hiod_iommufd(vtd_as)) { @@ -3153,13 +3283,18 @@ static void vtd_pasid_cache_sync_locked(gpointer ke= y, gpointer value, assert(vtd_as->pasid =3D=3D PCI_NO_PASID); =20 if (pc_info->reset || vtd_dev_get_pe_from_pasid(vtd_as, &pe)) { + if (!pc_entry->valid) { + return; + } + /* * No valid pasid entry in guest memory. e.g. pasid entry was modi= fied * to be either all-zero or non-present. Either case means existing * pasid cache should be invalidated. */ pc_entry->valid =3D false; - return; + err_prefix =3D "Detaching from HWPT failed: "; + goto do_bind_unbind; } =20 /* @@ -3184,7 +3319,20 @@ static void vtd_pasid_cache_sync_locked(gpointer key= , gpointer value, } =20 pc_entry->pasid_entry =3D pe; - pc_entry->valid =3D true; + if (!pc_entry->valid) { + pc_entry->valid =3D true; + err_prefix =3D "Attaching to HWPT failed: "; + } else if (vtd_pasid_entry_compare(&pe, &pc_entry->pasid_entry)) { + err_prefix =3D "Replacing HWPT attachment failed: "; + } else { + return; + } + +do_bind_unbind: + /* TODO: Fault event injection into guest, report error to QEMU for no= w */ + if (vtd_bind_guest_pasid(vtd_as, &local_err)) { + error_reportf_err(local_err, "%s", err_prefix); + } } =20 static void vtd_pasid_cache_sync(IntelIOMMUState *s, VTDPASIDCacheInfo *pc= _info) diff --git a/hw/i386/trace-events b/hw/i386/trace-events index b704f4f90c..5a3ee1cf64 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -73,6 +73,9 @@ vtd_warn_invalid_qi_tail(uint16_t tail) "tail 0x%"PRIx16 vtd_warn_ir_vector(uint16_t sid, int index, int vec, int target) "sid 0x%"= PRIx16" index %d vec %d (should be: %d)" vtd_warn_ir_trigger(uint16_t sid, int index, int trig, int target) "sid 0x= %"PRIx16" index %d trigger %d (should be: %d)" vtd_reset_exit(void) "" +vtd_device_attach_hwpt(uint32_t dev_id, uint32_t pasid, uint32_t hwpt_id, = int ret) "dev_id %d pasid %d hwpt_id %d, ret: %d" +vtd_device_detach_hwpt(uint32_t dev_id, uint32_t pasid, int ret) "dev_id %= d pasid %d ret: %d" +vtd_device_reattach_def_hwpt(uint32_t dev_id, uint32_t pasid, uint32_t hwp= t_id, int ret) "dev_id %d pasid %d hwpt_id %d, ret: %d" =20 # amd_iommu.c amdvi_evntlog_fail(uint64_t addr, uint32_t head) "error: fail to write at = addr 0x%"PRIx64" + offset 0x%"PRIx32 --=20 2.47.1