From nobody Sat Nov 15 01:19:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1758122807; cv=none; d=zohomail.com; s=zohoarc; b=n5zMIBwUyhCv3XbW1IqQmxeh80bsMfXHavE4vBOYdrRkPZ91nNAFD4K2Bb5S/08OlL/Js7qTbsOP/zoJ5cPsdlETuoTDpy73kYs1Sbgzs6MlEmOCAKk/GNFZys1BYMa9qsQXySlOOq/2QgPrqMuxufjF1YICWKDZPBUuU5s3+KI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758122807; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=i9GaT3Of/DBpWFzaLmyHMeakmgLz4z1c3ocjxM0NkjY=; b=jUpaKiwOtkLMC1qJpLL7ZcT6QYbJgah0pFQl78110l5/owLb9UhZVIpsr+7dd7R8hhbZErcmVK3AxzO8wfheJ07FZuXFH5nDYn+b9JMT7XHoMhlL8UaOiCJP1YEYazgu1HjgyJBrOxInUpFlxYzaBpy79xGIPEsrxstE8MDku8Q= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758122807405768.9520567316771; Wed, 17 Sep 2025 08:26:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uysy4-00016L-4w; Wed, 17 Sep 2025 10:17:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uysx4-0000tA-Eo for qemu-devel@nongnu.org; Wed, 17 Sep 2025 10:16:12 -0400 Received: from [185.176.79.56] (helo=frasgout.his.huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uysx2-0000VH-8i for qemu-devel@nongnu.org; Wed, 17 Sep 2025 10:16:05 -0400 Received: from mail.maildlp.com (unknown [172.18.186.231]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4cRgg50PMbz6L5gq; Wed, 17 Sep 2025 22:11:29 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id 911771400F4; Wed, 17 Sep 2025 22:16:01 +0800 (CST) Received: from SecurePC-101-06.huawei.com (10.122.19.247) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Wed, 17 Sep 2025 16:16:01 +0200 To: Michael Tsirkin , , CC: , Fan Ni , , , Ravi Shankar Subject: [PATCH qemu for 10.2 4/5] hw/cxl/events: Updates for rev3.2 DRAM event record Date: Wed, 17 Sep 2025 15:13:54 +0100 Message-ID: <20250917141355.293217-5-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250917141355.293217-1-Jonathan.Cameron@huawei.com> References: <20250917141355.293217-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.19.247] X-ClientProxiedBy: lhrpeml100003.china.huawei.com (7.191.160.210) To frapeml500008.china.huawei.com (7.182.85.71) X-Host-Lookup-Failed: Reverse DNS lookup failed for 185.176.79.56 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1758122809419116600 Content-Type: text/plain; charset="utf-8" From: Shiju Jose CXL spec rev3.2 section 8.2.10.2.1.2 Table 8-58, DRAM event record has updated with following new fields. 1. Component Identifier 2. Sub-channel of the memory event location 3. Advanced Programmable Corrected Memory Error Threshold Event Flags 4. Corrected Volatile Memory Error Count at Event 5. Memory Event Sub-Type Add updates for the above spec changes in the CXL DRAM event reporting and QMP command to inject DRAM event. Signed-off-by: Shiju Jose Signed-off-by: Jonathan Cameron --- qapi/cxl.json | 21 ++++++++++++++++++- include/hw/cxl/cxl_events.h | 9 ++++++-- hw/mem/cxl_type3.c | 42 +++++++++++++++++++++++++++++++++++++ hw/mem/cxl_type3_stubs.c | 7 +++++++ 4 files changed, 76 insertions(+), 3 deletions(-) diff --git a/qapi/cxl.json b/qapi/cxl.json index 36a1632dcd..fc22e26ecb 100644 --- a/qapi/cxl.json +++ b/qapi/cxl.json @@ -168,6 +168,21 @@ # @correction-mask: Bits within each nibble. Used in order of bits # set in the nibble-mask. Up to 4 nibbles may be covered. # +# @component-id: Device specific component identifier for the event. +# May describe a field replaceable sub-component of the device. +# +# @is-comp-id-pldm: This flag specifies whether the device-specific +# component identifier format follows PLDM. +# +# @sub-channel: The sub-channel of the memory event location. +# +# @cme-ev-flags: Advanced programmable corrected memory error +# threshold event flags. +# +# @cvme-count: Corrected volatile memory error count at event. +# +# @sub-type: Memory event sub-type. +# # Since: 8.1 ## { 'struct': 'CXLDRAMEvent', @@ -176,7 +191,11 @@ 'type': 'uint8', 'transaction-type': 'uint8', '*channel': 'uint8', '*rank': 'uint8', '*nibble-mask': 'uint32= ', '*bank-group': 'uint8', '*bank': 'uint8', '*row': 'uint32', - '*column': 'uint16', '*correction-mask': [ 'uint64' ] + '*column': 'uint16', '*correction-mask': [ 'uint64' ], + '*component-id': 'str', '*is-comp-id-pldm':'bool', + '*sub-channel':'uint8', + '*cme-ev-flags':'uint8', '*cvme-count':'uint32', + 'sub-type':'uint8' }} =20 ## diff --git a/include/hw/cxl/cxl_events.h b/include/hw/cxl/cxl_events.h index 352f9891bd..a3c5f2ec20 100644 --- a/include/hw/cxl/cxl_events.h +++ b/include/hw/cxl/cxl_events.h @@ -138,7 +138,7 @@ typedef struct CXLEventGenMedia { =20 /* * DRAM Event Record - * CXL r3.1 Section 8.2.9.2.1.2: Table 8-46 + * CXL r3.2 Section 8.2.10.2.1.2: Table 8-58 * All fields little endian. */ typedef struct CXLEventDram { @@ -156,7 +156,12 @@ typedef struct CXLEventDram { uint8_t row[3]; uint16_t column; uint64_t correction_mask[4]; - uint8_t reserved[0x17]; + uint8_t component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE]; + uint8_t sub_channel; + uint8_t cme_ev_flags; + uint8_t cvme_count[3]; + uint8_t sub_type; + uint8_t reserved; } QEMU_PACKED CXLEventDram; =20 /* diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index f1d8c5adcc..96c78b7222 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -1783,6 +1783,13 @@ void qmp_cxl_inject_general_media_event(const char *= path, CxlEventLog log, #define CXL_DRAM_VALID_ROW BIT(5) #define CXL_DRAM_VALID_COLUMN BIT(6) #define CXL_DRAM_VALID_CORRECTION_MASK BIT(7) +#define CXL_DRAM_VALID_COMPONENT BIT(8) +#define CXL_DRAM_VALID_COMPONENT_ID_FORMAT BIT(9) +#define CXL_DRAM_VALID_SUB_CHANNEL BIT(10) + +#define CXL_DRAM_EV_DESC_UCE BIT(0) +#define CXL_DRAM_EV_DESC_THRESHOLD_EVENT BIT(1) +#define CXL_DRAM_EV_DESC_POISON_LIST_OVERFLOW_EVENT BIT(2) =20 void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log, uint32_t flags, @@ -1802,6 +1809,12 @@ void qmp_cxl_inject_dram_event(const char *path, Cxl= EventLog log, bool has_column, uint16_t column, bool has_correction_mask, uint64List *correction_mask, + const char *component_id, + bool has_comp_id_pldm, bool is_comp_id_pldm, + bool has_sub_channel, uint8_t sub_channel, + bool has_cme_ev_flags, uint8_t cme_ev_flags, + bool has_cvme_count, uint32_t cvme_count, + uint8_t sub_type, Error **errp) { Object *obj =3D object_resolve_path(path, NULL); @@ -1888,6 +1901,35 @@ void qmp_cxl_inject_dram_event(const char *path, Cxl= EventLog log, valid_flags |=3D CXL_DRAM_VALID_CORRECTION_MASK; } =20 + if (component_id) { + strncpy((char *)dram.component_id, component_id, + sizeof(dram.component_id) - 1); + valid_flags |=3D CXL_DRAM_VALID_COMPONENT; + if (has_comp_id_pldm && is_comp_id_pldm) { + valid_flags |=3D CXL_DRAM_VALID_COMPONENT_ID_FORMAT; + } + } + + if (has_sub_channel) { + dram.sub_channel =3D sub_channel; + valid_flags |=3D CXL_DRAM_VALID_SUB_CHANNEL; + } + + if (has_cme_ev_flags) { + dram.cme_ev_flags =3D cme_ev_flags; + } else { + dram.cme_ev_flags =3D 0; + } + + if (has_cvme_count) { + descriptor |=3D CXL_DRAM_EV_DESC_THRESHOLD_EVENT; + st24_le_p(dram.cvme_count, cvme_count); + } else { + st24_le_p(dram.cvme_count, 0); + } + + dram.sub_type =3D sub_type; + stw_le_p(&dram.validity_flags, valid_flags); =20 if (cxl_event_insert(cxlds, enc_log, (CXLEventRecordRaw *)&dram)) { diff --git a/hw/mem/cxl_type3_stubs.c b/hw/mem/cxl_type3_stubs.c index 2047e97846..231dda263f 100644 --- a/hw/mem/cxl_type3_stubs.c +++ b/hw/mem/cxl_type3_stubs.c @@ -53,6 +53,13 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEven= tLog log, bool has_column, uint16_t column, bool has_correction_mask, uint64List *correction_mask, + const char *component_id, + bool has_comp_id_pldm, + bool is_comp_id_pldm, + bool has_sub_channel, uint8_t sub_channel, + bool has_cme_ev_flags, uint8_t cme_ev_flags, + bool has_cvme_count, uint32_t cvme_count, + uint8_t sub_type, Error **errp) {} =20 void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log, --=20 2.48.1