From nobody Sat Nov 15 01:22:05 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1758072790; cv=none; d=zohomail.com; s=zohoarc; b=VEMleh9MrdUu+kkOFWJelmot2BMsh3rRIa2W0n82c7Yk7fbGsnh70WFZWDC8GyLl2B4cpkq/hD/pqwrRaCeci/324s1AS1liHFTIONVRmR0IIcfKRixkQdQNWwXq+il93cj6WccBjchH7AOF/kVfQuKLGIj9C4N2LeT9tnH9pi8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758072790; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=ivSfwuGAkKhG2Nt1AIOPhcRWsyz1Be+7+TJxdoDQ9DM=; b=Perl5xstWDDfUB5k7KX/l6Nfq+BKLoLQKMlJltIU2CWI3sCakNqnVrzidvjFjmL3sApaE3oBCzfaQ0bTq2Oo99T+cmQCkwRCd/5nup9ZA8EvHY/o5x3zGzawGdk+Og+cCh4Ta5Hauh22Zj3JFgu2+RCsaZscYi9ZJt3AL8tvJvE= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758072790325232.0399401875991; Tue, 16 Sep 2025 18:33:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uyh20-0006Ic-Tn; Tue, 16 Sep 2025 21:32:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uyh1y-0006Hh-TV; Tue, 16 Sep 2025 21:32:23 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uyh1w-0006vf-KY; Tue, 16 Sep 2025 21:32:22 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 17 Sep 2025 09:31:45 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 17 Sep 2025 09:31:45 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v1 6/6] hw/arm/aspeed: Model AST1700 IO expander I2C on AST27x0 Date: Wed, 17 Sep 2025 09:31:41 +0800 Message-ID: <20250917013143.1600377-7-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250917013143.1600377-1-kane_chen@aspeedtech.com> References: <20250917013143.1600377-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1758072792219116600 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS Each AST1700 IO expander integrates a multi-function I2C controller with 16 buses. Model this controller in the AST1700 child and expose its MMIO on AST27x0 machines. Addressing: - slot 0 (IO0): 0x30000000 + 0x00C0F000 =3D 0x30C0F000 - slot 1 (IO1): 0x50000000 + 0x00C0F000 =3D 0x50C0F000 Interrupts: - add IO expander I2C interrupt sources and connect per-bus IRQs (bits 0-15) to the AST27x0 interrupt fabric, following the same fan-out used by on-SoC I2C. Each AST1700 I2C bus i emits one IRQ which is wired via ASPEED_DEV_IOEXP{0,1}_I2C index i. Enumeration: - the on-SoC AST27x0 exposes 16 I2C adapters (i2c-0 ~ i2c-15) - first AST1700 expands to i2c-16 ~ i2c-31 - second AST1700 expands to i2c-32 ~ i2c-47 Signed-off-by: Kane-Chen-AS --- include/hw/arm/aspeed_soc.h | 2 + hw/arm/aspeed_ast27x0.c | 73 +++++++++++++++++++++++++++++++++++-- 2 files changed, 71 insertions(+), 4 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 290bb7a6cf..c1702c96e3 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -307,6 +307,8 @@ enum { ASPEED_DEV_IPC1, ASPEED_DEV_LTPI_CTRL1, ASPEED_DEV_LTPI_CTRL2, + ASPEED_DEV_IOEXP0_I2C, + ASPEED_DEV_IOEXP1_I2C, ASPEED_DEV_IOEXP0_INTCIO, ASPEED_DEV_IOEXP1_INTCIO, }; diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index d192534e9e..5f54858046 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -201,6 +201,8 @@ static const int aspeed_soc_ast2700a1_irqmap[] =3D { [ASPEED_DEV_ETH3] =3D 196, [ASPEED_DEV_PECI] =3D 197, [ASPEED_DEV_SDHCI] =3D 197, + [ASPEED_DEV_IOEXP0_I2C] =3D 198, + [ASPEED_DEV_IOEXP1_I2C] =3D 200, }; =20 /* GICINT 128 */ @@ -260,6 +262,28 @@ static const int ast2700_gic133_gic197_intcmap[] =3D { [ASPEED_DEV_PECI] =3D 4, }; =20 +/* Primary AST1700 Interrupts */ +/* A1: GICINT 198 */ +static const int ast2700_gic198_intcmap[] =3D { + [ASPEED_DEV_IOEXP0_I2C] =3D 0, /* 0 - 15 */ +}; + +/* Primary AST1700 Interrupts */ +/* A1: GINTC 199 */ +static const int ast2700_gic199_intcmap[] =3D { +}; + +/* Secondary AST1700 Interrupts */ +/* A1: GINTC 200 */ +static const int ast2700_gic200_intcmap[] =3D { + [ASPEED_DEV_IOEXP1_I2C] =3D 0, /* 0 - 15 */ +}; + +/* Secondary AST1700 Interrupts */ +/* A1: GINTC 201 */ +static const int ast2700_gic201_intcmap[] =3D { +}; + /* GICINT 128 ~ 136 */ /* GICINT 192 ~ 201 */ struct gic_intc_irq_info { @@ -276,10 +300,10 @@ static const struct gic_intc_irq_info ast2700_gic_int= cmap[] =3D { {195, 1, 3, ast2700_gic131_gic195_intcmap}, {196, 1, 4, ast2700_gic132_gic196_intcmap}, {197, 1, 5, ast2700_gic133_gic197_intcmap}, - {198, 1, 6, NULL}, - {199, 1, 7, NULL}, - {200, 1, 8, NULL}, - {201, 1, 9, NULL}, + {198, 2, 0, ast2700_gic198_intcmap}, + {199, 2, 1, ast2700_gic199_intcmap}, + {200, 3, 0, ast2700_gic200_intcmap}, + {201, 3, 1, ast2700_gic201_intcmap}, {128, 0, 1, ast2700_gic128_gic192_intcmap}, {129, 0, 2, NULL}, {130, 0, 3, ast2700_gic130_gic194_intcmap}, @@ -557,8 +581,18 @@ static void aspeed_soc_ast2700_init(Object *obj) =20 static void aspeed_ast2700_ast1700_init(AspeedSoCState *s, int i) { + char socname[8]; + char typename[64]; + + if (sscanf(object_get_typename(OBJECT(s)), "%7s", socname) !=3D 1) { + g_assert_not_reached(); + } + object_initialize_child(OBJECT(s), "uart[*]", &s->ioexp[i].uart, TYPE_SERIAL_MM); + snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); + object_initialize_child(OBJECT(s), "ioexp-i2c[*]", &s->ioexp[i].i2c, + typename); object_initialize_child(OBJECT(s), "ltpi-ctrl[*]", &s->ltpi_ctrl[i], TYPE_ASPEED_LTPI); } @@ -652,8 +686,11 @@ static void aspeed_soc_ast2700_ast1700_realize(Aspeed2= 7x0SoCState *a, int i; hwaddr uart_base =3D sc->memmap[ASPEED_DEV_LTPI_IO0 + index] + aspeed_soc_ast1700_memmap[ASPEED_DEV_UART12]; + AspeedI2CClass *i2c_ctl =3D ASPEED_I2C_GET_CLASS(&s->ioexp[index].i2c); AspeedLTPIState *ltpi_ctrl =3D ASPEED_LTPI(&s->ltpi_ctrl[index]); hwaddr ltpi_base =3D sc->memmap[ASPEED_DEV_LTPI_CTRL1 + index]; + qemu_irq irq; + smm =3D &s->ioexp[index].uart; =20 /* Chardev property is set by the machine. */ @@ -683,6 +720,34 @@ static void aspeed_soc_ast2700_ast1700_realize(Aspeed2= 7x0SoCState *a, } =20 aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, uart_base); + + /* I2C */ + object_property_set_link(OBJECT(&s->ioexp[index].i2c), "dram", + OBJECT(s->dram_mr), &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->ioexp[index].i2c), errp)) { + return; + } + aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ioexp[index].i2c), 0, + sc->memmap[ASPEED_DEV_LTPI_IO0 + index] + + aspeed_soc_ast1700_memmap[ASPEED_DEV_I2C]); + for (i =3D 0; i < i2c_ctl->num_busses; i++) { + /* + * For I2C on AST1700: + * I2C bus interrupts are connected to the OR gate from bit 0 to b= it + * 15, and the OR gate output pin is connected to the input pin of + * GICINT192 of IO expander Interrupt controller (INTC2/3). Then, + * the output pin is connected to the INTC (CPU Die) input pin, and + * its output pin is connected to the GIC. + * + * I2C bus 0 is connected to the OR gate at bit 0. + * I2C bus 15 is connected to the OR gate at bit 15. + */ + irq =3D aspeed_soc_ast2700_get_irq_index(s, + ASPEED_DEV_IOEXP0_I2C + ind= ex, + i); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[index].i2c.busses[i]), + 0, irq); + } } =20 static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) --=20 2.43.0