From nobody Sat Nov 15 01:23:23 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1758072879; cv=none; d=zohomail.com; s=zohoarc; b=XlQoZeM3VFmwHzXu1x9sdsecb7MU+4XaEAHWxI4AyVEjYPcoST0j5NCz1LLaVYrUV6OAhUBjtRREFg34si0yOnzVOrynEujbTUayrX82T03XBcApHtdFNTPoC/7WjxfmYb2g7fNe5qMnALLu5kYgkRyCbLBr85Jika5c4AX3UCM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758072879; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=e9Zfue+UmTGiH2eOxTo1yzhYMdLlPWATIolG+t8osOE=; b=SBDx8ejY8681WWOSPZPSkf51c6IyRNvHfzALrmEY9vZgmQ1m8ZMCr0Nbc88ic03Ks+7bq52Xb1+OEFSgHL+XcWzu79zPLd0Jtit/Q2Aib6XEIk+h7qM47uE+re4FgSBjq+w+R0WGvgGl0u0WIjQXySUKcAzp//BWN1vkEytpHqU= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758072879159439.7477961255893; Tue, 16 Sep 2025 18:34:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uyh1y-0006HO-DQ; Tue, 16 Sep 2025 21:32:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uyh1v-0006Fj-Lj; Tue, 16 Sep 2025 21:32:19 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uyh1t-0006vf-6e; Tue, 16 Sep 2025 21:32:19 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 17 Sep 2025 09:31:45 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 17 Sep 2025 09:31:45 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v1 5/6] hw/arm/aspeed: Model AST1700 IO expander interrupt controllers on AST27x0 Date: Wed, 17 Sep 2025 09:31:40 +0800 Message-ID: <20250917013143.1600377-6-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250917013143.1600377-1-kane_chen@aspeedtech.com> References: <20250917013143.1600377-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1758072881220116600 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS AST27x0 boards may host up to two AST1700 IO expander cards. Model the per-expander interrupt controller (INTCIO) instances and map their MMIO windows in the SoC. This reserves the IO expander interrupt controller address space so that firmware can later route and handle interrupts for AST1700-based boards. Signed-off-by: Kane-Chen-AS --- include/hw/arm/aspeed_soc.h | 4 ++- include/hw/intc/aspeed_intc.h | 2 ++ hw/arm/aspeed_ast27x0.c | 37 +++++++++++++++++++++ hw/intc/aspeed_intc.c | 60 +++++++++++++++++++++++++++++++++++ 4 files changed, 102 insertions(+), 1 deletion(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 648c8d5c00..290bb7a6cf 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -151,7 +151,7 @@ struct Aspeed27x0SoCState { AspeedSoCState parent; =20 ARMCPU cpu[ASPEED_CPUS_NUM]; - AspeedINTCState intc[2]; + AspeedINTCState intc[4]; GICv3State gic; MemoryRegion dram_empty; }; @@ -307,6 +307,8 @@ enum { ASPEED_DEV_IPC1, ASPEED_DEV_LTPI_CTRL1, ASPEED_DEV_LTPI_CTRL2, + ASPEED_DEV_IOEXP0_INTCIO, + ASPEED_DEV_IOEXP1_INTCIO, }; =20 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev); diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h index 51288384a5..4565bbab84 100644 --- a/include/hw/intc/aspeed_intc.h +++ b/include/hw/intc/aspeed_intc.h @@ -15,6 +15,8 @@ #define TYPE_ASPEED_INTC "aspeed.intc" #define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700" #define TYPE_ASPEED_2700_INTCIO TYPE_ASPEED_INTC "io-ast2700" +#define TYPE_ASPEED_2700_INTCIOEXP1 TYPE_ASPEED_INTC "ast2700-ioexp1" +#define TYPE_ASPEED_2700_INTCIOEXP2 TYPE_ASPEED_INTC "ast2700-ioexp2" #define TYPE_ASPEED_2700SSP_INTC TYPE_ASPEED_INTC "-ast2700ssp" #define TYPE_ASPEED_2700SSP_INTCIO TYPE_ASPEED_INTC "io-ast2700ssp" #define TYPE_ASPEED_2700TSP_INTC TYPE_ASPEED_INTC "-ast2700tsp" diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index d63a331c0a..d192534e9e 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -84,7 +84,9 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D { [ASPEED_DEV_LTPI_CTRL2] =3D 0x14C35000, [ASPEED_DEV_WDT] =3D 0x14C37000, [ASPEED_DEV_LTPI_IO0] =3D 0x30000000, + [ASPEED_DEV_IOEXP0_INTCIO] =3D 0x30C18000, [ASPEED_DEV_LTPI_IO1] =3D 0x50000000, + [ASPEED_DEV_IOEXP1_INTCIO] =3D 0x50C18000, [ASPEED_DEV_SPI_BOOT] =3D 0x100000000, [ASPEED_DEV_SDRAM] =3D 0x400000000, }; @@ -504,6 +506,10 @@ static void aspeed_soc_ast2700_init(Object *obj) object_initialize_child(obj, "intc", &a->intc[0], TYPE_ASPEED_2700_INT= C); object_initialize_child(obj, "intcio", &a->intc[1], TYPE_ASPEED_2700_INTCIO); + object_initialize_child(obj, "intcioexp0", &a->intc[2], + TYPE_ASPEED_2700_INTCIOEXP1); + object_initialize_child(obj, "intcioexp1", &a->intc[3], + TYPE_ASPEED_2700_INTCIOEXP2); =20 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); object_initialize_child(obj, "adc", &s->adc, typename); @@ -642,6 +648,8 @@ static void aspeed_soc_ast2700_ast1700_realize(Aspeed27= x0SoCState *a, int index, Error **errp) { SerialMM *smm; + AspeedINTCClass *icio =3D ASPEED_INTC_GET_CLASS(&a->intc[2 + index]); + int i; hwaddr uart_base =3D sc->memmap[ASPEED_DEV_LTPI_IO0 + index] + aspeed_soc_ast1700_memmap[ASPEED_DEV_UART12]; AspeedLTPIState *ltpi_ctrl =3D ASPEED_LTPI(&s->ltpi_ctrl[index]); @@ -661,6 +669,19 @@ static void aspeed_soc_ast2700_ast1700_realize(Aspeed2= 7x0SoCState *a, return; } aspeed_mmio_map(s, SYS_BUS_DEVICE(ltpi_ctrl), 0, ltpi_base); + + /* INTC2/3 internal: orgate[i] -> input[i] */ + for (i =3D 0; i < icio->num_inpins; i++) { + qdev_connect_gpio_out(DEVICE(&a->intc[2 + index].orgates[i]), 0, + qdev_get_gpio_in(DEVICE(&a->intc[2 + index])= , i)); + } + + /* INTC2/3 output[i] -> INTC0.orgate[0].input[i] */ + for (i =3D 0; i < icio->num_outpins; i++) { + sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[2 + index]), i, + qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0])= , i)); + } + aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, uart_base); } =20 @@ -717,6 +738,22 @@ static void aspeed_soc_ast2700_realize(DeviceState *de= v, Error **errp) aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[1]), 0, sc->memmap[ASPEED_DEV_INTCIO]); =20 + /* INTCIOEXP0 */ + if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[2]), errp)) { + return; + } + + aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[2]), 0, + sc->memmap[ASPEED_DEV_IOEXP0_INTCIO]); + + /* INTCIOEXP */ + if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[3]), errp)) { + return; + } + + aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[3]), 0, + sc->memmap[ASPEED_DEV_IOEXP1_INTCIO]); + /* irq sources -> orgates -> INTC */ for (i =3D 0; i < ic->num_inpins; i++) { qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0, diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c index 5cd786dee6..a04005ee7c 100644 --- a/hw/intc/aspeed_intc.c +++ b/hw/intc/aspeed_intc.c @@ -924,6 +924,64 @@ static const TypeInfo aspeed_2700_intc_info =3D { .class_init =3D aspeed_2700_intc_class_init, }; =20 +static AspeedINTCIRQ aspeed_2700_intcioexp2_irqs[ASPEED_INTC_MAX_INPINS] = =3D { + {0, 8, 1, R_GICINT192_EN, R_GICINT192_STATUS}, + {1, 9, 1, R_GICINT193_EN, R_GICINT193_STATUS}, +}; + +static void aspeed_2700_intcioexp2_class_init(ObjectClass *klass, + const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + AspeedINTCClass *aic =3D ASPEED_INTC_CLASS(klass); + + dc->desc =3D "ASPEED 2700 IOEXP2 INTC Controller"; + aic->num_lines =3D 32; + aic->num_inpins =3D 2; + aic->num_outpins =3D 10; + aic->mem_size =3D 0x400; + aic->nr_regs =3D 0x58 >> 2; + aic->reg_offset =3D 0x100; + aic->reg_ops =3D &aspeed_intcio_ops; + aic->irq_table =3D aspeed_2700_intcioexp2_irqs; + aic->irq_table_count =3D ARRAY_SIZE(aspeed_2700_intcioexp2_irqs); +} + +static const TypeInfo aspeed_2700_intcioexp2_info =3D { + .name =3D TYPE_ASPEED_2700_INTCIOEXP2, + .parent =3D TYPE_ASPEED_INTC, + .class_init =3D aspeed_2700_intcioexp2_class_init, +}; + +static AspeedINTCIRQ aspeed_2700_intcioexp1_irqs[ASPEED_INTC_MAX_INPINS] = =3D { + {0, 6, 1, R_GICINT192_EN, R_GICINT192_STATUS}, + {1, 7, 1, R_GICINT193_EN, R_GICINT193_STATUS}, +}; + +static void aspeed_2700_intcioexp1_class_init(ObjectClass *klass, + const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + AspeedINTCClass *aic =3D ASPEED_INTC_CLASS(klass); + + dc->desc =3D "ASPEED 2700 IOEXP1 INTC Controller"; + aic->num_lines =3D 32; + aic->num_inpins =3D 2; + aic->num_outpins =3D 10; + aic->mem_size =3D 0x400; + aic->nr_regs =3D 0x58 >> 2; + aic->reg_offset =3D 0x100; + aic->reg_ops =3D &aspeed_intcio_ops; + aic->irq_table =3D aspeed_2700_intcioexp1_irqs; + aic->irq_table_count =3D ARRAY_SIZE(aspeed_2700_intcioexp1_irqs); +} + +static const TypeInfo aspeed_2700_intcioexp1_info =3D { + .name =3D TYPE_ASPEED_2700_INTCIOEXP1, + .parent =3D TYPE_ASPEED_INTC, + .class_init =3D aspeed_2700_intcioexp1_class_init, +}; + static AspeedINTCIRQ aspeed_2700_intcio_irqs[ASPEED_INTC_MAX_INPINS] =3D { {0, 0, 1, R_GICINT192_EN, R_GICINT192_STATUS}, {1, 1, 1, R_GICINT193_EN, R_GICINT193_STATUS}, @@ -1099,6 +1157,8 @@ static void aspeed_intc_register_types(void) type_register_static(&aspeed_intc_info); type_register_static(&aspeed_2700_intc_info); type_register_static(&aspeed_2700_intcio_info); + type_register_static(&aspeed_2700_intcioexp1_info); + type_register_static(&aspeed_2700_intcioexp2_info); type_register_static(&aspeed_2700ssp_intc_info); type_register_static(&aspeed_2700ssp_intcio_info); type_register_static(&aspeed_2700tsp_intc_info); --=20 2.43.0