From nobody Sat Nov 15 01:23:23 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1758072906; cv=none; d=zohomail.com; s=zohoarc; b=GMk7TvZs+JtEvczHOkjHga8rq/Ja1+EB+XHJ5wL4mISOstIpRE2zdw5kS3ZgPAYn7IqvVx5xmjXYQxJIyodO0BFKQzoQmwr36t8pyXiYfYvINXgvP+5ZPki8eVlFNiiCItyDhztrzU/g06zuDx+SxOHGWJ5aAqgOrqO5RYBJCnU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758072906; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=0GWYHPrFOpPiizSPq6yjFK+j5kfemur3bxnnE7716kw=; b=Njt62sfgSmmjyeh/LWTSg2Fac9YdX+u8jzJ84yOfbp/XsWwZ32H/9DVddd374+0n8StcpVDBij2UrDn+fwt0ewhdu2SlMvlPeLnBeIazHTRJFYIDhTFLF6or7rF1vPe+Y8AsOS6D+pCinHS1I44UM6rJ/eIF5Ve5ppd+JZaUyw8= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175807290621760.26835923369106; Tue, 16 Sep 2025 18:35:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uyh1u-0006Ej-AR; Tue, 16 Sep 2025 21:32:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uyh1q-0006D9-U3; Tue, 16 Sep 2025 21:32:16 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uyh1o-0006vf-NC; Tue, 16 Sep 2025 21:32:14 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 17 Sep 2025 09:31:44 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 17 Sep 2025 09:31:44 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v1 4/6] hw/arm/aspeed: Model AST1700 IO expander UART on AST27x0 Date: Wed, 17 Sep 2025 09:31:39 +0800 Message-ID: <20250917013143.1600377-5-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250917013143.1600377-1-kane_chen@aspeedtech.com> References: <20250917013143.1600377-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1758072907203116600 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS AST1700 IO expander boards carry a serial-mm UART. Model this device in the AST1700 child and expose it via the AST1700 MMIO map (UART12 at offset 0x00C33B00) on AST27x0 machines. Addressing: - slot 0 (IO0): 0x30000000 + 0x00C33B00 =3D 0x30C33B00 - slot 1 (IO1): 0x50000000 + 0x00C33B00 =3D 0x50C33B00 Signed-off-by: Kane-Chen-AS --- hw/arm/aspeed_ast27x0.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 2e180c8cc5..d63a331c0a 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -89,6 +89,19 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D { [ASPEED_DEV_SDRAM] =3D 0x400000000, }; =20 +static const hwaddr aspeed_soc_ast1700_memmap[] =3D { + [ASPEED_DEV_PWM] =3D 0x000C0000, + [ASPEED_DEV_SRAM] =3D 0x00BC0000, + [ASPEED_DEV_ADC] =3D 0x00C00000, + [ASPEED_DEV_SCU] =3D 0x00C02000, + [ASPEED_DEV_GPIO] =3D 0x00C0B000, + [ASPEED_DEV_I2C] =3D 0x00C0F000, + [ASPEED_DEV_I3C] =3D 0x00C20000, + [ASPEED_DEV_UART12] =3D 0x00C33B00, + [ASPEED_DEV_WDT] =3D 0x00C37000, + [ASPEED_DEV_SPI_BOOT] =3D 0x04000000, +}; + #define AST2700_MAX_IRQ 256 =20 /* Shared Peripheral Interrupt values below are offset by -32 from datashe= et */ @@ -538,6 +551,8 @@ static void aspeed_soc_ast2700_init(Object *obj) =20 static void aspeed_ast2700_ast1700_init(AspeedSoCState *s, int i) { + object_initialize_child(OBJECT(s), "uart[*]", &s->ioexp[i].uart, + TYPE_SERIAL_MM); object_initialize_child(OBJECT(s), "ltpi-ctrl[*]", &s->ltpi_ctrl[i], TYPE_ASPEED_LTPI); } @@ -626,13 +641,27 @@ static void aspeed_soc_ast2700_ast1700_realize(Aspeed= 27x0SoCState *a, AspeedSoCClass *sc, int index, Error **errp) { + SerialMM *smm; + hwaddr uart_base =3D sc->memmap[ASPEED_DEV_LTPI_IO0 + index] + + aspeed_soc_ast1700_memmap[ASPEED_DEV_UART12]; AspeedLTPIState *ltpi_ctrl =3D ASPEED_LTPI(&s->ltpi_ctrl[index]); hwaddr ltpi_base =3D sc->memmap[ASPEED_DEV_LTPI_CTRL1 + index]; + smm =3D &s->ioexp[index].uart; + + /* Chardev property is set by the machine. */ + qdev_prop_set_uint8(DEVICE(smm), "regshift", 2); + qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400); + qdev_set_legacy_instance_id(DEVICE(smm), uart_base, 2); + qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN); + if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) { + return; + } =20 if (!sysbus_realize(SYS_BUS_DEVICE(ltpi_ctrl), errp)) { return; } aspeed_mmio_map(s, SYS_BUS_DEVICE(ltpi_ctrl), 0, ltpi_base); + aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, uart_base); } =20 static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) --=20 2.43.0