From nobody Sat Nov 15 01:22:05 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1758072809; cv=none; d=zohomail.com; s=zohoarc; b=hYjekyd6Utwlb+mFMwjrbWTZULF1AMpsEqfdzjxY+raJ8qn640cwCjkuNSodGh0TmNZJdF1oR+JngWk8D+Wb7k9ceMkcKbJFnI+hOyU3VpIHK3vpFwOJi5mb6kLNlEA+mC4NxoPtaClEA9J6FB8Tlfj5WcH30gw0ZNnV/SwLiP4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758072809; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=RsWA/15A5tN8CfvPiii13SRy+q/3Gbq9gyBh4d+aj8I=; b=UQJMW69cjBKMw9fuAwXYJajnn0Vjjqp78VRRxdSnPyHXKQR0tPTkvi2V3rPsbnW84LsWgwdMxe6xVnqN+MOsPvA7P3pdFHER4MeXKRQoG05d+W/Wl/hMqNRxpzq84f8ncN0Kh4VGr57CwxdXYTIcKiEdCzSAobQBAWtAfaLPyik= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758072809527380.53484212095486; Tue, 16 Sep 2025 18:33:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uyh1j-0006AS-Aq; Tue, 16 Sep 2025 21:32:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uyh1f-00068g-Ci; Tue, 16 Sep 2025 21:32:03 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uyh1c-0006vf-SU; Tue, 16 Sep 2025 21:32:02 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 17 Sep 2025 09:31:44 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 17 Sep 2025 09:31:44 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v1 1/6] hw/arm/aspeed: Add 'ioexps-num' property for AST27x0 Date: Wed, 17 Sep 2025 09:31:36 +0800 Message-ID: <20250917013143.1600377-2-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250917013143.1600377-1-kane_chen@aspeedtech.com> References: <20250917013143.1600377-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1758072810766116600 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS AST27x0 platforms can attach up to two AST1700 IO expander boards. Introduce the 'ioexps-num' property to let users specify how many IO expanders to instantiate for a given machine. This enables modeling board variants that ship with 0-2 expanders. Note: AST2500 and AST2600 do not support IO expanders; this property is only available on AST27x0 machines. Command usage: ``` ./qemu-system-aarch64 -M ast2700a1-evb,ioexps-num=3D2 \ -drive image-bmc,format=3Draw,if=3Dmtd \ ... ``` Signed-off-by: Kane-Chen-AS --- include/hw/arm/aspeed_soc.h | 2 ++ hw/arm/aspeed.c | 49 +++++++++++++++++++++++++++++++++++++ 2 files changed, 51 insertions(+) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 217ef0eafd..77263cc6ec 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -49,6 +49,7 @@ #define ASPEED_MACS_NUM 4 #define ASPEED_UARTS_NUM 13 #define ASPEED_JTAG_NUM 2 +#define ASPEED_IOEXP_NUM 2 =20 struct AspeedSoCState { DeviceState parent; @@ -103,6 +104,7 @@ struct AspeedSoCState { UnimplementedDeviceState ltpi; UnimplementedDeviceState jtag[ASPEED_JTAG_NUM]; AspeedAPB2OPBState fsi[2]; + uint8_t ioexp_num; }; =20 #define TYPE_ASPEED_SOC "aspeed-soc" diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index c31bbe7701..593cb87bfe 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -32,6 +32,7 @@ #include "qemu/units.h" #include "hw/qdev-clock.h" #include "system/system.h" +#include "qapi/visitor.h" =20 static struct arm_boot_info aspeed_board_binfo =3D { .board_id =3D -1, /* device-tree-only board */ @@ -49,6 +50,7 @@ struct AspeedMachineState { char *fmc_model; char *spi_model; uint32_t hw_strap1; + uint32_t ioexp_num; }; =20 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */ @@ -444,6 +446,9 @@ static void aspeed_machine_init(MachineState *machine) OBJECT(get_system_memory()), &error_abort); object_property_set_link(OBJECT(bmc->soc), "dram", OBJECT(machine->ram), &error_abort); + + bmc->soc->ioexp_num =3D bmc->ioexp_num; + if (amc->sdhci_wp_inverted) { for (i =3D 0; i < bmc->soc->sdhci.num_slots; i++) { object_property_set_bool(OBJECT(&bmc->soc->sdhci.slots[i]), @@ -1486,6 +1491,49 @@ static void aspeed_machine_ast2600_class_emmc_init(O= bjectClass *oc) "Set or unset boot from EMMC"); } =20 +#ifdef TARGET_AARCH64 +static void aspeed_get_ioexps_num(Object *obj, + Visitor *v, + const char *name, + void *opaque, + Error **errp) +{ + AspeedMachineState *bmc =3D ASPEED_MACHINE(obj); + + visit_type_uint32(v, name, &bmc->ioexp_num, errp); +} + +static void aspeed_set_ioexps_num(Object *obj, + Visitor *v, + const char *name, + void *opaque, + Error **errp) +{ + uint32_t val; + AspeedMachineState *bmc =3D ASPEED_MACHINE(obj); + + if (!visit_type_uint32(v, name, &val, errp)) { + return; + } + + if (val > ASPEED_IOEXP_NUM) { + error_setg(errp, "IOEXP number is exceeded: %d", val); + return; + } + + bmc->ioexp_num =3D val; +} + + +static void aspeed_machine_ast1700_class_init(ObjectClass *oc) +{ + object_class_property_add(oc, "ioexps-num", "uint32", + aspeed_get_ioexps_num, + aspeed_set_ioexps_num, + NULL, NULL); +} +#endif + static void aspeed_machine_class_init(ObjectClass *oc, const void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); @@ -2032,6 +2080,7 @@ static void aspeed_machine_ast2700a1_evb_class_init(O= bjectClass *oc, mc->auto_create_sdcard =3D true; mc->default_ram_size =3D 1 * GiB; aspeed_machine_class_init_cpus_defaults(mc); + aspeed_machine_ast1700_class_init(oc); } #endif =20 --=20 2.43.0