From nobody Sat Nov 15 00:46:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1758072809; cv=none; d=zohomail.com; s=zohoarc; b=hYjekyd6Utwlb+mFMwjrbWTZULF1AMpsEqfdzjxY+raJ8qn640cwCjkuNSodGh0TmNZJdF1oR+JngWk8D+Wb7k9ceMkcKbJFnI+hOyU3VpIHK3vpFwOJi5mb6kLNlEA+mC4NxoPtaClEA9J6FB8Tlfj5WcH30gw0ZNnV/SwLiP4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758072809; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=RsWA/15A5tN8CfvPiii13SRy+q/3Gbq9gyBh4d+aj8I=; b=UQJMW69cjBKMw9fuAwXYJajnn0Vjjqp78VRRxdSnPyHXKQR0tPTkvi2V3rPsbnW84LsWgwdMxe6xVnqN+MOsPvA7P3pdFHER4MeXKRQoG05d+W/Wl/hMqNRxpzq84f8ncN0Kh4VGr57CwxdXYTIcKiEdCzSAobQBAWtAfaLPyik= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758072809527380.53484212095486; Tue, 16 Sep 2025 18:33:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uyh1j-0006AS-Aq; Tue, 16 Sep 2025 21:32:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uyh1f-00068g-Ci; Tue, 16 Sep 2025 21:32:03 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uyh1c-0006vf-SU; Tue, 16 Sep 2025 21:32:02 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 17 Sep 2025 09:31:44 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 17 Sep 2025 09:31:44 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v1 1/6] hw/arm/aspeed: Add 'ioexps-num' property for AST27x0 Date: Wed, 17 Sep 2025 09:31:36 +0800 Message-ID: <20250917013143.1600377-2-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250917013143.1600377-1-kane_chen@aspeedtech.com> References: <20250917013143.1600377-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1758072810766116600 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS AST27x0 platforms can attach up to two AST1700 IO expander boards. Introduce the 'ioexps-num' property to let users specify how many IO expanders to instantiate for a given machine. This enables modeling board variants that ship with 0-2 expanders. Note: AST2500 and AST2600 do not support IO expanders; this property is only available on AST27x0 machines. Command usage: ``` ./qemu-system-aarch64 -M ast2700a1-evb,ioexps-num=3D2 \ -drive image-bmc,format=3Draw,if=3Dmtd \ ... ``` Signed-off-by: Kane-Chen-AS --- include/hw/arm/aspeed_soc.h | 2 ++ hw/arm/aspeed.c | 49 +++++++++++++++++++++++++++++++++++++ 2 files changed, 51 insertions(+) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 217ef0eafd..77263cc6ec 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -49,6 +49,7 @@ #define ASPEED_MACS_NUM 4 #define ASPEED_UARTS_NUM 13 #define ASPEED_JTAG_NUM 2 +#define ASPEED_IOEXP_NUM 2 =20 struct AspeedSoCState { DeviceState parent; @@ -103,6 +104,7 @@ struct AspeedSoCState { UnimplementedDeviceState ltpi; UnimplementedDeviceState jtag[ASPEED_JTAG_NUM]; AspeedAPB2OPBState fsi[2]; + uint8_t ioexp_num; }; =20 #define TYPE_ASPEED_SOC "aspeed-soc" diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index c31bbe7701..593cb87bfe 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -32,6 +32,7 @@ #include "qemu/units.h" #include "hw/qdev-clock.h" #include "system/system.h" +#include "qapi/visitor.h" =20 static struct arm_boot_info aspeed_board_binfo =3D { .board_id =3D -1, /* device-tree-only board */ @@ -49,6 +50,7 @@ struct AspeedMachineState { char *fmc_model; char *spi_model; uint32_t hw_strap1; + uint32_t ioexp_num; }; =20 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */ @@ -444,6 +446,9 @@ static void aspeed_machine_init(MachineState *machine) OBJECT(get_system_memory()), &error_abort); object_property_set_link(OBJECT(bmc->soc), "dram", OBJECT(machine->ram), &error_abort); + + bmc->soc->ioexp_num =3D bmc->ioexp_num; + if (amc->sdhci_wp_inverted) { for (i =3D 0; i < bmc->soc->sdhci.num_slots; i++) { object_property_set_bool(OBJECT(&bmc->soc->sdhci.slots[i]), @@ -1486,6 +1491,49 @@ static void aspeed_machine_ast2600_class_emmc_init(O= bjectClass *oc) "Set or unset boot from EMMC"); } =20 +#ifdef TARGET_AARCH64 +static void aspeed_get_ioexps_num(Object *obj, + Visitor *v, + const char *name, + void *opaque, + Error **errp) +{ + AspeedMachineState *bmc =3D ASPEED_MACHINE(obj); + + visit_type_uint32(v, name, &bmc->ioexp_num, errp); +} + +static void aspeed_set_ioexps_num(Object *obj, + Visitor *v, + const char *name, + void *opaque, + Error **errp) +{ + uint32_t val; + AspeedMachineState *bmc =3D ASPEED_MACHINE(obj); + + if (!visit_type_uint32(v, name, &val, errp)) { + return; + } + + if (val > ASPEED_IOEXP_NUM) { + error_setg(errp, "IOEXP number is exceeded: %d", val); + return; + } + + bmc->ioexp_num =3D val; +} + + +static void aspeed_machine_ast1700_class_init(ObjectClass *oc) +{ + object_class_property_add(oc, "ioexps-num", "uint32", + aspeed_get_ioexps_num, + aspeed_set_ioexps_num, + NULL, NULL); +} +#endif + static void aspeed_machine_class_init(ObjectClass *oc, const void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); @@ -2032,6 +2080,7 @@ static void aspeed_machine_ast2700a1_evb_class_init(O= bjectClass *oc, mc->auto_create_sdcard =3D true; mc->default_ram_size =3D 1 * GiB; aspeed_machine_class_init_cpus_defaults(mc); + aspeed_machine_ast1700_class_init(oc); } #endif =20 --=20 2.43.0 From nobody Sat Nov 15 00:46:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175807287375973.34192203366615; Tue, 16 Sep 2025 18:34:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uyh1s-0006Cl-Iv; Tue, 16 Sep 2025 21:32:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uyh1j-0006Ak-NU; Tue, 16 Sep 2025 21:32:09 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uyh1h-0006vf-LT; Tue, 16 Sep 2025 21:32:07 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 17 Sep 2025 09:31:44 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 17 Sep 2025 09:31:44 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v1 2/6] hw/arm/aspeed: Add LTPI controller Date: Wed, 17 Sep 2025 09:31:37 +0800 Message-ID: <20250917013143.1600377-3-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250917013143.1600377-1-kane_chen@aspeedtech.com> References: <20250917013143.1600377-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1758072875027116600 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS AST27x0 platforms support two LTPI controllers. Each LTPI controller has one set of device registers, one set of PHY register and one OEM channel for AST1700 connection. Signed-off-by: Kane-Chen-AS --- include/hw/arm/aspeed_soc.h | 4 ++ include/hw/misc/aspeed_ltpi.h | 25 ++++++++ hw/arm/aspeed_ast27x0.c | 28 +++++++++ hw/misc/aspeed_ltpi.c | 111 ++++++++++++++++++++++++++++++++++ hw/misc/meson.build | 1 + 5 files changed, 169 insertions(+) create mode 100644 include/hw/misc/aspeed_ltpi.h create mode 100644 hw/misc/aspeed_ltpi.c diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 77263cc6ec..72eefb0327 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -41,6 +41,7 @@ #include "hw/fsi/aspeed_apb2opb.h" #include "hw/char/serial-mm.h" #include "hw/intc/arm_gicv3.h" +#include "hw/misc/aspeed_ltpi.h" =20 #define ASPEED_SPIS_NUM 3 #define ASPEED_EHCIS_NUM 4 @@ -104,6 +105,7 @@ struct AspeedSoCState { UnimplementedDeviceState ltpi; UnimplementedDeviceState jtag[ASPEED_JTAG_NUM]; AspeedAPB2OPBState fsi[2]; + AspeedLTPIState ltpi_ctrl[ASPEED_IOEXP_NUM]; uint8_t ioexp_num; }; =20 @@ -287,6 +289,8 @@ enum { ASPEED_GIC_REDIST, ASPEED_DEV_IPC0, ASPEED_DEV_IPC1, + ASPEED_DEV_LTPI_CTRL1, + ASPEED_DEV_LTPI_CTRL2, }; =20 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev); diff --git a/include/hw/misc/aspeed_ltpi.h b/include/hw/misc/aspeed_ltpi.h new file mode 100644 index 0000000000..2c31a555dd --- /dev/null +++ b/include/hw/misc/aspeed_ltpi.h @@ -0,0 +1,25 @@ +/* + * ASPEED LTPI Controller + * + * Copyright (C) 2025 ASPEED Technology Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef ASPEED_LTPI_H +#define ASPEED_LTPI_H + +#include "hw/sysbus.h" + +#define TYPE_ASPEED_LTPI "aspeed.ltpi-ctrl" +OBJECT_DECLARE_SIMPLE_TYPE(AspeedLTPIState, ASPEED_LTPI) + +#define ASPEED_LTPI_NR_REGS (0x900 >> 2) + +struct AspeedLTPIState { + SysBusDevice parent; + MemoryRegion mmio; + + uint32_t regs[ASPEED_LTPI_NR_REGS]; +}; + +#endif /* ASPEED_LTPI_H */ diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 6aa3841b69..3f93554027 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -80,6 +80,8 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D { [ASPEED_DEV_UART10] =3D 0x14C33900, [ASPEED_DEV_UART11] =3D 0x14C33A00, [ASPEED_DEV_UART12] =3D 0x14C33B00, + [ASPEED_DEV_LTPI_CTRL1] =3D 0x14C34000, + [ASPEED_DEV_LTPI_CTRL2] =3D 0x14C35000, [ASPEED_DEV_WDT] =3D 0x14C37000, [ASPEED_DEV_SPI_BOOT] =3D 0x100000000, [ASPEED_DEV_LTPI] =3D 0x300000000, @@ -531,6 +533,12 @@ static void aspeed_soc_ast2700_init(Object *obj) TYPE_UNIMPLEMENTED_DEVICE); } =20 +static void aspeed_ast2700_ast1700_init(AspeedSoCState *s, int i) +{ + object_initialize_child(OBJECT(s), "ltpi-ctrl[*]", + &s->ltpi_ctrl[i], TYPE_ASPEED_LTPI); +} + /* * ASPEED ast2700 has 0x0 as cluster ID * @@ -610,6 +618,20 @@ static bool aspeed_soc_ast2700_gic_realize(DeviceState= *dev, Error **errp) return true; } =20 +static void aspeed_soc_ast2700_ast1700_realize(Aspeed27x0SoCState *a, + AspeedSoCState *s, + AspeedSoCClass *sc, + int index, Error **errp) +{ + AspeedLTPIState *ltpi_ctrl =3D ASPEED_LTPI(&s->ltpi_ctrl[index]); + hwaddr ltpi_base =3D sc->memmap[ASPEED_DEV_LTPI_CTRL1 + index]; + + if (!sysbus_realize(SYS_BUS_DEVICE(ltpi_ctrl), errp)) { + return; + } + aspeed_mmio_map(s, SYS_BUS_DEVICE(ltpi_ctrl), 0, ltpi_base); +} + static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) { int i; @@ -936,6 +958,12 @@ static void aspeed_soc_ast2700_realize(DeviceState *de= v, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); =20 + /* I/O Expander */ + for (i =3D 0; i < s->ioexp_num; i++) { + aspeed_ast2700_ast1700_init(s, i); + aspeed_soc_ast2700_ast1700_realize(a, s, sc, i, errp); + } + aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->dpmcu), "aspeed.dpmcu", sc->memmap[ASPEED_DEV_DPMCU], diff --git a/hw/misc/aspeed_ltpi.c b/hw/misc/aspeed_ltpi.c new file mode 100644 index 0000000000..0c9cf40094 --- /dev/null +++ b/hw/misc/aspeed_ltpi.c @@ -0,0 +1,111 @@ +/* + * ASPEED LTPI Controller + * + * Copyright (C) 2025 ASPEED Technology Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "migration/vmstate.h" +#include "hw/misc/aspeed_ltpi.h" + +#define LTPI_LINK_MNG 0x42 +#define LTPI_PHY_MODE 0x80 + +static uint64_t ltpi_read(void *opaque, hwaddr offset, unsigned size) +{ + AspeedLTPIState *s =3D opaque; + uint32_t idx =3D offset >> 2; + + if (idx >=3D ASPEED_LTPI_NR_REGS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bad offset=3D0x%" HWADDR_PRIx "\n", + TYPE_ASPEED_LTPI, offset); + return 0; + } + + return s->regs[idx]; +} + +static void ltpi_write(void *opaque, hwaddr offset, uint64_t val, unsigned= size) +{ + AspeedLTPIState *s =3D opaque; + uint32_t idx =3D offset >> 2; + + if (idx >=3D ASPEED_LTPI_NR_REGS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bad offset=3D0x%" HWADDR_PRIx " val=3D0x%" PRIx= 64 "\n", + TYPE_ASPEED_LTPI, offset, val); + return; + } + + switch (offset) { + default: + s->regs[idx] =3D (uint32_t)val; + break; + } +} + +static const MemoryRegionOps ltpi_ops =3D { + .read =3D ltpi_read, + .write =3D ltpi_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + }, +}; + +static void ltpi_reset(DeviceState *dev) +{ + AspeedLTPIState *s =3D ASPEED_LTPI(dev); + memset(s->regs, 0, sizeof(s->regs)); + /* set default values */ + s->regs[LTPI_LINK_MNG] =3D 0x11900007; + s->regs[LTPI_PHY_MODE] =3D 0x2; +} + + +static const VMStateDescription vmstate_ltpi =3D { + .name =3D TYPE_ASPEED_LTPI, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, AspeedLTPIState, + ASPEED_LTPI_NR_REGS), + VMSTATE_END_OF_LIST() + } +}; + +static void ltpi_realize(DeviceState *dev, Error **errp) +{ + AspeedLTPIState *s =3D ASPEED_LTPI(dev); + + memory_region_init_io(&s->mmio, OBJECT(s), <pi_ops, s, + TYPE_ASPEED_LTPI, ASPEED_LTPI_NR_REGS); + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio); +} + +static void ltpi_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + dc->realize =3D ltpi_realize; + dc->vmsd =3D &vmstate_ltpi; + device_class_set_legacy_reset(dc, ltpi_reset); +} + +static const TypeInfo ltpi_info =3D { + .name =3D TYPE_ASPEED_LTPI, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(AspeedLTPIState), + .class_init =3D ltpi_class_init, +}; + +static void ltpi_register_types(void) +{ + type_register_static(<pi_info); +} + +type_init(ltpi_register_types); diff --git a/hw/misc/meson.build b/hw/misc/meson.build index b1d8d8e5d2..45b16e7797 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -136,6 +136,7 @@ system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed_hace.c', 'aspeed_i3c.c', 'aspeed_lpc.c', + 'aspeed_ltpi.c', 'aspeed_scu.c', 'aspeed_sbc.c', 'aspeed_sdmc.c', --=20 2.43.0 From nobody Sat Nov 15 00:46:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 17 Sep 2025 09:31:44 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 17 Sep 2025 09:31:44 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v1 3/6] hw/arm/aspeed: Add AST1700 IO expander Date: Wed, 17 Sep 2025 09:31:38 +0800 Message-ID: <20250917013143.1600377-4-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250917013143.1600377-1-kane_chen@aspeedtech.com> References: <20250917013143.1600377-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1758072783987116601 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS AST27x0 machines can carry up to two AST1700-based IO expander boards. This change introduces a lightweight AST1700 SoC container and maps two separate LTPI IO windows for those expanders. Signed-off-by: Kane-Chen-AS --- include/hw/arm/aspeed_soc.h | 20 ++++++++++++++++++-- hw/arm/aspeed_ast27x0.c | 17 ++++++++++++----- 2 files changed, 30 insertions(+), 7 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 72eefb0327..648c8d5c00 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -52,6 +52,21 @@ #define ASPEED_JTAG_NUM 2 #define ASPEED_IOEXP_NUM 2 =20 +typedef struct { + MemoryRegion *memory; + MemoryRegion container; + AddressSpace dram_as; + + AspeedSMCState spi; + AspeedADCState adc; + AspeedSCUState scu; + AspeedGPIOState gpio; + AspeedI2CState i2c; + AspeedI3CState i3c; + SerialMM uart; + AspeedWDTState wdt[ASPEED_WDTS_NUM]; +} AspeedAST1700SoCState; + struct AspeedSoCState { DeviceState parent; =20 @@ -102,10 +117,10 @@ struct AspeedSoCState { UnimplementedDeviceState espi; UnimplementedDeviceState udc; UnimplementedDeviceState sgpiom; - UnimplementedDeviceState ltpi; UnimplementedDeviceState jtag[ASPEED_JTAG_NUM]; AspeedAPB2OPBState fsi[2]; AspeedLTPIState ltpi_ctrl[ASPEED_IOEXP_NUM]; + AspeedAST1700SoCState ioexp[ASPEED_IOEXP_NUM]; uint8_t ioexp_num; }; =20 @@ -206,7 +221,8 @@ enum { ASPEED_DEV_IOMEM, ASPEED_DEV_IOMEM0, ASPEED_DEV_IOMEM1, - ASPEED_DEV_LTPI, + ASPEED_DEV_LTPI_IO0, + ASPEED_DEV_LTPI_IO1, ASPEED_DEV_UART0, ASPEED_DEV_UART1, ASPEED_DEV_UART2, diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 3f93554027..2e180c8cc5 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -83,8 +83,9 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D { [ASPEED_DEV_LTPI_CTRL1] =3D 0x14C34000, [ASPEED_DEV_LTPI_CTRL2] =3D 0x14C35000, [ASPEED_DEV_WDT] =3D 0x14C37000, + [ASPEED_DEV_LTPI_IO0] =3D 0x30000000, + [ASPEED_DEV_LTPI_IO1] =3D 0x50000000, [ASPEED_DEV_SPI_BOOT] =3D 0x100000000, - [ASPEED_DEV_LTPI] =3D 0x300000000, [ASPEED_DEV_SDRAM] =3D 0x400000000, }; =20 @@ -523,7 +524,9 @@ static void aspeed_soc_ast2700_init(Object *obj) object_initialize_child(obj, "hace", &s->hace, typename); object_initialize_child(obj, "dpmcu", &s->dpmcu, TYPE_UNIMPLEMENTED_DEVICE); - object_initialize_child(obj, "ltpi", &s->ltpi, + object_initialize_child(obj, "ltpi0", &s->ioexp[0], + TYPE_UNIMPLEMENTED_DEVICE); + object_initialize_child(obj, "ltpi1", &s->ioexp[1], TYPE_UNIMPLEMENTED_DEVICE); object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE); @@ -968,9 +971,13 @@ static void aspeed_soc_ast2700_realize(DeviceState *de= v, Error **errp) "aspeed.dpmcu", sc->memmap[ASPEED_DEV_DPMCU], AST2700_SOC_DPMCU_SIZE); - aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->ltpi), - "aspeed.ltpi", - sc->memmap[ASPEED_DEV_LTPI], + aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->ioexp[0]), + "aspeed.ltpi.0", + sc->memmap[ASPEED_DEV_LTPI_IO0], + AST2700_SOC_LTPI_SIZE); + aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->ioexp[1]), + "aspeed.ltpi.1", + sc->memmap[ASPEED_DEV_LTPI_IO1], AST2700_SOC_LTPI_SIZE); aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io", --=20 2.43.0 From nobody Sat Nov 15 00:46:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 17 Sep 2025 09:31:44 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 17 Sep 2025 09:31:44 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v1 4/6] hw/arm/aspeed: Model AST1700 IO expander UART on AST27x0 Date: Wed, 17 Sep 2025 09:31:39 +0800 Message-ID: <20250917013143.1600377-5-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250917013143.1600377-1-kane_chen@aspeedtech.com> References: <20250917013143.1600377-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1758072907203116600 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS AST1700 IO expander boards carry a serial-mm UART. Model this device in the AST1700 child and expose it via the AST1700 MMIO map (UART12 at offset 0x00C33B00) on AST27x0 machines. Addressing: - slot 0 (IO0): 0x30000000 + 0x00C33B00 =3D 0x30C33B00 - slot 1 (IO1): 0x50000000 + 0x00C33B00 =3D 0x50C33B00 Signed-off-by: Kane-Chen-AS --- hw/arm/aspeed_ast27x0.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 2e180c8cc5..d63a331c0a 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -89,6 +89,19 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D { [ASPEED_DEV_SDRAM] =3D 0x400000000, }; =20 +static const hwaddr aspeed_soc_ast1700_memmap[] =3D { + [ASPEED_DEV_PWM] =3D 0x000C0000, + [ASPEED_DEV_SRAM] =3D 0x00BC0000, + [ASPEED_DEV_ADC] =3D 0x00C00000, + [ASPEED_DEV_SCU] =3D 0x00C02000, + [ASPEED_DEV_GPIO] =3D 0x00C0B000, + [ASPEED_DEV_I2C] =3D 0x00C0F000, + [ASPEED_DEV_I3C] =3D 0x00C20000, + [ASPEED_DEV_UART12] =3D 0x00C33B00, + [ASPEED_DEV_WDT] =3D 0x00C37000, + [ASPEED_DEV_SPI_BOOT] =3D 0x04000000, +}; + #define AST2700_MAX_IRQ 256 =20 /* Shared Peripheral Interrupt values below are offset by -32 from datashe= et */ @@ -538,6 +551,8 @@ static void aspeed_soc_ast2700_init(Object *obj) =20 static void aspeed_ast2700_ast1700_init(AspeedSoCState *s, int i) { + object_initialize_child(OBJECT(s), "uart[*]", &s->ioexp[i].uart, + TYPE_SERIAL_MM); object_initialize_child(OBJECT(s), "ltpi-ctrl[*]", &s->ltpi_ctrl[i], TYPE_ASPEED_LTPI); } @@ -626,13 +641,27 @@ static void aspeed_soc_ast2700_ast1700_realize(Aspeed= 27x0SoCState *a, AspeedSoCClass *sc, int index, Error **errp) { + SerialMM *smm; + hwaddr uart_base =3D sc->memmap[ASPEED_DEV_LTPI_IO0 + index] + + aspeed_soc_ast1700_memmap[ASPEED_DEV_UART12]; AspeedLTPIState *ltpi_ctrl =3D ASPEED_LTPI(&s->ltpi_ctrl[index]); hwaddr ltpi_base =3D sc->memmap[ASPEED_DEV_LTPI_CTRL1 + index]; + smm =3D &s->ioexp[index].uart; + + /* Chardev property is set by the machine. */ + qdev_prop_set_uint8(DEVICE(smm), "regshift", 2); + qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400); + qdev_set_legacy_instance_id(DEVICE(smm), uart_base, 2); + qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN); + if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) { + return; + } =20 if (!sysbus_realize(SYS_BUS_DEVICE(ltpi_ctrl), errp)) { return; } aspeed_mmio_map(s, SYS_BUS_DEVICE(ltpi_ctrl), 0, ltpi_base); + aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, uart_base); } =20 static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) --=20 2.43.0 From nobody Sat Nov 15 00:46:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1758072879; cv=none; d=zohomail.com; s=zohoarc; b=XlQoZeM3VFmwHzXu1x9sdsecb7MU+4XaEAHWxI4AyVEjYPcoST0j5NCz1LLaVYrUV6OAhUBjtRREFg34si0yOnzVOrynEujbTUayrX82T03XBcApHtdFNTPoC/7WjxfmYb2g7fNe5qMnALLu5kYgkRyCbLBr85Jika5c4AX3UCM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758072879; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Tue, 16 Sep 2025 21:32:19 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 17 Sep 2025 09:31:45 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 17 Sep 2025 09:31:45 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v1 5/6] hw/arm/aspeed: Model AST1700 IO expander interrupt controllers on AST27x0 Date: Wed, 17 Sep 2025 09:31:40 +0800 Message-ID: <20250917013143.1600377-6-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250917013143.1600377-1-kane_chen@aspeedtech.com> References: <20250917013143.1600377-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1758072881220116600 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS AST27x0 boards may host up to two AST1700 IO expander cards. Model the per-expander interrupt controller (INTCIO) instances and map their MMIO windows in the SoC. This reserves the IO expander interrupt controller address space so that firmware can later route and handle interrupts for AST1700-based boards. Signed-off-by: Kane-Chen-AS --- include/hw/arm/aspeed_soc.h | 4 ++- include/hw/intc/aspeed_intc.h | 2 ++ hw/arm/aspeed_ast27x0.c | 37 +++++++++++++++++++++ hw/intc/aspeed_intc.c | 60 +++++++++++++++++++++++++++++++++++ 4 files changed, 102 insertions(+), 1 deletion(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 648c8d5c00..290bb7a6cf 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -151,7 +151,7 @@ struct Aspeed27x0SoCState { AspeedSoCState parent; =20 ARMCPU cpu[ASPEED_CPUS_NUM]; - AspeedINTCState intc[2]; + AspeedINTCState intc[4]; GICv3State gic; MemoryRegion dram_empty; }; @@ -307,6 +307,8 @@ enum { ASPEED_DEV_IPC1, ASPEED_DEV_LTPI_CTRL1, ASPEED_DEV_LTPI_CTRL2, + ASPEED_DEV_IOEXP0_INTCIO, + ASPEED_DEV_IOEXP1_INTCIO, }; =20 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev); diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h index 51288384a5..4565bbab84 100644 --- a/include/hw/intc/aspeed_intc.h +++ b/include/hw/intc/aspeed_intc.h @@ -15,6 +15,8 @@ #define TYPE_ASPEED_INTC "aspeed.intc" #define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700" #define TYPE_ASPEED_2700_INTCIO TYPE_ASPEED_INTC "io-ast2700" +#define TYPE_ASPEED_2700_INTCIOEXP1 TYPE_ASPEED_INTC "ast2700-ioexp1" +#define TYPE_ASPEED_2700_INTCIOEXP2 TYPE_ASPEED_INTC "ast2700-ioexp2" #define TYPE_ASPEED_2700SSP_INTC TYPE_ASPEED_INTC "-ast2700ssp" #define TYPE_ASPEED_2700SSP_INTCIO TYPE_ASPEED_INTC "io-ast2700ssp" #define TYPE_ASPEED_2700TSP_INTC TYPE_ASPEED_INTC "-ast2700tsp" diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index d63a331c0a..d192534e9e 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -84,7 +84,9 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D { [ASPEED_DEV_LTPI_CTRL2] =3D 0x14C35000, [ASPEED_DEV_WDT] =3D 0x14C37000, [ASPEED_DEV_LTPI_IO0] =3D 0x30000000, + [ASPEED_DEV_IOEXP0_INTCIO] =3D 0x30C18000, [ASPEED_DEV_LTPI_IO1] =3D 0x50000000, + [ASPEED_DEV_IOEXP1_INTCIO] =3D 0x50C18000, [ASPEED_DEV_SPI_BOOT] =3D 0x100000000, [ASPEED_DEV_SDRAM] =3D 0x400000000, }; @@ -504,6 +506,10 @@ static void aspeed_soc_ast2700_init(Object *obj) object_initialize_child(obj, "intc", &a->intc[0], TYPE_ASPEED_2700_INT= C); object_initialize_child(obj, "intcio", &a->intc[1], TYPE_ASPEED_2700_INTCIO); + object_initialize_child(obj, "intcioexp0", &a->intc[2], + TYPE_ASPEED_2700_INTCIOEXP1); + object_initialize_child(obj, "intcioexp1", &a->intc[3], + TYPE_ASPEED_2700_INTCIOEXP2); =20 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); object_initialize_child(obj, "adc", &s->adc, typename); @@ -642,6 +648,8 @@ static void aspeed_soc_ast2700_ast1700_realize(Aspeed27= x0SoCState *a, int index, Error **errp) { SerialMM *smm; + AspeedINTCClass *icio =3D ASPEED_INTC_GET_CLASS(&a->intc[2 + index]); + int i; hwaddr uart_base =3D sc->memmap[ASPEED_DEV_LTPI_IO0 + index] + aspeed_soc_ast1700_memmap[ASPEED_DEV_UART12]; AspeedLTPIState *ltpi_ctrl =3D ASPEED_LTPI(&s->ltpi_ctrl[index]); @@ -661,6 +669,19 @@ static void aspeed_soc_ast2700_ast1700_realize(Aspeed2= 7x0SoCState *a, return; } aspeed_mmio_map(s, SYS_BUS_DEVICE(ltpi_ctrl), 0, ltpi_base); + + /* INTC2/3 internal: orgate[i] -> input[i] */ + for (i =3D 0; i < icio->num_inpins; i++) { + qdev_connect_gpio_out(DEVICE(&a->intc[2 + index].orgates[i]), 0, + qdev_get_gpio_in(DEVICE(&a->intc[2 + index])= , i)); + } + + /* INTC2/3 output[i] -> INTC0.orgate[0].input[i] */ + for (i =3D 0; i < icio->num_outpins; i++) { + sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[2 + index]), i, + qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0])= , i)); + } + aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, uart_base); } =20 @@ -717,6 +738,22 @@ static void aspeed_soc_ast2700_realize(DeviceState *de= v, Error **errp) aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[1]), 0, sc->memmap[ASPEED_DEV_INTCIO]); =20 + /* INTCIOEXP0 */ + if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[2]), errp)) { + return; + } + + aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[2]), 0, + sc->memmap[ASPEED_DEV_IOEXP0_INTCIO]); + + /* INTCIOEXP */ + if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[3]), errp)) { + return; + } + + aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[3]), 0, + sc->memmap[ASPEED_DEV_IOEXP1_INTCIO]); + /* irq sources -> orgates -> INTC */ for (i =3D 0; i < ic->num_inpins; i++) { qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0, diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c index 5cd786dee6..a04005ee7c 100644 --- a/hw/intc/aspeed_intc.c +++ b/hw/intc/aspeed_intc.c @@ -924,6 +924,64 @@ static const TypeInfo aspeed_2700_intc_info =3D { .class_init =3D aspeed_2700_intc_class_init, }; =20 +static AspeedINTCIRQ aspeed_2700_intcioexp2_irqs[ASPEED_INTC_MAX_INPINS] = =3D { + {0, 8, 1, R_GICINT192_EN, R_GICINT192_STATUS}, + {1, 9, 1, R_GICINT193_EN, R_GICINT193_STATUS}, +}; + +static void aspeed_2700_intcioexp2_class_init(ObjectClass *klass, + const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + AspeedINTCClass *aic =3D ASPEED_INTC_CLASS(klass); + + dc->desc =3D "ASPEED 2700 IOEXP2 INTC Controller"; + aic->num_lines =3D 32; + aic->num_inpins =3D 2; + aic->num_outpins =3D 10; + aic->mem_size =3D 0x400; + aic->nr_regs =3D 0x58 >> 2; + aic->reg_offset =3D 0x100; + aic->reg_ops =3D &aspeed_intcio_ops; + aic->irq_table =3D aspeed_2700_intcioexp2_irqs; + aic->irq_table_count =3D ARRAY_SIZE(aspeed_2700_intcioexp2_irqs); +} + +static const TypeInfo aspeed_2700_intcioexp2_info =3D { + .name =3D TYPE_ASPEED_2700_INTCIOEXP2, + .parent =3D TYPE_ASPEED_INTC, + .class_init =3D aspeed_2700_intcioexp2_class_init, +}; + +static AspeedINTCIRQ aspeed_2700_intcioexp1_irqs[ASPEED_INTC_MAX_INPINS] = =3D { + {0, 6, 1, R_GICINT192_EN, R_GICINT192_STATUS}, + {1, 7, 1, R_GICINT193_EN, R_GICINT193_STATUS}, +}; + +static void aspeed_2700_intcioexp1_class_init(ObjectClass *klass, + const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + AspeedINTCClass *aic =3D ASPEED_INTC_CLASS(klass); + + dc->desc =3D "ASPEED 2700 IOEXP1 INTC Controller"; + aic->num_lines =3D 32; + aic->num_inpins =3D 2; + aic->num_outpins =3D 10; + aic->mem_size =3D 0x400; + aic->nr_regs =3D 0x58 >> 2; + aic->reg_offset =3D 0x100; + aic->reg_ops =3D &aspeed_intcio_ops; + aic->irq_table =3D aspeed_2700_intcioexp1_irqs; + aic->irq_table_count =3D ARRAY_SIZE(aspeed_2700_intcioexp1_irqs); +} + +static const TypeInfo aspeed_2700_intcioexp1_info =3D { + .name =3D TYPE_ASPEED_2700_INTCIOEXP1, + .parent =3D TYPE_ASPEED_INTC, + .class_init =3D aspeed_2700_intcioexp1_class_init, +}; + static AspeedINTCIRQ aspeed_2700_intcio_irqs[ASPEED_INTC_MAX_INPINS] =3D { {0, 0, 1, R_GICINT192_EN, R_GICINT192_STATUS}, {1, 1, 1, R_GICINT193_EN, R_GICINT193_STATUS}, @@ -1099,6 +1157,8 @@ static void aspeed_intc_register_types(void) type_register_static(&aspeed_intc_info); type_register_static(&aspeed_2700_intc_info); type_register_static(&aspeed_2700_intcio_info); + type_register_static(&aspeed_2700_intcioexp1_info); + type_register_static(&aspeed_2700_intcioexp2_info); type_register_static(&aspeed_2700ssp_intc_info); type_register_static(&aspeed_2700ssp_intcio_info); type_register_static(&aspeed_2700tsp_intc_info); --=20 2.43.0 From nobody Sat Nov 15 00:46:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 17 Sep 2025 09:31:45 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 17 Sep 2025 09:31:45 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v1 6/6] hw/arm/aspeed: Model AST1700 IO expander I2C on AST27x0 Date: Wed, 17 Sep 2025 09:31:41 +0800 Message-ID: <20250917013143.1600377-7-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250917013143.1600377-1-kane_chen@aspeedtech.com> References: <20250917013143.1600377-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1758072792219116600 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS Each AST1700 IO expander integrates a multi-function I2C controller with 16 buses. Model this controller in the AST1700 child and expose its MMIO on AST27x0 machines. Addressing: - slot 0 (IO0): 0x30000000 + 0x00C0F000 =3D 0x30C0F000 - slot 1 (IO1): 0x50000000 + 0x00C0F000 =3D 0x50C0F000 Interrupts: - add IO expander I2C interrupt sources and connect per-bus IRQs (bits 0-15) to the AST27x0 interrupt fabric, following the same fan-out used by on-SoC I2C. Each AST1700 I2C bus i emits one IRQ which is wired via ASPEED_DEV_IOEXP{0,1}_I2C index i. Enumeration: - the on-SoC AST27x0 exposes 16 I2C adapters (i2c-0 ~ i2c-15) - first AST1700 expands to i2c-16 ~ i2c-31 - second AST1700 expands to i2c-32 ~ i2c-47 Signed-off-by: Kane-Chen-AS --- include/hw/arm/aspeed_soc.h | 2 + hw/arm/aspeed_ast27x0.c | 73 +++++++++++++++++++++++++++++++++++-- 2 files changed, 71 insertions(+), 4 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 290bb7a6cf..c1702c96e3 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -307,6 +307,8 @@ enum { ASPEED_DEV_IPC1, ASPEED_DEV_LTPI_CTRL1, ASPEED_DEV_LTPI_CTRL2, + ASPEED_DEV_IOEXP0_I2C, + ASPEED_DEV_IOEXP1_I2C, ASPEED_DEV_IOEXP0_INTCIO, ASPEED_DEV_IOEXP1_INTCIO, }; diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index d192534e9e..5f54858046 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -201,6 +201,8 @@ static const int aspeed_soc_ast2700a1_irqmap[] =3D { [ASPEED_DEV_ETH3] =3D 196, [ASPEED_DEV_PECI] =3D 197, [ASPEED_DEV_SDHCI] =3D 197, + [ASPEED_DEV_IOEXP0_I2C] =3D 198, + [ASPEED_DEV_IOEXP1_I2C] =3D 200, }; =20 /* GICINT 128 */ @@ -260,6 +262,28 @@ static const int ast2700_gic133_gic197_intcmap[] =3D { [ASPEED_DEV_PECI] =3D 4, }; =20 +/* Primary AST1700 Interrupts */ +/* A1: GICINT 198 */ +static const int ast2700_gic198_intcmap[] =3D { + [ASPEED_DEV_IOEXP0_I2C] =3D 0, /* 0 - 15 */ +}; + +/* Primary AST1700 Interrupts */ +/* A1: GINTC 199 */ +static const int ast2700_gic199_intcmap[] =3D { +}; + +/* Secondary AST1700 Interrupts */ +/* A1: GINTC 200 */ +static const int ast2700_gic200_intcmap[] =3D { + [ASPEED_DEV_IOEXP1_I2C] =3D 0, /* 0 - 15 */ +}; + +/* Secondary AST1700 Interrupts */ +/* A1: GINTC 201 */ +static const int ast2700_gic201_intcmap[] =3D { +}; + /* GICINT 128 ~ 136 */ /* GICINT 192 ~ 201 */ struct gic_intc_irq_info { @@ -276,10 +300,10 @@ static const struct gic_intc_irq_info ast2700_gic_int= cmap[] =3D { {195, 1, 3, ast2700_gic131_gic195_intcmap}, {196, 1, 4, ast2700_gic132_gic196_intcmap}, {197, 1, 5, ast2700_gic133_gic197_intcmap}, - {198, 1, 6, NULL}, - {199, 1, 7, NULL}, - {200, 1, 8, NULL}, - {201, 1, 9, NULL}, + {198, 2, 0, ast2700_gic198_intcmap}, + {199, 2, 1, ast2700_gic199_intcmap}, + {200, 3, 0, ast2700_gic200_intcmap}, + {201, 3, 1, ast2700_gic201_intcmap}, {128, 0, 1, ast2700_gic128_gic192_intcmap}, {129, 0, 2, NULL}, {130, 0, 3, ast2700_gic130_gic194_intcmap}, @@ -557,8 +581,18 @@ static void aspeed_soc_ast2700_init(Object *obj) =20 static void aspeed_ast2700_ast1700_init(AspeedSoCState *s, int i) { + char socname[8]; + char typename[64]; + + if (sscanf(object_get_typename(OBJECT(s)), "%7s", socname) !=3D 1) { + g_assert_not_reached(); + } + object_initialize_child(OBJECT(s), "uart[*]", &s->ioexp[i].uart, TYPE_SERIAL_MM); + snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); + object_initialize_child(OBJECT(s), "ioexp-i2c[*]", &s->ioexp[i].i2c, + typename); object_initialize_child(OBJECT(s), "ltpi-ctrl[*]", &s->ltpi_ctrl[i], TYPE_ASPEED_LTPI); } @@ -652,8 +686,11 @@ static void aspeed_soc_ast2700_ast1700_realize(Aspeed2= 7x0SoCState *a, int i; hwaddr uart_base =3D sc->memmap[ASPEED_DEV_LTPI_IO0 + index] + aspeed_soc_ast1700_memmap[ASPEED_DEV_UART12]; + AspeedI2CClass *i2c_ctl =3D ASPEED_I2C_GET_CLASS(&s->ioexp[index].i2c); AspeedLTPIState *ltpi_ctrl =3D ASPEED_LTPI(&s->ltpi_ctrl[index]); hwaddr ltpi_base =3D sc->memmap[ASPEED_DEV_LTPI_CTRL1 + index]; + qemu_irq irq; + smm =3D &s->ioexp[index].uart; =20 /* Chardev property is set by the machine. */ @@ -683,6 +720,34 @@ static void aspeed_soc_ast2700_ast1700_realize(Aspeed2= 7x0SoCState *a, } =20 aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, uart_base); + + /* I2C */ + object_property_set_link(OBJECT(&s->ioexp[index].i2c), "dram", + OBJECT(s->dram_mr), &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->ioexp[index].i2c), errp)) { + return; + } + aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ioexp[index].i2c), 0, + sc->memmap[ASPEED_DEV_LTPI_IO0 + index] + + aspeed_soc_ast1700_memmap[ASPEED_DEV_I2C]); + for (i =3D 0; i < i2c_ctl->num_busses; i++) { + /* + * For I2C on AST1700: + * I2C bus interrupts are connected to the OR gate from bit 0 to b= it + * 15, and the OR gate output pin is connected to the input pin of + * GICINT192 of IO expander Interrupt controller (INTC2/3). Then, + * the output pin is connected to the INTC (CPU Die) input pin, and + * its output pin is connected to the GIC. + * + * I2C bus 0 is connected to the OR gate at bit 0. + * I2C bus 15 is connected to the OR gate at bit 15. + */ + irq =3D aspeed_soc_ast2700_get_irq_index(s, + ASPEED_DEV_IOEXP0_I2C + ind= ex, + i); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[index].i2c.busses[i]), + 0, irq); + } } =20 static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) --=20 2.43.0