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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3e760775880sm23033286f8f.2.2025.09.16.11.06.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 11:06:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758046008; x=1758650808; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ubfc2PZj+oS1m5/ITApUfm2bX3aVbus3n9rVpILRrWE=; b=jvB/OlytC3Cd0Ypu3HNq+FQ7FvQjfIvSeBDqPl9tgfMxoxlKlCJhYzbK7kjCqZKNRz 5Ndq+ZjFwYQWchjswDlKkefv/nU3gnF6k0HI0TrAl36lLVkM49Q6tTs5PrqjScD4TPK4 i7QVA7/Pb8+JiENZFs6Bi/scgAnqYlyItIaYxys/2DMu6bbwYWaJs/wRydQxbrLrthSS +PVdaoiCyCCHcl6S+Ek+y6QNLmUqdmY0hC7Cg8n4IEvPRs8ccS57wM8n1QBdY2Sl/oYj 0aTLPdxEssaj5pZZ2mRgGzDPhAQpeYB31rt9Wz0LoZO79mYMIJJjfm79X4DJfo9aRnH3 nUjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758046008; x=1758650808; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ubfc2PZj+oS1m5/ITApUfm2bX3aVbus3n9rVpILRrWE=; b=Q0hn5IYU7qrYZJlzZHVFKzf1NgLtWHgt1DQKgZQ3bGJ2QLAXpomLYmoXIMVXBxKoFj Mjs8YKaqHP1Xhc962g/+ajpj/cUCOYavMYInGEqrQWZrZy3n8xo6VUFP2GrnvMY66w9j lL9SqZ568h8X3/OFN5xMwkoIaDjSrnfzZbfSfaHy9NHZptTP0KsOh1SuQbc+Gapv9qDL A0si5sEtYK8zruhiJD7Q//hADBbfsWj0EnzNUTZNOZX5Ha7whrH9Fapi9Z3V9CxAlmPw rOKHJi4hz1WMQwb8AGLDT8+cq7t26c4dwaEyTW/KTFTD4nqRX5vl0FanoCwQSpMr/bpf CZqw== X-Gm-Message-State: AOJu0YyHsW11nHbCgOpeWZYADi/ytZjP45KhVMlH1Ua9CbNPylFmoFI/ YHpnSeJURFNqYg9GfzHxsrX3KRPYPEvsHkCS4tO+aPQfGOAv16tUtZ0T+6JFu3/4csaGTZhId0g TQVDJ X-Gm-Gg: ASbGncvNIrEOOjFoTIUL9qAzl7BrZSpP72qcrgyHpAvjCkBkwEMxWAUlY2CQun/CQoV JIXcB9PEiyYyqJfO/W84D7PhBiaxHylfnXIpwo6SnERHhQ8LOkeBu5CeRMu+sBedXs0tLUsvey6 nDrxJMqBmh7k4q7pMe1HxXBmH4G3XI7Mt7rj0l5+zoI8JL6bO4uyXcs0R47PsKpYsLSobQxpqqN sOTGC5F3DfzO/8K7CkLK7cVGUULQpOPrUghqQPSulNg9hjlMg8sK9QfC2f7DnJgbwl5DDCBKnzJ YvW16M+CQk7nbUKAb3j0qiYhJZd4X6NAZWroI8Pvphcx4C1sPUNoLil6IC8uoZ7m72vFzstIy2U u9HawrS7owjf9Itz9YwtbB7tKv+6IZLGsKuf+ACY= X-Google-Smtp-Source: AGHT+IFApf8ohbI8uwk+/MEsz8A+1IubEnMXSZzTRs4tUjzWR4e0k0InydV3hI/MH4a9X+zVisgRuQ== X-Received: by 2002:a05:600c:1909:b0:45f:2c89:a873 with SMTP id 5b1f17b1804b1-45f2cbafa55mr63564115e9.35.1758046007948; Tue, 16 Sep 2025 11:06:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/36] hw/pci: Introduce pci_setup_iommu_per_bus() for per-bus IOMMU ops retrieval Date: Tue, 16 Sep 2025 19:06:04 +0100 Message-ID: <20250916180611.1481266-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916180611.1481266-1-peter.maydell@linaro.org> References: <20250916180611.1481266-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758046416740116600 From: Shameer Kolothum Currently, pci_setup_iommu() registers IOMMU ops for a given PCIBus. However, when retrieving IOMMU ops for a device using pci_device_get_iommu_bus_devfn(), the function checks the parent_dev and fetches IOMMU ops from the parent device, even if the current bus does not have any associated IOMMU ops. This behavior works for now because QEMU's IOMMU implementations are globally scoped, and host bridges rely on the bypass_iommu property to skip IOMMU translation when needed. However, this model will break with the soon to be introduced arm-smmuv3 device, which allows users to associate the IOMMU with a specific PCIe root complex (e.g., the default pcie.0 or a pxb-pcie root complex). For example, consider the following setup with multiple root complexes: -device arm-smmuv3,primary-bus=3Dpcie.0,id=3Dsmmuv3.0 \ ... -device pxb-pcie,id=3Dpcie.1,bus_nr=3D8,bus=3Dpcie.0 \ -device pcie-root-port,id=3Dpcie.port1,bus=3Dpcie.1 \ -device virtio-net-pci,bus=3Dpcie.port1 In Qemu, pxb-pcie acts as a special root complex whose parent is effectively the default root complex(pcie.0). Hence, though pcie.1 has no associated SMMUv3 as per above, pci_device_get_iommu_bus_devfn() will incorrectly return the IOMMU ops from pcie.0 due to the fallback via parent_dev. To fix this, introduce a new helper pci_setup_iommu_per_bus() that explicitly sets the new iommu_per_bus field in the PCIBus structure. This helper will be used in a subsequent patch that adds support for the new arm-smmuv3 device. Update pci_device_get_iommu_bus_devfn() to use iommu_per_bus when determining the correct IOMMU ops, ensuring accurate behavior for per-bus IOMMUs. Reviewed-by: Jonathan Cameron Reviewed-by: Eric Auger Tested-by: Nathan Chen Tested-by: Eric Auger Reviewed-by: Nicolin Chen Tested-by: Nicolin Chen Signed-off-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Reviewed-by: Donald Dutile Message-id: 20250829082543.7680-7-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- include/hw/pci/pci.h | 2 ++ include/hw/pci/pci_bus.h | 1 + hw/pci/pci.c | 31 +++++++++++++++++++++++++++++++ 3 files changed, 34 insertions(+) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 6b7d3ac8a36..6bccb25ac2f 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -773,6 +773,8 @@ int pci_iommu_unregister_iotlb_notifier(PCIDevice *dev,= uint32_t pasid, */ void pci_setup_iommu(PCIBus *bus, const PCIIOMMUOps *ops, void *opaque); =20 +void pci_setup_iommu_per_bus(PCIBus *bus, const PCIIOMMUOps *ops, void *op= aque); + pcibus_t pci_bar_address(PCIDevice *d, int reg, uint8_t type, pcibus_t size); =20 diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bus.h index 22613125462..c7384467888 100644 --- a/include/hw/pci/pci_bus.h +++ b/include/hw/pci/pci_bus.h @@ -35,6 +35,7 @@ struct PCIBus { enum PCIBusFlags flags; const PCIIOMMUOps *iommu_ops; void *iommu_opaque; + bool iommu_per_bus; uint8_t devfn_min; uint32_t slot_reserved_mask; pci_set_irq_fn set_irq; diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 297196b2421..c3df9d6656b 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2912,6 +2912,19 @@ static void pci_device_get_iommu_bus_devfn(PCIDevice= *dev, } } =20 + /* + * When multiple PCI Express Root Buses are defined using pxb-pcie, + * the IOMMU configuration may be specific to each root bus. Howev= er, + * pxb-pcie acts as a special root complex whose parent is effecti= vely + * the default root complex(pcie.0). Ensure that we retrieve the + * correct IOMMU ops(if any) in such cases. + */ + if (pci_bus_is_express(iommu_bus) && pci_bus_is_root(iommu_bus)) { + if (parent_bus->iommu_per_bus) { + break; + } + } + iommu_bus =3D parent_bus; } =20 @@ -3172,6 +3185,24 @@ void pci_setup_iommu(PCIBus *bus, const PCIIOMMUOps = *ops, void *opaque) bus->iommu_opaque =3D opaque; } =20 +/* + * Similar to pci_setup_iommu(), but sets iommu_per_bus to true, + * indicating that the IOMMU is specific to this bus. This is used by + * IOMMU implementations that are tied to a specific PCIe root complex. + * + * In QEMU, pxb-pcie behaves as a special root complex whose parent is + * effectively the default root complex (pcie.0). The iommu_per_bus + * is checked in pci_device_get_iommu_bus_devfn() to ensure the correct + * IOMMU ops are returned, avoiding the use of the parent=E2=80=99s IOMMU = when + * it's not appropriate. + */ +void pci_setup_iommu_per_bus(PCIBus *bus, const PCIIOMMUOps *ops, + void *opaque) +{ + pci_setup_iommu(bus, ops, opaque); + bus->iommu_per_bus =3D true; +} + static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque) { Range *range =3D opaque; --=20 2.43.0