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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3e760775880sm23033286f8f.2.2025.09.16.11.06.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 11:06:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758046000; x=1758650800; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Zw0lxXrZ3sXM9zNmueYN9ABFbXL8fmNkpgwpH4pUGn4=; b=LOUYuMo2bzbFZaogDuFWO7aMINxdnzRCJGL/TgsWqoG+XUdmUNkomqHZ5qSRQ2BwxA ZGyLrilSi+/weJMN1HQq4agh8Enxaizyye+ADRX64+QJNnTzIx2SPE1syBt6/GNxgbS0 FPOfeIWkmUP2BskbasN+vnGosEXKPvuBGs7D4dsKpuK7Hmgfz0RUBjfEJqwgAT0D9oih bW3g+z0NVhTFEsKdTTEIsynYmgynKRb2Zl9RUeBuFDqNZyzsBfzCWW591LYlVgblqU0m ehASN+lH36fUb1MQep4C6b6QsFuAnGAMdu2Thd7cfINGt8PanVRtTp7vW4dh3uQjoClP nXFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758046000; x=1758650800; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Zw0lxXrZ3sXM9zNmueYN9ABFbXL8fmNkpgwpH4pUGn4=; b=LJkIzoP8yJmJMPrhKWQu3CYTUcpLYyfl3Ch2B+eSjqXtudWzSN8y7yWzzaClPlV375 LFwhg+q9sUh4VtjxUcFcP63qZG1iWkfgdTAb7JSYgizwj3VWAfS9qqjwRmQtvkZzDvH7 TTYaknL+mZTEvY4mxSl/htA4EA0E8F2DihBT5Y1l4ZFeD4D8EeoVPlZ7Iu7XT7cKyPj4 FPRH2xs+2P0HLEElwXoOPXk3lp7qsehOvawoj6mMlXGZThWFhp4HGkaMa13ITLtl4MDo HsbWsHwWFVyoK4cc+zIpTSQ2YIaRDRKUMwXsgjAwJKgexmfxWAGwpGKsmnZdY5HyTbno 6Fqw== X-Gm-Message-State: AOJu0YxtKWkiLu7CTG09R+KZh0R2WHsTxSx3geqcfDVBoegXrzsdIbw/ jcRRtp2KJPMRKbdJLFaTfc7voLKLcwzrNSKfNBAMeXXaG10at5joJb/oPTh/wfUJQSgLFIoTeRE Q/jNh X-Gm-Gg: ASbGncvz977Tsr23tufhLJuqnYLSvPfGTyrwcyJ9h5Tezr0EHCQm/dF5DVmfK0u2QGJ ksidjnZmF94rmsq1A3ET2rhfTwN2zozfjTeWl1a3sXZFn+Y4rxPqYXikaj/ILpPucOm84kAM6Oc GwaRJLg3lOGSa2fNes3JpCGDToeYgc2suKjS+Mflw3FHjtOF1lBHveMgdagFEhD2hAwgFybTgpB b83j5eW9Z83C4ySaNtUbhWEFwtqIrSn+hM8JYG7hOBRPY/ttJErPFHmA7MmAijtsLMeuFK6jwXT bp4mQS5QRl3dYTOcdGP8RYRDpgajSkEeCvAS6QZR6Pu+rmGWQXJdKTAT9B+mq7zER6RJpwRUvCC bcGeBK6y6AedtOSHrkkhjA4s10rhKmF7tlzJsYig= X-Google-Smtp-Source: AGHT+IFUP6cJ9GMZ0USQ4nlRhELZjWjIF0nhfAcy31LL2DDclTFrkVGy/MtZPfBBIhiga+l4EEvqgA== X-Received: by 2002:a05:600c:22d4:b0:450:6b55:cf91 with SMTP id 5b1f17b1804b1-45f211cb52amr144808095e9.6.1758046000025; Tue, 16 Sep 2025 11:06:40 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/36] target/arm: Added support for SME register exposure to GDB Date: Tue, 16 Sep 2025 19:05:57 +0100 Message-ID: <20250916180611.1481266-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916180611.1481266-1-peter.maydell@linaro.org> References: <20250916180611.1481266-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758046096763116600 Content-Type: text/plain; charset="utf-8" From: Vacha Bhavsar The QEMU GDB stub does not expose the ZA storage SME register to GDB via the remote serial protocol, which can be a useful functionality to debug SME code. To provide this functionality for AArch64 targets, this patch registers the SME register set with the GDB stub. To do so, this patch implements the aarch64_gdb_get_sme_reg() and aarch64_gdb_set_sme_reg() functions to specify how to get and set the SME registers, and the arm_gen_dynamic_smereg_feature() function to generate the target description in XML format to indicate the target architecture supports SME. Finally, this patch includes a dyn_smereg_feature structure to hold this GDB XML description of the SME registers for each CPU. Note that according to the GDB documentation the ZA register is defined as a vector of bytes; however the target description xml retrieved when using gdb natively on a host with SME capabilities represents the ZA register as a vector of vectors of bytes, so this is a GDB documentation error. We follow GDB's own gdbstub implementation and represent the ZA register as a vector of vectors of bytes as is done by GDB here: https://github.com/bminor/binutils-gdb/blob/5cce2b7006daa7073b98e3d1a3b1761= 99d1381d7/gdb/features/aarch64-sme.c#L50 Signed-off-by: Vacha Bhavsar Message-id: 20250909161012.2561593-3-vacha.bhavsar@oss.qualcomm.com Reviewed-by: Peter Maydell [PMM: fixed minor checkpatch nits] Signed-off-by: Peter Maydell --- target/arm/cpu.h | 1 + target/arm/internals.h | 3 ++ target/arm/gdbstub.c | 10 +++- target/arm/gdbstub64.c | 119 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 132 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6644043f4c2..1c0deb723d7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -925,6 +925,7 @@ struct ArchCPU { =20 DynamicGDBFeatureInfo dyn_sysreg_feature; DynamicGDBFeatureInfo dyn_svereg_feature; + DynamicGDBFeatureInfo dyn_smereg_feature; DynamicGDBFeatureInfo dyn_m_systemreg_feature; DynamicGDBFeatureInfo dyn_m_secextreg_feature; =20 diff --git a/target/arm/internals.h b/target/arm/internals.h index 8782594b774..532fabcafc1 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1817,8 +1817,11 @@ static inline uint64_t pmu_counter_mask(CPUARMState = *env) } =20 GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *cpu, int base_reg); +GDBFeature *arm_gen_dynamic_smereg_feature(CPUState *cpu, int base_reg); int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray *buf, int reg); int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf, int reg); +int aarch64_gdb_get_sme_reg(CPUState *cs, GByteArray *buf, int reg); +int aarch64_gdb_set_sme_reg(CPUState *cs, uint8_t *buf, int reg); int aarch64_gdb_get_fpu_reg(CPUState *cs, GByteArray *buf, int reg); int aarch64_gdb_set_fpu_reg(CPUState *cs, uint8_t *buf, int reg); int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int reg); diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index ce4497ad7c3..2d331fff445 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -527,7 +527,8 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) * registers so we don't need to include both. */ #ifdef TARGET_AARCH64 - if (isar_feature_aa64_sve(&cpu->isar)) { + if (isar_feature_aa64_sve(&cpu->isar) || + isar_feature_aa64_sme(&cpu->isar)) { GDBFeature *feature =3D arm_gen_dynamic_svereg_feature(cs, cs-= >gdb_num_regs); gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg, aarch64_gdb_set_sve_reg, feature, 0); @@ -537,6 +538,13 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cp= u) gdb_find_static_feature("aarch64-fpu.= xml"), 0); } + + if (isar_feature_aa64_sme(&cpu->isar)) { + GDBFeature *sme_feature =3D + arm_gen_dynamic_smereg_feature(cs, cs->gdb_num_regs); + gdb_register_coprocessor(cs, aarch64_gdb_get_sme_reg, + aarch64_gdb_set_sme_reg, sme_feature,= 0); + } /* * Note that we report pauth information via the feature name * org.gnu.gdb.aarch64.pauth_v2, not org.gnu.gdb.aarch64.pauth. diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 08e28585396..3bccde2bf25 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -249,6 +249,90 @@ int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf= , int reg) return 0; } =20 +int aarch64_gdb_get_sme_reg(CPUState *cs, GByteArray *buf, int reg) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + switch (reg) { + case 0: /* svg register */ + { + int vq =3D 0; + if (FIELD_EX64(env->svcr, SVCR, SM)) { + vq =3D sve_vqm1_for_el_sm(env, arm_current_el(env), + FIELD_EX64(env->svcr, SVCR, SM)) + 1; + } + /* svg =3D vector granules (2 * vector quardwords) in streaming mo= de */ + return gdb_get_reg64(buf, vq * 2); + } + case 1: /* svcr register */ + return gdb_get_reg64(buf, env->svcr); + case 2: /* za register */ + { + int len =3D 0; + int vq =3D cpu->sme_max_vq; + int svl =3D vq * 16; + for (int i =3D 0; i < svl; i++) { + for (int q =3D 0; q < vq; q++) { + len +=3D gdb_get_reg128(buf, + env->za_state.za[i].d[q * 2 + 1], + env->za_state.za[i].d[q * 2]); + } + } + return len; + } + default: + /* gdbstub asked for something out of range */ + qemu_log_mask(LOG_UNIMP, "%s: out of range register %d", __func__,= reg); + break; + } + + return 0; +} + +int aarch64_gdb_set_sme_reg(CPUState *cs, uint8_t *buf, int reg) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + switch (reg) { + case 0: /* svg register */ + /* cannot set svg via gdbstub */ + return 8; + case 1: /* svcr register */ + aarch64_set_svcr(env, ldq_le_p(buf), + R_SVCR_SM_MASK | R_SVCR_ZA_MASK); + return 8; + case 2: /* za register */ + { + int len =3D 0; + int vq =3D cpu->sme_max_vq; + int svl =3D vq * 16; + for (int i =3D 0; i < svl; i++) { + for (int q =3D 0; q < vq; q++) { + if (target_big_endian()) { + env->za_state.za[i].d[q * 2 + 1] =3D ldq_p(buf); + buf +=3D 8; + env->za_state.za[i].d[q * 2] =3D ldq_p(buf); + } else{ + env->za_state.za[i].d[q * 2] =3D ldq_p(buf); + buf +=3D 8; + env->za_state.za[i].d[q * 2 + 1] =3D ldq_p(buf); + } + buf +=3D 8; + len +=3D 16; + } + } + return len; + } + default: + /* gdbstub asked for something out of range */ + break; + } + + return 0; +} + int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int reg) { ARMCPU *cpu =3D ARM_CPU(cs); @@ -413,6 +497,41 @@ GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *c= s, int base_reg) return &cpu->dyn_svereg_feature.desc; } =20 +GDBFeature *arm_gen_dynamic_smereg_feature(CPUState *cs, int base_reg) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + int vq =3D cpu->sme_max_vq; + int svl =3D vq * 16; + GDBFeatureBuilder builder; + int reg =3D 0; + + gdb_feature_builder_init(&builder, &cpu->dyn_smereg_feature.desc, + "org.gnu.gdb.aarch64.sme", "sme-registers.xml= ", + base_reg); + + + /* Create the sme_bv vector type. */ + gdb_feature_builder_append_tag( + &builder, "", + svl); + + /* Create the sme_bvv vector type. */ + gdb_feature_builder_append_tag( + &builder, "", + svl); + + /* Define the svg, svcr, and za registers. */ + + gdb_feature_builder_append_reg(&builder, "svg", 64, reg++, "int", NULL= ); + gdb_feature_builder_append_reg(&builder, "svcr", 64, reg++, "int", NUL= L); + gdb_feature_builder_append_reg(&builder, "za", svl * svl * 8, reg++, + "sme_bvv", NULL); + + gdb_feature_builder_end(&builder); + + return &cpu->dyn_smereg_feature.desc; +} + #ifdef CONFIG_USER_ONLY int aarch64_gdb_get_tag_ctl_reg(CPUState *cs, GByteArray *buf, int reg) { --=20 2.43.0