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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3e760775880sm23033286f8f.2.2025.09.16.11.06.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 11:06:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758045994; x=1758650794; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=1mgWq+XLJB78p1c1ZffyK1tRiq8+FbVO+cvOUHxJI0A=; b=g6E6Hs2L2sz3aXYoapdgO6irdKa8S+TLloMP4/+Tm9ohxUG+AnQwrqGzgtbJCDuNTn hR2TNNII5QFZ0A4EY0RRKNhljV4vQOnfQJPYDcjiM4KXZjqrDy+8nelSKARYFfm4T7Qi AZdeKBrOxzwCq4zQigjAKCI41M5yt3Fsb+vrXwzqrzVnv2gSQXTrhV0NCbdj7lXzp4qm 7t2/O7vnip0EC4iCnCKWUY4fHb1CcamzbK76qNFnfEaf5+ACqzN7bjgQ2/YFmhjKMCSS +M91DMT4c4hmqpir0wbLU0QHwoI6vxoX0sfxZVpVPBJ7TB255X13X5Xbal05uyD5XsHH ZjqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758045994; x=1758650794; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1mgWq+XLJB78p1c1ZffyK1tRiq8+FbVO+cvOUHxJI0A=; b=XJZ0qWewOaL85Qf/k4uEgiHrvNrO4AQCPXhWAZzWvsrHyiToya8svt8z+Pa4FpvNeF ZwP3RY+GSygs/mpMKsxUd9Jz+H5u/N1iYlCDq0Z8awVXDxffAuugMUke2RdkzZB/W32f iyWJKTy9mcvDSLaYYbVaYt0wSXhzeKv/M8oyvZwJsfsnABbkI4FhOjnCYKNhSC2NNMsP BgJDyHguui4HOqc24Ye1rsKQw2r1G+VU1VQhcq/ATT2B8esXM5QGls3acYr/GBOdIRnK LgKNoQAIOKmD49N9e1emazbd3UPVHFxh3j1XAgF5K9rzcHdnKXTgUm5Frkqx0VhtGEXZ CPWA== X-Gm-Message-State: AOJu0YyqPJqSg4n6rQF2tZc3o0QVWwwnWPutvfbXTM/Zrwd5zTl4Bmgn Por3LohTbbaVfOGEsuMewGi1yIQdT3TH64EK7k1es7sNP68uT9DTvqB7uonOmMAKIzZUonk3x72 bP2Vr X-Gm-Gg: ASbGncvHu49blPCQM234/njsHRAab7RR2wjM0+hvEW/qNnaadcEbbcYRCyqE+mqlg9e N4Zj8dsecdl046q7e57jJEZ8E2z0InSE9IRSdloDieuMqoWNddxKxiRKng02Rb/xYRFLC5oBvAn qF2QkzBQ7eCV5pb44mFncK+OKyaxsLKDGl8P3M6AIvS+Ay8c4I9TPj3/vOX0MCwn+CMUd7Ga/M4 lDtD+PgAUlxWUdJ7j4Thn7lw+O34b2a9Kue3EszqRC44zcvLvTUKeXhbAUctPQJklQr8994++Fx 3+JuejFrXA7tuS7z0/t2HXeS+IPwj/ybE+IKbBQ6eJNVpWPJDOwP6UaCch8xFJC0je7D4Pn0j2e d47HFeYAK4eInhgf41ya7cY3opZTo X-Google-Smtp-Source: AGHT+IG+2a7Mn7vaI0A/l4I1viiqGG+69vkh5BaStzwV3frau6XAXLY/GHzLS4yFfBCIttICoTO11g== X-Received: by 2002:a05:600c:19c9:b0:45d:d291:5dc1 with SMTP id 5b1f17b1804b1-45f211da6aamr149292015e9.15.1758045994156; Tue, 16 Sep 2025 11:06:34 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/36] target/arm: Drop ARM_FEATURE_IWMMXT handling Date: Tue, 16 Sep 2025 19:05:53 +0100 Message-ID: <20250916180611.1481266-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916180611.1481266-1-peter.maydell@linaro.org> References: <20250916180611.1481266-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758046453434116600 We have now removed all the CPU types which had the Intel XScale extensions indicated via ARM_FEATURE_IWMMXT, so this feature bit is never set. Remove all the code that can only be reached when using this flag. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20250828140422.3271703-6-peter.maydell@linaro.org --- bsd-user/arm/target_arch_elf.h | 1 - target/arm/cpu.h | 19 ---------- linux-user/arm/elfload.c | 1 - linux-user/arm/signal.c | 67 ---------------------------------- target/arm/cpu.c | 8 ---- target/arm/machine.c | 21 ----------- 6 files changed, 117 deletions(-) diff --git a/bsd-user/arm/target_arch_elf.h b/bsd-user/arm/target_arch_elf.h index b1c0fd2b320..b54bf5fbc69 100644 --- a/bsd-user/arm/target_arch_elf.h +++ b/bsd-user/arm/target_arch_elf.h @@ -86,7 +86,6 @@ static uint32_t get_elf_hwcap(void) /* probe for the extra features */ /* EDSP is in v5TE and above */ GET_FEATURE(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP); - GET_FEATURE(ARM_FEATURE_IWMMXT, ARM_HWCAP_ARM_IWMMXT); GET_FEATURE(ARM_FEATURE_THUMB2EE, ARM_HWCAP_ARM_THUMBEE); GET_FEATURE(ARM_FEATURE_NEON, ARM_HWCAP_ARM_NEON); GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS); diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 92fcb96671e..6644043f4c2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -697,14 +697,6 @@ typedef struct CPUArchState { */ uint64_t exclusive_high; =20 - /* iwMMXt coprocessor state. */ - struct { - uint64_t regs[16]; - uint64_t val; - - uint32_t cregs[16]; - } iwmmxt; - struct { ARMPACKey apia; ARMPACKey apib; @@ -1863,16 +1855,6 @@ enum arm_cpu_mode { /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ #define QEMU_VFP_FPSCR_NZCV 0xffff =20 -/* iwMMXt coprocessor control registers. */ -#define ARM_IWMMXT_wCID 0 -#define ARM_IWMMXT_wCon 1 -#define ARM_IWMMXT_wCSSF 2 -#define ARM_IWMMXT_wCASF 3 -#define ARM_IWMMXT_wCGR0 8 -#define ARM_IWMMXT_wCGR1 9 -#define ARM_IWMMXT_wCGR2 10 -#define ARM_IWMMXT_wCGR3 11 - /* V7M CCR bits */ FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) FIELD(V7M_CCR, USERSETMPEND, 1, 1) @@ -2442,7 +2424,6 @@ QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= =3D R_V7M_CSSELR_INDEX_MASK); */ enum arm_features { ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ - ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ ARM_FEATURE_V6, ARM_FEATURE_V6K, ARM_FEATURE_V7, diff --git a/linux-user/arm/elfload.c b/linux-user/arm/elfload.c index 308ed23fcbd..b1a4db44660 100644 --- a/linux-user/arm/elfload.c +++ b/linux-user/arm/elfload.c @@ -76,7 +76,6 @@ abi_ulong get_elf_hwcap(CPUState *cs) =20 /* EDSP is in v5TE and above, but all our v5 CPUs are v5TE */ GET_FEATURE(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP); - GET_FEATURE(ARM_FEATURE_IWMMXT, ARM_HWCAP_ARM_IWMMXT); GET_FEATURE(ARM_FEATURE_THUMB2EE, ARM_HWCAP_ARM_THUMBEE); GET_FEATURE(ARM_FEATURE_NEON, ARM_HWCAP_ARM_NEON); GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS); diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c index 8db1c4b2338..3b387cd6d78 100644 --- a/linux-user/arm/signal.c +++ b/linux-user/arm/signal.c @@ -76,21 +76,7 @@ struct target_vfp_sigframe { struct target_user_vfp_exc ufp_exc; } __attribute__((__aligned__(8))); =20 -struct target_iwmmxt_sigframe { - abi_ulong magic; - abi_ulong size; - uint64_t regs[16]; - /* Note that not all the coprocessor control registers are stored here= */ - uint32_t wcssf; - uint32_t wcasf; - uint32_t wcgr0; - uint32_t wcgr1; - uint32_t wcgr2; - uint32_t wcgr3; -} __attribute__((__aligned__(8))); - #define TARGET_VFP_MAGIC 0x56465001 -#define TARGET_IWMMXT_MAGIC 0x12ef842a =20 struct sigframe { @@ -267,25 +253,6 @@ static abi_ulong *setup_sigframe_vfp(abi_ulong *regspa= ce, CPUARMState *env) return (abi_ulong*)(vfpframe+1); } =20 -static abi_ulong *setup_sigframe_iwmmxt(abi_ulong *regspace, CPUARMState *= env) -{ - int i; - struct target_iwmmxt_sigframe *iwmmxtframe; - iwmmxtframe =3D (struct target_iwmmxt_sigframe *)regspace; - __put_user(TARGET_IWMMXT_MAGIC, &iwmmxtframe->magic); - __put_user(sizeof(*iwmmxtframe), &iwmmxtframe->size); - for (i =3D 0; i < 16; i++) { - __put_user(env->iwmmxt.regs[i], &iwmmxtframe->regs[i]); - } - __put_user(env->vfp.xregs[ARM_IWMMXT_wCSSF], &iwmmxtframe->wcssf); - __put_user(env->vfp.xregs[ARM_IWMMXT_wCASF], &iwmmxtframe->wcssf); - __put_user(env->vfp.xregs[ARM_IWMMXT_wCGR0], &iwmmxtframe->wcgr0); - __put_user(env->vfp.xregs[ARM_IWMMXT_wCGR1], &iwmmxtframe->wcgr1); - __put_user(env->vfp.xregs[ARM_IWMMXT_wCGR2], &iwmmxtframe->wcgr2); - __put_user(env->vfp.xregs[ARM_IWMMXT_wCGR3], &iwmmxtframe->wcgr3); - return (abi_ulong*)(iwmmxtframe+1); -} - static void setup_sigframe(struct target_ucontext *uc, target_sigset_t *set, CPUARMState *env) { @@ -306,9 +273,6 @@ static void setup_sigframe(struct target_ucontext *uc, if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { regspace =3D setup_sigframe_vfp(regspace, env); } - if (arm_feature(env, ARM_FEATURE_IWMMXT)) { - regspace =3D setup_sigframe_iwmmxt(regspace, env); - } =20 /* Write terminating magic word */ __put_user(0, regspace); @@ -435,31 +399,6 @@ static abi_ulong *restore_sigframe_vfp(CPUARMState *en= v, abi_ulong *regspace) return (abi_ulong*)(vfpframe + 1); } =20 -static abi_ulong *restore_sigframe_iwmmxt(CPUARMState *env, - abi_ulong *regspace) -{ - int i; - abi_ulong magic, sz; - struct target_iwmmxt_sigframe *iwmmxtframe; - iwmmxtframe =3D (struct target_iwmmxt_sigframe *)regspace; - - __get_user(magic, &iwmmxtframe->magic); - __get_user(sz, &iwmmxtframe->size); - if (magic !=3D TARGET_IWMMXT_MAGIC || sz !=3D sizeof(*iwmmxtframe)) { - return 0; - } - for (i =3D 0; i < 16; i++) { - __get_user(env->iwmmxt.regs[i], &iwmmxtframe->regs[i]); - } - __get_user(env->vfp.xregs[ARM_IWMMXT_wCSSF], &iwmmxtframe->wcssf); - __get_user(env->vfp.xregs[ARM_IWMMXT_wCASF], &iwmmxtframe->wcssf); - __get_user(env->vfp.xregs[ARM_IWMMXT_wCGR0], &iwmmxtframe->wcgr0); - __get_user(env->vfp.xregs[ARM_IWMMXT_wCGR1], &iwmmxtframe->wcgr1); - __get_user(env->vfp.xregs[ARM_IWMMXT_wCGR2], &iwmmxtframe->wcgr2); - __get_user(env->vfp.xregs[ARM_IWMMXT_wCGR3], &iwmmxtframe->wcgr3); - return (abi_ulong*)(iwmmxtframe + 1); -} - static int do_sigframe_return(CPUARMState *env, target_ulong context_addr, struct target_ucontext *uc) @@ -482,12 +421,6 @@ static int do_sigframe_return(CPUARMState *env, return 1; } } - if (arm_feature(env, ARM_FEATURE_IWMMXT)) { - regspace =3D restore_sigframe_iwmmxt(env, regspace); - if (!regspace) { - return 1; - } - } =20 target_restore_altstack(&uc->tuc_stack, env); =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9781055bdc1..02e2a31a863 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -247,10 +247,6 @@ static void arm_cpu_reset_hold(Object *obj, ResetType = type) =20 cpu->power_state =3D cs->start_powered_off ? PSCI_OFF : PSCI_ON; =20 - if (arm_feature(env, ARM_FEATURE_IWMMXT)) { - env->iwmmxt.cregs[ARM_IWMMXT_wCID] =3D 0x69051000 | 'Q'; - } - if (arm_feature(env, ARM_FEATURE_AARCH64)) { /* 64 bit CPUs always start in 64 bit mode */ env->aarch64 =3D true; @@ -2610,14 +2606,10 @@ static const Property arm_cpu_properties[] =3D { static const gchar *arm_gdb_arch_name(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; =20 if (arm_gdbstub_is_aarch64(cpu)) { return "aarch64"; } - if (arm_feature(env, ARM_FEATURE_IWMMXT)) { - return "iwmmxt"; - } return "arm"; } =20 diff --git a/target/arm/machine.c b/target/arm/machine.c index 6986915bee8..6666a0c50c4 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -221,26 +221,6 @@ static const VMStateDescription vmstate_vfp =3D { } }; =20 -static bool iwmmxt_needed(void *opaque) -{ - ARMCPU *cpu =3D opaque; - CPUARMState *env =3D &cpu->env; - - return arm_feature(env, ARM_FEATURE_IWMMXT); -} - -static const VMStateDescription vmstate_iwmmxt =3D { - .name =3D "cpu/iwmmxt", - .version_id =3D 1, - .minimum_version_id =3D 1, - .needed =3D iwmmxt_needed, - .fields =3D (const VMStateField[]) { - VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16), - VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16), - VMSTATE_END_OF_LIST() - } -}; - /* The expression ARM_MAX_VQ - 2 is 0 for pure AArch32 build, * and ARMPredicateReg is actively empty. This triggers errors * in the expansion of the VMSTATE macros. @@ -1102,7 +1082,6 @@ const VMStateDescription vmstate_arm_cpu =3D { }, .subsections =3D (const VMStateDescription * const []) { &vmstate_vfp, - &vmstate_iwmmxt, &vmstate_m, &vmstate_thumb2ee, /* pmsav7_rnr must come before pmsav7 so that we have the --=20 2.43.0