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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3e760775880sm23033286f8f.2.2025.09.16.11.06.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 11:06:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758045974; x=1758650774; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=0mBY6NFVbqKezKf5uFHmR0YYjbdBCNV8gOIHFBoyFzo=; b=LItW75roIyNXZp/Jr817xHIBw5AB3Q+C/wFCciNBkcl9ZF30FSIJVZWIT+6RNDppIb DmuBcnuACnNAMCR5Py5sEvSHGJDztDajHPShArtgQ5/ee/QNjOdFylVUAH4oOtyVpPuy udqq89F/ksVHaRQFMG3Me4F80AalgpK4qafI72bWmmiyt6fTqgoF5Yv1gV2lNy96wB+z EvkqV+PgYPaZbiOPp6oEKhF/lWMUkTBUgceJnzXozmUS3irPlmTFUMtqgicD55pD2O9Q bgrrlGFo+hd1/JUqa2vOKW+UOv9NqFI8md35S5WW2n/fLFXZkkMvC0CpI24iAriNtpFv fosg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758045974; x=1758650774; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0mBY6NFVbqKezKf5uFHmR0YYjbdBCNV8gOIHFBoyFzo=; b=oG6NdNTTdSTpSXpj04p0EZZLZlaAywrjrQSd5vko8SRtY5WAe8I8sGx6iTwAitX/Mp mLEsWOyHS607XnO1DniKEZvifoSuhTSQMos1JH6OsBj5jKjss3ohOxFwjGnUcHawljM/ VGILvz5CSPspi7pU3iGuqIDb8XWMtYbNhdntO3AWk3DqLE7A9hZND8b+zma6B9wt3moW gnEAin8PhzQBFNWa9CaLnOlLOJMZ0U7mfsLL1lVZPjZX71JcgUUidd526E53ISNBDy3P XIOz46G1IAqSzAseROrcXweB+xPuVTnldtfFE9i1SSIHKf2yOrvm52pyUxiUHk/jEber WamQ== X-Gm-Message-State: AOJu0YxZZqhgGr1AdTsS71sQsxEETNyX67zHqka0D1yYUV+FxaRhGFjt 7Zbmd0hq2im5qR1pRUKtnplvFpAYTINXwz1qtIDW2GaFHbYRNj6nx1nuAM6UYpbpiulIZ1c+ISd 5vwQs X-Gm-Gg: ASbGnctDC9IHytnomhvkx7AYHAGdxFjbuxDopVs9NSjsVIcnGBBWMRgfSNQHI8hptr1 wDSeiT2SFSGiIuuISJA4y550Uu+ygUp7rmsG7rv/6sz06XAEIoHg5X8+DKxEpSOUtVesTHsNiBb 7yHk9tOmMBKYVL/YWzd0BZitNeUL/cjBWAxMV9bi3/OnKcF5g0t14QOHVXJSV7W67V10LJ1RVdG Iuus+mln+dbqQn0hquBqWWZon/MfmOr9pdkRx88w2mS05ybTZhfM7MhUNqkBu4sNKOLMYO5RTVW lcTCHaggaiK7fMapU2vWqb/+WNAvvyI47LtUHVtqLdw1AGIuFXdTlVy0RvfYAEwX7wBb7qTmSKG s9iEji4JEBVK98B0GeprmJCtKQyej X-Google-Smtp-Source: AGHT+IEJi818ejMIw6Og4iE6lYgxa7ucNGV8evkZzWGC3gvnsogu7Y4T7oL95/bNQSc/6AKv1rJZ5Q== X-Received: by 2002:a05:6000:4020:b0:3e9:2189:c2c3 with SMTP id ffacd0b85a97d-3e92189f54bmr10428755f8f.33.1758045974517; Tue, 16 Sep 2025 11:06:14 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/36] tests, scripts: Don't import print_function from __future__ Date: Tue, 16 Sep 2025 19:05:35 +0100 Message-ID: <20250916180611.1481266-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916180611.1481266-1-peter.maydell@linaro.org> References: <20250916180611.1481266-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758046173719116600 Some of our Python scripts still include the line from __future__ import print_function which is intended to allow a Python 2 to handle the Python 3 print() syntax. This particular part of the future arrived many years ago, and our minimum Python version is 3.9, so we don't need to keep this line around. NB: the scripts in tests/tcg/*/gdbstub/ are run with whatever Python gdb was built against, but we can safely assume that that was a Python 3 because our supported distros are all on Python 3. In any case these are only run as part of "make check-tcg", not by end-users. Commit created with: sed -i -e '/import print_function/d' $(git grep -l 'from __future__') Signed-off-by: Peter Maydell Reviewed-by: Daniel P. Berrang=C3=A9 Reviewed-by: John Snow Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20250819102409.2117969-1-peter.maydell@linaro.org --- scripts/userfaultfd-wrlat.py | 1 - tests/guest-debug/test_gdbstub.py | 1 - tests/tcg/aarch64/gdbstub/test-mte.py | 1 - tests/tcg/aarch64/gdbstub/test-sve-ioctl.py | 1 - tests/tcg/aarch64/gdbstub/test-sve.py | 1 - tests/tcg/multiarch/gdbstub/interrupt.py | 1 - tests/tcg/multiarch/gdbstub/memory.py | 1 - tests/tcg/multiarch/gdbstub/sha1.py | 1 - tests/tcg/multiarch/gdbstub/test-proc-mappings.py | 1 - tests/tcg/multiarch/gdbstub/test-qxfer-auxv-read.py | 1 - tests/tcg/multiarch/gdbstub/test-qxfer-siginfo-read.py | 1 - tests/tcg/multiarch/gdbstub/test-thread-breakpoint.py | 1 - tests/tcg/s390x/gdbstub/test-signals-s390x.py | 1 - tests/tcg/s390x/gdbstub/test-svc.py | 1 - 14 files changed, 14 deletions(-) diff --git a/scripts/userfaultfd-wrlat.py b/scripts/userfaultfd-wrlat.py index 0684be4e044..a61a9abbfcb 100755 --- a/scripts/userfaultfd-wrlat.py +++ b/scripts/userfaultfd-wrlat.py @@ -17,7 +17,6 @@ # This work is licensed under the terms of the GNU GPL, version 2 or # later. See the COPYING file in the top-level directory. =20 -from __future__ import print_function from bcc import BPF from ctypes import c_ushort, c_int, c_ulonglong from time import sleep diff --git a/tests/guest-debug/test_gdbstub.py b/tests/guest-debug/test_gdb= stub.py index 4f08089e6a9..e017ccb55d7 100644 --- a/tests/guest-debug/test_gdbstub.py +++ b/tests/guest-debug/test_gdbstub.py @@ -1,7 +1,6 @@ """Helper functions for gdbstub testing =20 """ -from __future__ import print_function import argparse import gdb import os diff --git a/tests/tcg/aarch64/gdbstub/test-mte.py b/tests/tcg/aarch64/gdbs= tub/test-mte.py index 9ad98e7a54c..f4a7d7b4465 100644 --- a/tests/tcg/aarch64/gdbstub/test-mte.py +++ b/tests/tcg/aarch64/gdbstub/test-mte.py @@ -1,4 +1,3 @@ -from __future__ import print_function # # Test GDB memory-tag commands that exercise the stubs for the qIsAddressT= agged, # qMemTag, and QMemTag packets, which are used for manipulating allocation= tags. diff --git a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py b/tests/tcg/aarch6= 4/gdbstub/test-sve-ioctl.py index a78a3a2514d..2c5c2180319 100644 --- a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py +++ b/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py @@ -1,4 +1,3 @@ -from __future__ import print_function # # Test the SVE ZReg reports the right amount of data. It uses the # sve-ioctl test and examines the register data each time the diff --git a/tests/tcg/aarch64/gdbstub/test-sve.py b/tests/tcg/aarch64/gdbs= tub/test-sve.py index 84cdcd4a32e..7b0489a622b 100644 --- a/tests/tcg/aarch64/gdbstub/test-sve.py +++ b/tests/tcg/aarch64/gdbstub/test-sve.py @@ -1,4 +1,3 @@ -from __future__ import print_function # # Test the SVE registers are visible and changeable via gdbstub # diff --git a/tests/tcg/multiarch/gdbstub/interrupt.py b/tests/tcg/multiarch= /gdbstub/interrupt.py index 2d5654d1540..4eccdb41b97 100644 --- a/tests/tcg/multiarch/gdbstub/interrupt.py +++ b/tests/tcg/multiarch/gdbstub/interrupt.py @@ -1,4 +1,3 @@ -from __future__ import print_function # # Test some of the system debug features with the multiarch memory # test. It is a port of the original vmlinux focused test case but diff --git a/tests/tcg/multiarch/gdbstub/memory.py b/tests/tcg/multiarch/gd= bstub/memory.py index 532b92e7fb3..76d75e52512 100644 --- a/tests/tcg/multiarch/gdbstub/memory.py +++ b/tests/tcg/multiarch/gdbstub/memory.py @@ -1,4 +1,3 @@ -from __future__ import print_function # # Test some of the system debug features with the multiarch memory # test. It is a port of the original vmlinux focused test case but diff --git a/tests/tcg/multiarch/gdbstub/sha1.py b/tests/tcg/multiarch/gdbs= tub/sha1.py index 1ce711a402c..3403b82fd4a 100644 --- a/tests/tcg/multiarch/gdbstub/sha1.py +++ b/tests/tcg/multiarch/gdbstub/sha1.py @@ -1,4 +1,3 @@ -from __future__ import print_function # # A very simple smoke test for debugging the SHA1 userspace test on # each target. diff --git a/tests/tcg/multiarch/gdbstub/test-proc-mappings.py b/tests/tcg/= multiarch/gdbstub/test-proc-mappings.py index 6eb6ebf7b17..796dca75f0c 100644 --- a/tests/tcg/multiarch/gdbstub/test-proc-mappings.py +++ b/tests/tcg/multiarch/gdbstub/test-proc-mappings.py @@ -1,7 +1,6 @@ """Test that gdbstub has access to proc mappings. =20 This runs as a sourced script (via -x, via run-test.py).""" -from __future__ import print_function import gdb from test_gdbstub import gdb_exit, main, report =20 diff --git a/tests/tcg/multiarch/gdbstub/test-qxfer-auxv-read.py b/tests/tc= g/multiarch/gdbstub/test-qxfer-auxv-read.py index 00c26ab4a95..fa36c943d66 100644 --- a/tests/tcg/multiarch/gdbstub/test-qxfer-auxv-read.py +++ b/tests/tcg/multiarch/gdbstub/test-qxfer-auxv-read.py @@ -1,4 +1,3 @@ -from __future__ import print_function # # Test auxiliary vector is loaded via gdbstub # diff --git a/tests/tcg/multiarch/gdbstub/test-qxfer-siginfo-read.py b/tests= /tcg/multiarch/gdbstub/test-qxfer-siginfo-read.py index 862596b07a7..b18fa1234fb 100644 --- a/tests/tcg/multiarch/gdbstub/test-qxfer-siginfo-read.py +++ b/tests/tcg/multiarch/gdbstub/test-qxfer-siginfo-read.py @@ -1,4 +1,3 @@ -from __future__ import print_function # # Test gdbstub Xfer:siginfo:read stub. # diff --git a/tests/tcg/multiarch/gdbstub/test-thread-breakpoint.py b/tests/= tcg/multiarch/gdbstub/test-thread-breakpoint.py index 4d6b6b9fbe7..49cbc3548f6 100644 --- a/tests/tcg/multiarch/gdbstub/test-thread-breakpoint.py +++ b/tests/tcg/multiarch/gdbstub/test-thread-breakpoint.py @@ -1,4 +1,3 @@ -from __future__ import print_function # # Test auxiliary vector is loaded via gdbstub # diff --git a/tests/tcg/s390x/gdbstub/test-signals-s390x.py b/tests/tcg/s390= x/gdbstub/test-signals-s390x.py index b6b7b39fc46..398ad534ebf 100644 --- a/tests/tcg/s390x/gdbstub/test-signals-s390x.py +++ b/tests/tcg/s390x/gdbstub/test-signals-s390x.py @@ -1,4 +1,3 @@ -from __future__ import print_function =20 # # Test that signals and debugging mix well together on s390x. diff --git a/tests/tcg/s390x/gdbstub/test-svc.py b/tests/tcg/s390x/gdbstub/= test-svc.py index 17210b4e020..29a0aa0ede4 100644 --- a/tests/tcg/s390x/gdbstub/test-svc.py +++ b/tests/tcg/s390x/gdbstub/test-svc.py @@ -1,7 +1,6 @@ """Test single-stepping SVC. =20 This runs as a sourced script (via -x, via run-test.py).""" -from __future__ import print_function import gdb from test_gdbstub import main, report =20 --=20 2.43.0 From nobody Sat Nov 15 00:45:06 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 16 Sep 2025 11:06:15 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/36] linux-user/aarch64: Split out signal_for_exception Date: Tue, 16 Sep 2025 19:05:36 +0100 Message-ID: <20250916180611.1481266-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916180611.1481266-1-peter.maydell@linaro.org> References: <20250916180611.1481266-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758046033676116600 From: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-id: 20250830054128.448363-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- linux-user/aarch64/cpu_loop.c | 84 ++++++++++++++++++++--------------- 1 file changed, 47 insertions(+), 37 deletions(-) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 4c4921152e8..3b2782581b6 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -27,11 +27,56 @@ #include "target/arm/syndrome.h" #include "target/arm/cpu-features.h" =20 +/* Use the exception syndrome to map a cpu exception to a signal. */ +static void signal_for_exception(CPUARMState *env, vaddr addr) +{ + uint32_t syn =3D env->exception.syndrome; + int si_code, si_signo; + + switch (syn_get_ec(syn)) { + case EC_DATAABORT: + case EC_INSNABORT: + /* Both EC have the same format for FSC, or close enough. */ + switch (extract32(syn, 0, 6)) { + case 0x04 ... 0x07: /* Translation fault, level {0-3} */ + si_signo =3D TARGET_SIGSEGV; + si_code =3D TARGET_SEGV_MAPERR; + break; + case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ + case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ + si_signo =3D TARGET_SIGSEGV; + si_code =3D TARGET_SEGV_ACCERR; + break; + case 0x11: /* Synchronous Tag Check Fault */ + si_signo =3D TARGET_SIGSEGV; + si_code =3D TARGET_SEGV_MTESERR; + break; + case 0x21: /* Alignment fault */ + si_signo =3D TARGET_SIGBUS; + si_code =3D TARGET_BUS_ADRALN; + break; + default: + g_assert_not_reached(); + } + break; + + case EC_PCALIGNMENT: + si_signo =3D TARGET_SIGBUS; + si_code =3D TARGET_BUS_ADRALN; + break; + + default: + g_assert_not_reached(); + } + + force_sig_fault(si_signo, si_code, addr); +} + /* AArch64 main loop */ void cpu_loop(CPUARMState *env) { CPUState *cs =3D env_cpu(env); - int trapnr, ec, fsc, si_code, si_signo; + int trapnr; abi_long ret; =20 for (;;) { @@ -67,42 +112,7 @@ void cpu_loop(CPUARMState *env) break; case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: - ec =3D syn_get_ec(env->exception.syndrome); - switch (ec) { - case EC_DATAABORT: - case EC_INSNABORT: - /* Both EC have the same format for FSC, or close enough. = */ - fsc =3D extract32(env->exception.syndrome, 0, 6); - switch (fsc) { - case 0x04 ... 0x07: /* Translation fault, level {0-3} */ - si_signo =3D TARGET_SIGSEGV; - si_code =3D TARGET_SEGV_MAPERR; - break; - case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ - case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ - si_signo =3D TARGET_SIGSEGV; - si_code =3D TARGET_SEGV_ACCERR; - break; - case 0x11: /* Synchronous Tag Check Fault */ - si_signo =3D TARGET_SIGSEGV; - si_code =3D TARGET_SEGV_MTESERR; - break; - case 0x21: /* Alignment fault */ - si_signo =3D TARGET_SIGBUS; - si_code =3D TARGET_BUS_ADRALN; - break; - default: - g_assert_not_reached(); - } - break; - case EC_PCALIGNMENT: - si_signo =3D TARGET_SIGBUS; - si_code =3D TARGET_BUS_ADRALN; - break; - default: - g_assert_not_reached(); - } - force_sig_fault(si_signo, si_code, env->exception.vaddress); + signal_for_exception(env, env->exception.vaddress); break; case EXCP_DEBUG: case EXCP_BKPT: --=20 2.43.0 From nobody Sat Nov 15 00:45:06 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758046192; cv=none; d=zohomail.com; s=zohoarc; b=go4zezBJ//MGX7K74bUKD/nbnMktswVE9jPOy4RYsu+9h0ErXzQkY3lOkprS0D5W6NbfkblunOYX3bUK8SD1EmU5HiRoNmRM9Gn9OiX9GtrXoT0F8ci02q10DYUzT2OlE5yz8sYxEXZsntZo1x+sRtxlnUcS1VFQ61pFFvMOV3Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758046192; 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Only pacfail uses ILL_ILLOPN (do_el0_fpac). Note that EC_MOP (do_el0_mops) ought not signal at all. For now, preserve existing behavior signalling ILL_ILLOPN. List all other exception codes and document why they do not apply to user-only. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-id: 20250830054128.448363-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- linux-user/aarch64/cpu_loop.c | 75 ++++++++++++++++++++++++++++++++++- 1 file changed, 74 insertions(+), 1 deletion(-) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 3b2782581b6..7ad26316dea 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -65,6 +65,79 @@ static void signal_for_exception(CPUARMState *env, vaddr= addr) si_code =3D TARGET_BUS_ADRALN; break; =20 + case EC_UNCATEGORIZED: /* E.g. undefined instruction */ + case EC_SYSTEMREGISTERTRAP: /* E.g. inaccessible register */ + case EC_SMETRAP: /* E.g. invalid insn in streaming state= */ + case EC_BTITRAP: /* E.g. invalid guarded branch target */ + case EC_ILLEGALSTATE: + /* + * Illegal state happens via an ERET from a privileged mode, + * so is not normally possible from user-only. However, gdbstub + * is not prevented from writing CPSR_IL, aka PSTATE.IL, which + * would generate a trap from the next translated block. + * In the kernel, default case -> el0_inv -> bad_el0_sync. + */ + si_signo =3D TARGET_SIGILL; + si_code =3D TARGET_ILL_ILLOPC; + break; + + case EC_PACFAIL: + si_signo =3D TARGET_SIGILL; + si_code =3D TARGET_ILL_ILLOPN; + break; + + case EC_MOP: + /* + * FIXME: The kernel fixes up wrong-option exceptions. + * For QEMU linux-user mode, you can only get these if + * the process is doing something silly (not executing + * the MOPS instructions in the required P/M/E sequence), + * so it is not a problem in practice that we do not. + * + * We ought ideally to implement the same "rewind to the + * start of the sequence" logic that the kernel does in + * arm64_mops_reset_regs(). In the meantime, deliver + * the guest a SIGILL, with the same ILLOPN si_code + * we've always used for this. + */ + si_signo =3D TARGET_SIGILL; + si_code =3D TARGET_ILL_ILLOPN; + break; + + case EC_WFX_TRAP: /* user-only WFI implemented as NOP */ + case EC_CP15RTTRAP: /* AArch32 */ + case EC_CP15RRTTRAP: /* AArch32 */ + case EC_CP14RTTRAP: /* AArch32 */ + case EC_CP14DTTRAP: /* AArch32 */ + case EC_ADVSIMDFPACCESSTRAP: /* user-only does not disable fpu */ + case EC_FPIDTRAP: /* AArch32 */ + case EC_PACTRAP: /* user-only does not disable pac regs = */ + case EC_BXJTRAP: /* AArch32 */ + case EC_CP14RRTTRAP: /* AArch32 */ + case EC_AA32_SVC: /* AArch32 */ + case EC_AA32_HVC: /* AArch32 */ + case EC_AA32_SMC: /* AArch32 */ + case EC_AA64_SVC: /* generates EXCP_SWI */ + case EC_AA64_HVC: /* user-only generates EC_UNCATEGORIZED= */ + case EC_AA64_SMC: /* user-only generates EC_UNCATEGORIZED= */ + case EC_SVEACCESSTRAP: /* user-only does not disable sve */ + case EC_ERETTRAP: /* user-only generates EC_UNCATEGORIZED= */ + case EC_GPC: /* user-only has no EL3 gpc tables */ + case EC_INSNABORT_SAME_EL: /* el0 cannot trap to el0 */ + case EC_DATAABORT_SAME_EL: /* el0 cannot trap to el0 */ + case EC_SPALIGNMENT: /* sp alignment checks not implemented = */ + case EC_AA32_FPTRAP: /* fp exceptions not implemented */ + case EC_AA64_FPTRAP: /* fp exceptions not implemented */ + case EC_SERROR: /* user-only does not have hw faults */ + case EC_BREAKPOINT: /* user-only does not have hw debug */ + case EC_BREAKPOINT_SAME_EL: /* user-only does not have hw debug */ + case EC_SOFTWARESTEP: /* user-only does not have hw debug */ + case EC_SOFTWARESTEP_SAME_EL: /* user-only does not have hw debug */ + case EC_WATCHPOINT: /* user-only does not have hw debug */ + case EC_WATCHPOINT_SAME_EL: /* user-only does not have hw debug */ + case EC_AA32_BKPT: /* AArch32 */ + case EC_VECTORCATCH: /* AArch32 */ + case EC_AA64_BKPT: /* generates EXCP_BKPT */ default: g_assert_not_reached(); } @@ -108,7 +181,7 @@ void cpu_loop(CPUARMState *env) /* just indicate that signals should be handled asap */ break; case EXCP_UDEF: - force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN, env->pc); + signal_for_exception(env, env->pc); break; case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: --=20 2.43.0 From nobody Sat Nov 15 00:45:06 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758046021; cv=none; d=zohomail.com; s=zohoarc; b=c7U+JjxrTurp6RNUe1zeIQxsbdcjpS2quzLLoIaKIss39ZSa69+sm9k0lbBDs1uO925BdiSeZLGBd8G608O0iQgY4dJNS7PG+kChxJwdP41sLdQcSKjcU/lBXTDSQ7NBscQ1WPlhDgcbLY8T6M2qCQuQRyAN290ssrMsBbrWB0I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758046021; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=iJXgjCpBilcdbaSRNWIXr2Xsvv7vQk5GhQFN3jN+8R8=; b=e1nPO5a5OFfnNzR8DW9sH8M/Lg9YxeJixABytSVn+Kr2lTmAqmSwWAs0iGog2cvM61bmnqo3HuHH2CJKRR9Q9zqamc9vJujRZCdNcEeJn7y6V1HmDVFIoQLS+/lj0IKCtv8mVx0MgPasqThPxtliwfMEnwMX0qaNl2cvaitpckc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758046021143506.8712125454857; Tue, 16 Sep 2025 11:07:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uya4P-0002mX-TR; Tue, 16 Sep 2025 14:06:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uya4L-0002fU-JR for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:06:21 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uya4J-0001Yp-N0 for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:06:21 -0400 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-45f29dd8490so28411115e9.1 for ; Tue, 16 Sep 2025 11:06:19 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Tue, 16 Sep 2025 11:06:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/36] linux-user/aarch64: Generate ESR signal records Date: Tue, 16 Sep 2025 19:05:38 +0100 Message-ID: <20250916180611.1481266-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916180611.1481266-1-peter.maydell@linaro.org> References: <20250916180611.1481266-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758046021805116600 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-id: 20250830054128.448363-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- linux-user/aarch64/cpu_loop.c | 3 +++ linux-user/aarch64/signal.c | 34 +++++++++++++++++++++++++++++++++- 2 files changed, 36 insertions(+), 1 deletion(-) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 7ad26316dea..6060572eed3 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -33,6 +33,9 @@ static void signal_for_exception(CPUARMState *env, vaddr = addr) uint32_t syn =3D env->exception.syndrome; int si_code, si_signo; =20 + /* Let signal delivery see that ESR is live. */ + env->cp15.esr_el[1] =3D syn; + switch (syn_get_ec(syn)) { case EC_DATAABORT: case EC_INSNABORT: diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 668353bbda4..ef97be3ac7b 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -65,6 +65,13 @@ struct target_fpsimd_context { uint64_t vregs[32 * 2]; /* really uint128_t vregs[32] */ }; =20 +#define TARGET_ESR_MAGIC 0x45535201 + +struct target_esr_context { + struct target_aarch64_ctx head; + uint64_t esr; +}; + #define TARGET_EXTRA_MAGIC 0x45585401 =20 struct target_extra_context { @@ -201,6 +208,14 @@ static void target_setup_fpsimd_record(struct target_f= psimd_context *fpsimd, } } =20 +static void target_setup_esr_record(struct target_esr_context *ctx, + CPUARMState *env) +{ + __put_user(TARGET_ESR_MAGIC, &ctx->head.magic); + __put_user(sizeof(*ctx), &ctx->head.size); + __put_user(env->cp15.esr_el[1], &ctx->esr); +} + static void target_setup_extra_record(struct target_extra_context *extra, uint64_t datap, uint32_t extra_size) { @@ -531,6 +546,9 @@ static int target_restore_sigframe(CPUARMState *env, fpsimd =3D (struct target_fpsimd_context *)ctx; break; =20 + case TARGET_ESR_MAGIC: + break; /* ignore */ + case TARGET_SVE_MAGIC: if (sve || size < sizeof(struct target_sve_context)) { goto err; @@ -683,7 +701,7 @@ static void target_setup_frame(int usig, struct target_= sigaction *ka, uc.tuc_mcontext.__reserved), }; int fpsimd_ofs, fr_ofs, sve_ofs =3D 0, za_ofs =3D 0, tpidr2_ofs =3D 0; - int zt_ofs =3D 0; + int zt_ofs =3D 0, esr_ofs =3D 0; int sve_size =3D 0, za_size =3D 0, tpidr2_size =3D 0, zt_size =3D 0; struct target_rt_sigframe *frame; struct target_rt_frame_record *fr; @@ -693,6 +711,15 @@ static void target_setup_frame(int usig, struct target= _sigaction *ka, fpsimd_ofs =3D alloc_sigframe_space(sizeof(struct target_fpsimd_contex= t), &layout); =20 + /* + * In user mode, ESR_EL1 is only set by cpu_loop while queueing the + * signal, and it's only valid for the one sync insn. + */ + if (env->cp15.esr_el[1]) { + esr_ofs =3D alloc_sigframe_space(sizeof(struct target_esr_context), + &layout); + } + /* SVE state needs saving only if it exists. */ if (cpu_isar_feature(aa64_sve, env_archcpu(env)) || cpu_isar_feature(aa64_sme, env_archcpu(env))) { @@ -754,6 +781,11 @@ static void target_setup_frame(int usig, struct target= _sigaction *ka, =20 target_setup_general_frame(frame, env, set); target_setup_fpsimd_record((void *)frame + fpsimd_ofs, env); + if (esr_ofs) { + target_setup_esr_record((void *)frame + esr_ofs, env); + /* Leave ESR_EL1 clear while it's not relevant. */ + env->cp15.esr_el[1] =3D 0; + } target_setup_end_record((void *)frame + layout.std_end_ofs); if (layout.extra_ofs) { target_setup_extra_record((void *)frame + layout.extra_ofs, --=20 2.43.0 From nobody Sat Nov 15 00:45:06 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758046457; cv=none; d=zohomail.com; s=zohoarc; b=VIzxkyzSUfPupC3BNhL9k3sLB6K5fCn0q8uGtf7ojZOnDjxS0Xw3jqrJ2PEj1W4CWjlC8t9qZtlUfS5FUhlQ+snP5/iLWLVqX2A/o81nk8chsCNTiK3VKrUyd15CM+MsMvJ3w7nQLwQiqjn+1ydd1utX8NYzi3sZK4ozKqdjCQw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758046457; 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Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-id: 20250830054128.448363-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/internals.h | 5 +++-- target/arm/ptw.c | 11 ++++++----- target/arm/tcg/m_helper.c | 4 ++-- 3 files changed, 11 insertions(+), 9 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index f5a1e75db37..899242e572f 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1624,8 +1624,9 @@ bool get_phys_addr_with_space_nogpc(CPUARMState *env,= vaddr address, __attribute__((nonnull)); =20 bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - bool is_secure, GetPhysAddrResult *result, + MMUAccessType access_type, unsigned prot_check, + ARMMMUIdx mmu_idx, bool is_secure, + GetPhysAddrResult *result, ARMMMUFaultInfo *fi, uint32_t *mregion); =20 void arm_log_exception(CPUState *cs); diff --git a/target/arm/ptw.c b/target/arm/ptw.c index ed5c728eab6..9652f40ff82 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2561,8 +2561,9 @@ static uint32_t *regime_rlar(CPUARMState *env, ARMMMU= Idx mmu_idx, } =20 bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - bool secure, GetPhysAddrResult *result, + MMUAccessType access_type, unsigned prot_check, + ARMMMUIdx mmu_idx, bool secure, + GetPhysAddrResult *result, ARMMMUFaultInfo *fi, uint32_t *mregion) { /* @@ -2750,7 +2751,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, if (arm_feature(env, ARM_FEATURE_M)) { fi->level =3D 1; } - return !(result->f.prot & (1 << access_type)); + return (prot_check & ~result->f.prot) !=3D 0; } =20 static bool v8m_is_sau_exempt(CPUARMState *env, @@ -2952,8 +2953,8 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, } } =20 - ret =3D pmsav8_mpu_lookup(env, address, access_type, mmu_idx, secure, - result, fi, NULL); + ret =3D pmsav8_mpu_lookup(env, address, access_type, 1 << access_type, + mmu_idx, secure, result, fi, NULL); if (sattrs.subpage) { result->f.lg_page_size =3D 0; } diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index 28307b56151..d856e3bc8e2 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -2829,8 +2829,8 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t ad= dr, uint32_t op) ARMMMUFaultInfo fi =3D {}; =20 /* We can ignore the return value as prot is always set */ - pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, targetsec, - &res, &fi, &mregion); + pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, PAGE_READ, mmu_idx, + targetsec, &res, &fi, &mregion); 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3e760775880sm23033286f8f.2.2025.09.16.11.06.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 11:06:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758045980; x=1758650780; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=3Ya4qtmitYtTQF+CaFE3GTL8y89kFASJ5OIdJ+/zP9s=; b=VqRIAxFnIY4uNMaOHmPLK0d32b/KtfsRrgEdSQkY2sC7gO5GrIQqPEyxLW2j3FnDCI 9G42e3unfNYGK12OO4T3q2gxCBlrP/PucvYEPNuYpspWcjoFAUHKOAB/BAsLMvp3Bw9X DyTiyD1/dFtk3ED2LpVU8iPjrQ0oSPTbRae6XMwr9LODu54tQEMR/ieZ7u0Vov56zNgB ZKs/HZRarWVKYE220vl0Ud+Wx+SLGB6jm2Q3pSEe7lkv8mTMXNxCzom/IonJSBEqNRG0 ThLYH4TPtV1y51HpZ4vh3yMX/runED1KHqkxrgpmPV6P0aV7+uDexXvxnWlFdDm0gxXC Yfww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758045980; x=1758650780; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3Ya4qtmitYtTQF+CaFE3GTL8y89kFASJ5OIdJ+/zP9s=; b=M8mhjWH9H71GUcRj4u971awM47kPANZgoh6HIw6+u0VuERQZnCQtiFbqZMKOkdR04p 6+APP5wHpCnXRpUsDqIPijpLlpVNKUY1cLrFXfD6lhMmfOfA36jRq9HKEhNQ4ifbzg53 Jf43qAvMBKPbg+R/M7OFIEm8fLs0B1ClzXUSMVpuNfIFidtlt6cdFHxhhu0pCPkxnHtl d6nO8433tV/Q6dbKErpD2nxruNn/ebstKUHaFU+8VQlDpj5dExDOeDm2h6HnnzjDJjwx cfTMSI0fA49zha059eEND0mQLr4BOrLjbx0uRp4xXOuwzgWcqHDzRQTVcRJ4b+fCUqpI IV8g== X-Gm-Message-State: AOJu0YyVtlbgMEVYfH7+569Wu+Bo+3vVUOG7LV5G5cIQ47fbbp0pIqEs Woe2i9Jls7Px1cdnX5PXAQQn53bZzzBrGGOgD6BMJe08jFXiWhD/tr6Qx3AKH131IpxjjcRV0UT J+/G8 X-Gm-Gg: ASbGncuCIa22shdb85nyFMXLDIdSxkqixcHg/bEqkuKE4McMBeCi2JIAfNKLQuG017R ToTXG6MjzkS+B7W9vKkL/ulBd7plhpmoQWtNtIliRclzwBLeNIexrXQDTsW8RloPviu3VNWLnls zzHv2/6cs24V/suHVFYuuZ++QoES3Y4pUeIG0Y7xOFvydpSlgh4mrcgR7fo4rHQhsODESXlVLMK OrJpuNHmUGZNY0C6IxZ8ZSO+GFujtI+n8Ns/PVenPghDUzAQBC1wI+nyvJiEDDl5q6nccWBQVrY Or/9JSoEaZOxvtNnG1/O+o9wLs/8iXePVvH+GIKcEacjlIKs1RTwmeGQTAkelGIApKqcIgwOvYE TYbKhJHiw3BfzuxOG3e+2s1KhLodi X-Google-Smtp-Source: AGHT+IFgfEB+W0wx/tZr0egfbOStdrf3QUB9y8axOLb/lBoff6XvgbotGMWJMsgLZ9c5XoRIyPk5Fg== X-Received: by 2002:a05:600c:6b06:b0:43c:ec4c:25b4 with SMTP id 5b1f17b1804b1-45f211d0795mr153118475e9.10.1758045979918; Tue, 16 Sep 2025 11:06:19 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/36] target/arm: Add in_prot_check to S1Translate Date: Tue, 16 Sep 2025 19:05:40 +0100 Message-ID: <20250916180611.1481266-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916180611.1481266-1-peter.maydell@linaro.org> References: <20250916180611.1481266-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758046084728116600 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Separate the access_type from the protection check. Save the trouble of modifying all helper functions by passing the new data in the control structure. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-id: 20250830054128.448363-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/ptw.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 9652f40ff82..d37c0ce0f1d 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -64,6 +64,12 @@ typedef struct S1Translate { * Stage 2 is indicated by in_mmu_idx set to ARMMMUIdx_Stage2{,_S}. */ bool in_s1_is_el0; + /* + * The set of PAGE_* bits to be use in the permission check. + * This is normally directly related to the access_type, but + * may be suppressed for debug or AT insns. + */ + uint8_t in_prot_check; bool out_rw; bool out_be; ARMSecuritySpace out_space; @@ -581,6 +587,7 @@ static bool S1_ptw_translate(CPUARMState *env, S1Transl= ate *ptw, .in_ptw_idx =3D ptw_idx_for_stage_2(env, s2_mmu_idx), .in_space =3D s2_space, .in_debug =3D true, + .in_prot_check =3D PAGE_READ, }; GetPhysAddrResult s2 =3D { }; =20 @@ -1089,7 +1096,7 @@ static bool get_phys_addr_v5(CPUARMState *env, S1Tran= slate *ptw, } result->f.prot =3D ap_to_rw_prot(env, ptw->in_mmu_idx, ap, domain_prot= ); result->f.prot |=3D result->f.prot ? PAGE_EXEC : 0; - if (!(result->f.prot & (1 << access_type))) { + if (ptw->in_prot_check & ~result->f.prot) { /* Access permission fault. */ fi->type =3D ARMFault_Permission; goto do_fault; @@ -1243,7 +1250,7 @@ static bool get_phys_addr_v6(CPUARMState *env, S1Tran= slate *ptw, =20 result->f.prot =3D get_S1prot(env, mmu_idx, false, user_rw, prot_r= w, xn, pxn, result->f.attrs.space, out_sp= ace); - if (!(result->f.prot & (1 << access_type))) { + if (ptw->in_prot_check & ~result->f.prot) { /* Access permission fault. */ fi->type =3D ARMFault_Permission; goto do_fault; @@ -2123,7 +2130,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, result->f.tlb_fill_flags =3D 0; } =20 - if (!(result->f.prot & (1 << access_type))) { + if (ptw->in_prot_check & ~result->f.prot) { fi->type =3D ARMFault_Permission; goto do_fault; } @@ -2537,7 +2544,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, =20 fi->type =3D ARMFault_Permission; fi->level =3D 1; - return !(result->f.prot & (1 << access_type)); + return (ptw->in_prot_check & ~result->f.prot) !=3D 0; } =20 static uint32_t *regime_rbar(CPUARMState *env, ARMMMUIdx mmu_idx, @@ -2953,7 +2960,7 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, } } =20 - ret =3D pmsav8_mpu_lookup(env, address, access_type, 1 << access_type, + ret =3D pmsav8_mpu_lookup(env, address, access_type, ptw->in_prot_chec= k, mmu_idx, secure, result, fi, NULL); if (sattrs.subpage) { result->f.lg_page_size =3D 0; @@ -3625,6 +3632,7 @@ bool get_phys_addr(CPUARMState *env, vaddr address, S1Translate ptw =3D { .in_mmu_idx =3D mmu_idx, .in_space =3D arm_mmu_idx_to_security_space(env, mmu_idx), + .in_prot_check =3D 1 << access_type, }; =20 return get_phys_addr_gpc(env, &ptw, address, access_type, @@ -3638,6 +3646,7 @@ static hwaddr arm_cpu_get_phys_page(CPUARMState *env,= vaddr addr, .in_mmu_idx =3D mmu_idx, .in_space =3D arm_mmu_idx_to_security_space(env, mmu_idx), .in_debug =3D true, + .in_prot_check =3D PAGE_READ, }; GetPhysAddrResult res =3D {}; ARMMMUFaultInfo fi =3D {}; --=20 2.43.0 From nobody Sat Nov 15 00:45:06 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758046459; cv=none; d=zohomail.com; s=zohoarc; b=IypTZlHRGmVWv4P3rsODbLBDmOgmHWRBC+oDPyBbG6XhLC953ka3uAV3MVP1bvzjGA/nsE7umdWZOAYRH8wW5Gj2CoUuWL/JtGMrgR7NJQ86JKUHsTw7zTMgM6Z9e98RsgMcB7KucodGEoNkH9AogCOxxPSfth0PaKKIxWkkdoc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758046459; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=B9VWGWlrF6zveqvRpxABw2S4ZXxummG73G7IdiTB2A8=; b=ikKRjBLl6EG8aUOwFbixGMXrQX7XV4U+8PT6oMmVeXQ7+MPAJ+DDVGajzmnu9fh/xy/i0rsr53sOQ71DA3r7d3RyZbOS1mRrDp3elgKsINuOQs2KP85zS6cUqtoj4NXPNj+G6Ftta3HQ50LVbdb+SCBQvoBmfJTD7ED4ANV6yt4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758046459196475.4038079264659; Tue, 16 Sep 2025 11:14:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uya4T-00033A-0I; Tue, 16 Sep 2025 14:06:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uya4N-0002lc-T7 for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:06:23 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uya4M-0001ZZ-Bn for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:06:23 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-45df0cde41bso42690325e9.3 for ; Tue, 16 Sep 2025 11:06:21 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-id: 20250830054128.448363-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/ptw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index d37c0ce0f1d..5d85610de29 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3646,7 +3646,7 @@ static hwaddr arm_cpu_get_phys_page(CPUARMState *env,= vaddr addr, .in_mmu_idx =3D mmu_idx, .in_space =3D arm_mmu_idx_to_security_space(env, mmu_idx), .in_debug =3D true, - .in_prot_check =3D PAGE_READ, + .in_prot_check =3D 0, }; GetPhysAddrResult res =3D {}; ARMMMUFaultInfo fi =3D {}; --=20 2.43.0 From nobody Sat Nov 15 00:45:06 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758046460; cv=none; d=zohomail.com; s=zohoarc; b=RYtql7mOUos0A1uFWE+sFTu/etCAnT1/YjIFZLFHb3lFzuaUhLBoAGsRZMkcj3BqPQ6GL63opAxFw/R5AXbMqouDaz9mmVpzABC5bmu6iQ6L9Zfv/DS//tquoc+2jEE2AboA1Q9fYBUzFjOVry1rm4q/cUXfLYXB2PQOLziqatE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758046460; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=7ECBn6N5IfpT2DcG4vN1Bk0unyr8MRHKpcjEdajq/Zw=; b=YcgLO1G2W5GoLcbng4NB8fF2vVqOigKhAuxmVV5paJM/2MDoFPTfJSzrdceHuqsh7Ly0AzAzDWkI9aCmVLtz0wILnFIwUE9vqiMSM93WH8NBJZSehAoHJf1ae2ljf1vBgJOdyCKCNn+eRKuMvnlo43FmwTte/EwQRRNeZO/0ixg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758046460654413.7879036752039; Tue, 16 Sep 2025 11:14:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uya4R-0002zF-ET; Tue, 16 Sep 2025 14:06:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uya4P-0002s1-Vk for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:06:26 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uya4N-0001Zl-LH for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:06:25 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-45dd513f4ecso35430825e9.3 for ; Tue, 16 Sep 2025 11:06:23 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3e760775880sm23033286f8f.2.2025.09.16.11.06.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 11:06:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758045982; x=1758650782; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=7ECBn6N5IfpT2DcG4vN1Bk0unyr8MRHKpcjEdajq/Zw=; b=dYdlcVI9yru39qydu7iWPsw4NI+A8MBD28I2olG8blAMHYW3taGtQlf2hPLVautY7g 2N7a9zsj6qPBelQ+Dh4nVXHaq7DxVR2YZzDm5w4aV4X578XMY1qZAzeqB+yOazjYcxpf m+UcQtBv9PkFbFqJeGNz4X/ffkr+W5rmyZemOnlJR3osNpfdwoJW8FT2uzjPoSAO4m1w QHZUziDOs0YpqmIhQCl0bUYvfKRz4fphYj8Gn56h53016v8/ED9EjPOWOPBe/DZmg6dB FRe8PXucddukbfzNmnYMgXs0FqrGkg4aXkSiQMjvVnab9qMiBe93HxV+pHcrEHwD1tgG 6rTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758045982; x=1758650782; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7ECBn6N5IfpT2DcG4vN1Bk0unyr8MRHKpcjEdajq/Zw=; b=nLF7B+TlQHtfcdd44+ofZB8QRzackWR8vwwHWy5+WcgBaapElUAmHQ2VlM0XihVeQA v1DWy+8qdzLNooCkQmCP+l8sUC5W97Z55NWOS0FtMv/oL5ituzwg8+vEZSWxkw93kxyT Bx5P5JGCmMrX+j9wobsTZTvJ9ZgCMuxO0As+WA+8UB6fWTXx6WssOnQdkGoLHrAizeHD GBwChgF657id97+TLDZfDhMQBIwLT0+FJ6Vr5d06fMJFAwxrkGy3ZN2WryZ/YmY/BDJ/ 6kZnUjMuKnmLgQrcm/taogHctHwPm/y+eEZDj6wLzuOH2i4AulCcBuhkLgePUeXIIwi+ tXiw== X-Gm-Message-State: AOJu0YxwY36M2plpbMkmUFCGtWSi5cU7S4VxXVpaWz56sv90pIjXJvgZ DJk7RgywzuMUOWgKyT39MOtB5lIc3MCwx0bic9pZckKN/6HgOGpMtWXCNUfZaz5FYmLKtkmHnae p6eZd X-Gm-Gg: ASbGncuuKGQettfFuSjyYRbn8kCXvFgK14zvURclYRX2gho5BI0l45Msq2lqxtxFCOl ey6FQojuzGh91R/a7CxGOFh2cujG/odqb2ntf2g8OMx+ph+kVjNcnfdSeFqzqdatuRz8ap3pRkI Mh/ljh+O1+Ta/WXN1rPg7jaMAvSqAxGR2ePBfGOMkQhdwPJma3QxnDIOb0bM+brQkqWbnDdoaNV 4amEy5KSDmlCVyIuANUGelER4/bVCEIy4lYRDZ9xK0iThCN+uEHYh9KLdqyo9xHpFhLe7zVhl7C yIGzUlnx5+5KzBLnYEyXFOyY78a8Z1ek6kjbO/IoiRnO+gVi5L09xLK5JcZlb6ivcHFfgjDcM6U oloAusqtyN0FL652Qz95iysc1lJ7w X-Google-Smtp-Source: AGHT+IG+85LWHUXpr9pMldixRuJcz+vNz60WkgedJv8nXDvgPHEb1DOoIlyVNnzNPl38BUOKI5TA7g== X-Received: by 2002:a7b:cc88:0:b0:45d:f7ca:4f07 with SMTP id 5b1f17b1804b1-45f2121490bmr136114715e9.18.1758045981895; Tue, 16 Sep 2025 11:06:21 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/36] target/arm: Introduce get_phys_addr_for_at Date: Tue, 16 Sep 2025 19:05:42 +0100 Message-ID: <20250916180611.1481266-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916180611.1481266-1-peter.maydell@linaro.org> References: <20250916180611.1481266-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758046461180116600 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Rename get_phys_addr_with_space_nogpc for its only caller, do_ats_write. Drop the MemOp memop argument as it doesn't make sense in the new context. Replace the access_type parameter with prot_check. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-id: 20250830054128.448363-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/internals.h | 18 +++++++----------- target/arm/ptw.c | 21 ++++++++++++++------- target/arm/tcg/cpregs-at.c | 11 ++--------- 3 files changed, 23 insertions(+), 27 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 899242e572f..8782594b774 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1602,25 +1602,21 @@ bool get_phys_addr(CPUARMState *env, vaddr address, __attribute__((nonnull)); =20 /** - * get_phys_addr_with_space_nogpc: get the physical address for a virtual - * address + * get_phys_addr_for_at: * @env: CPUARMState * @address: virtual address to get physical address for - * @access_type: 0 for read, 1 for write, 2 for execute - * @memop: memory operation feeding this access, or 0 for none + * @prot_check: PAGE_{READ,WRITE,EXEC}, or 0 * @mmu_idx: MMU index indicating required translation regime * @space: security space for the access * @result: set on translation success. * @fi: set to fault info if the translation fails * - * Similar to get_phys_addr, but use the given security space and don't pe= rform - * a Granule Protection Check on the resulting address. + * Similar to get_phys_addr, but for use by AccessType_AT, i.e. + * system instructions for address translation. */ -bool get_phys_addr_with_space_nogpc(CPUARMState *env, vaddr address, - MMUAccessType access_type, MemOp memop, - ARMMMUIdx mmu_idx, ARMSecuritySpace sp= ace, - GetPhysAddrResult *result, - ARMMMUFaultInfo *fi) +bool get_phys_addr_for_at(CPUARMState *env, vaddr address, unsigned prot_c= heck, + ARMMMUIdx mmu_idx, ARMSecuritySpace space, + GetPhysAddrResult *result, ARMMMUFaultInfo *fi) __attribute__((nonnull)); =20 bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 5d85610de29..8925c9a6100 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3545,18 +3545,25 @@ static bool get_phys_addr_gpc(CPUARMState *env, S1T= ranslate *ptw, return false; } =20 -bool get_phys_addr_with_space_nogpc(CPUARMState *env, vaddr address, - MMUAccessType access_type, MemOp memop, - ARMMMUIdx mmu_idx, ARMSecuritySpace sp= ace, - GetPhysAddrResult *result, - ARMMMUFaultInfo *fi) +bool get_phys_addr_for_at(CPUARMState *env, vaddr address, + unsigned prot_check, ARMMMUIdx mmu_idx, + ARMSecuritySpace space, GetPhysAddrResult *resul= t, + ARMMMUFaultInfo *fi) { S1Translate ptw =3D { .in_mmu_idx =3D mmu_idx, .in_space =3D space, + .in_prot_check =3D prot_check, }; - return get_phys_addr_nogpc(env, &ptw, address, access_type, - memop, result, fi); + /* + * I_MXTJT: Granule protection checks are not performed on the final + * address of a successful translation. This is a translation not a + * memory reference, so MMU_DATA_LOAD is arbitrary (the exact protecti= on + * check is handled or bypassed by .in_prot_check) and "memop =3D MO_8" + * bypasses any alignment check. + */ + return get_phys_addr_nogpc(env, &ptw, address, + MMU_DATA_LOAD, MO_8, result, fi); } =20 static ARMSecuritySpace diff --git a/target/arm/tcg/cpregs-at.c b/target/arm/tcg/cpregs-at.c index 398a61d3989..2ff0b3e76f7 100644 --- a/target/arm/tcg/cpregs-at.c +++ b/target/arm/tcg/cpregs-at.c @@ -27,19 +27,12 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t= value, MMUAccessType access_type, ARMMMUIdx mmu_idx, ARMSecuritySpace ss) { - bool ret; uint64_t par64; bool format64 =3D false; ARMMMUFaultInfo fi =3D {}; GetPhysAddrResult res =3D {}; - - /* - * I_MXTJT: Granule protection checks are not performed on the final - * address of a successful translation. This is a translation not a - * memory reference, so "memop =3D none =3D 0". - */ - ret =3D get_phys_addr_with_space_nogpc(env, value, access_type, 0, - mmu_idx, ss, &res, &fi); + bool ret =3D get_phys_addr_for_at(env, value, 1 << access_type, + mmu_idx, ss, &res, &fi); =20 /* * ATS operations only do S1 or S1+S2 translations, so we never --=20 2.43.0 From nobody Sat Nov 15 00:45:06 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758046232; cv=none; d=zohomail.com; s=zohoarc; b=BaEpmwyyQSqCP5F7vyFU7h/x4z309TdDv1NoaNb2eVGPk+XM1NZS+PpO2LjLm35JZAvIgVQq4JFNK/Mpzz6JAZCn9vB90b2jANhfzxoSHZogYOWEoXPM2Cl+TeahKRfDySviWXlgGzObhxj8EQUzVuypeO4dYeyKlrtrKOfmRqQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758046232; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=048D1PM0KI7bmfl5+HZw1hE5YzcYQNnw30YAurkEvnI=; b=Gnxefeihn8fMjo5HzXc+PB5eIHvmfxQBEmAZVzJPGjNckrjBIcPrB7lkOpmQYkUrp0qauRce+q8EPEKZdvoM3oEnM6Ws7+76Vi+bhWaHhMuc6FIwERLmS38V54aN7n/qcyJkdkrpX6uSMFWoEqJ1Ny9EUM73Gcqgj3X3n3K7DsU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758046232919230.61723346032193; Tue, 16 Sep 2025 11:10:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uya4T-00033O-U3; Tue, 16 Sep 2025 14:06:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uya4R-0002yL-7y for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:06:27 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uya4O-0001Zv-IY for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:06:26 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-45f2fa8a1adso1012455e9.1 for ; Tue, 16 Sep 2025 11:06:24 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Choose to skip both. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-id: 20250830054128.448363-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/ptw.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 8925c9a6100..089eeff845c 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -58,6 +58,12 @@ typedef struct S1Translate { * and will not change the state of the softmmu TLBs. */ bool in_debug; + /* + * in_at: is this AccessType_AT? + * This is also set for debug, because at heart that is also + * an address translation, and simplifies a test. + */ + bool in_at; /* * If this is stage 2 of a stage 1+2 page table walk, then this must * be true if stage 1 is an EL0 access; otherwise this is ignored. @@ -1929,7 +1935,12 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1T= ranslate *ptw, descaddr &=3D ~(hwaddr)(page_size - 1); descaddr |=3D (address & (page_size - 1)); =20 - if (likely(!ptw->in_debug)) { + /* + * For AccessType_AT, DB is not updated (AArch64.SetDirtyFlag), + * and it is IMPLEMENTATION DEFINED whether AF is updated + * (AArch64.SetAccessFlag; qemu chooses to not update). + */ + if (likely(!ptw->in_at)) { /* * Access flag. * If HA is enabled, prepare to update the descriptor below. @@ -3553,6 +3564,7 @@ bool get_phys_addr_for_at(CPUARMState *env, vaddr add= ress, S1Translate ptw =3D { .in_mmu_idx =3D mmu_idx, .in_space =3D space, + .in_at =3D true, .in_prot_check =3D prot_check, }; /* @@ -3653,6 +3665,7 @@ static hwaddr arm_cpu_get_phys_page(CPUARMState *env,= vaddr addr, .in_mmu_idx =3D mmu_idx, .in_space =3D arm_mmu_idx_to_security_space(env, mmu_idx), .in_debug =3D true, + .in_at =3D true, .in_prot_check =3D 0, }; GetPhysAddrResult res =3D {}; --=20 2.43.0 From nobody Sat Nov 15 00:45:06 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758046442; cv=none; d=zohomail.com; s=zohoarc; b=jtT5hRNZoHO9G/7fGvhVNudG/5lqoYZLgAvrDPJveaTUIYLOd9ytc1elsl45ji3xect1D16DO7zapjokO9TIyg5LGSUpt1OFno45YvjCvciZOAdm2Kzk9mNUfG5QDOcdI1BeKt8muDgN2EXsX4iHqHIvCp3UJbeVdNtKAMTjApM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758046442; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=2jY99sznuAdHkjwdN7SRLmA+n/jUeQ2zxUjbOwbHyAU=; b=OK8AJN4qqebDp0F/FF9oCRdmkTfD2OytdLv8EU2cpf6b5yXlZGXXacLN5otkX3QWWKWkQNyhE0sT92b2w/JtFGGAkOZEHqyaGo07bpwfPyTTzyq+pC5BLnMUfmR9zz9Y2GaK6JeKnsgNxY0czXuQtNhUQK5VyIoBqB8eQmXgICI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758046442402854.5151401835326; Tue, 16 Sep 2025 11:14:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uya4V-00034G-5G; Tue, 16 Sep 2025 14:06:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uya4R-00030F-ID for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:06:27 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uya4P-0001aB-NY for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:06:27 -0400 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-45f31adf368so12705325e9.3 for ; Tue, 16 Sep 2025 11:06:25 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-id: 20250830054128.448363-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/cpregs-at.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/arm/tcg/cpregs-at.c b/target/arm/tcg/cpregs-at.c index 2ff0b3e76f7..bebf1689970 100644 --- a/target/arm/tcg/cpregs-at.c +++ b/target/arm/tcg/cpregs-at.c @@ -24,14 +24,14 @@ static int par_el1_shareability(GetPhysAddrResult *res) } =20 static uint64_t do_ats_write(CPUARMState *env, uint64_t value, - MMUAccessType access_type, ARMMMUIdx mmu_idx, + unsigned prot_check, ARMMMUIdx mmu_idx, ARMSecuritySpace ss) { uint64_t par64; bool format64 =3D false; ARMMMUFaultInfo fi =3D {}; GetPhysAddrResult res =3D {}; - bool ret =3D get_phys_addr_for_at(env, value, 1 << access_type, + bool ret =3D get_phys_addr_for_at(env, value, prot_check, mmu_idx, ss, &res, &fi); =20 /* @@ -191,7 +191,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t= value, =20 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) { - MMUAccessType access_type =3D ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA= _LOAD; + unsigned access_perm =3D ri->opc2 & 1 ? PAGE_WRITE : PAGE_READ; uint64_t par64; ARMMMUIdx mmu_idx; int el =3D arm_current_el(env); @@ -253,7 +253,7 @@ static void ats_write(CPUARMState *env, const ARMCPRegI= nfo *ri, uint64_t value) g_assert_not_reached(); } =20 - par64 =3D do_ats_write(env, value, access_type, mmu_idx, ss); + par64 =3D do_ats_write(env, value, access_perm, mmu_idx, ss); =20 A32_BANKED_CURRENT_REG_SET(env, par, par64); } @@ -261,11 +261,11 @@ static void ats_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - MMUAccessType access_type =3D ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA= _LOAD; + unsigned access_perm =3D ri->opc2 & 1 ? PAGE_WRITE : PAGE_READ; uint64_t par64; =20 /* There is no SecureEL2 for AArch32. */ - par64 =3D do_ats_write(env, value, access_type, ARMMMUIdx_E2, + par64 =3D do_ats_write(env, value, access_perm, ARMMMUIdx_E2, ARMSS_NonSecure); =20 A32_BANKED_CURRENT_REG_SET(env, par, par64); @@ -309,7 +309,7 @@ static CPAccessResult at_s1e01_access(CPUARMState *env,= const ARMCPRegInfo *ri, static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - MMUAccessType access_type =3D ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA= _LOAD; + unsigned access_perm =3D ri->opc2 & 1 ? PAGE_WRITE : PAGE_READ; ARMMMUIdx mmu_idx; uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); bool regime_e20 =3D (hcr_el2 & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | = HCR_TGE); @@ -352,7 +352,7 @@ static void ats_write64(CPUARMState *env, const ARMCPRe= gInfo *ri, } =20 ss =3D for_el3 ? arm_security_space(env) : arm_security_space_below_el= 3(env); - env->cp15.par_el[1] =3D do_ats_write(env, value, access_type, mmu_idx,= ss); + env->cp15.par_el[1] =3D do_ats_write(env, value, access_perm, mmu_idx,= ss); } =20 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, --=20 2.43.0 From nobody Sat Nov 15 00:45:06 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758046443; cv=none; d=zohomail.com; s=zohoarc; b=mWJOlctOhrD8KMIIeLNJ5J9tip2IO4S4oMYaTSCWn8gy0YnJl3uG3VK/UeACl9BTUwuRe5gEMiWuTKfD+vajMNOYErWuYRHpOBAeT9MocwCNkx1IS4m1yy0MqPCu7XBPgHHDYgjekwWDt/QsW9pKCA2dVEOsgFjf6PGubCENQP0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758046443; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=1afiKA5WXH75zos913UixLbC9rUVw+fEq1nhaCLbfzY=; b=e2WU8mS3rB7husYsZV6AJgUUmk5ma1hD/65WI6S3E2q+97Jhuw3JAmxynIUqlo/vVrLjPXQLwIXpmf61p5yjumfb4/v3nUgk4eeFCHrFFroSRJuP7cI55n8Vcp3EJ6/qqYWBVMg4eIPxW6kCOqg37wKYnJztdY4yvdGqFNTJpDk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758046443144266.33647900017866; Tue, 16 Sep 2025 11:14:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uya4V-00034x-Pj; Tue, 16 Sep 2025 14:06:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uya4S-000330-JD for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:06:28 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uya4Q-0001aH-G4 for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:06:28 -0400 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-3dae49b117bso4502257f8f.1 for ; Tue, 16 Sep 2025 11:06:26 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Tue, 16 Sep 2025 11:06:24 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/36] target/arm: Fill in HFG[RWI]TR_EL2 bits for Arm v9.5 Date: Tue, 16 Sep 2025 19:05:45 +0100 Message-ID: <20250916180611.1481266-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916180611.1481266-1-peter.maydell@linaro.org> References: <20250916180611.1481266-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758046445091116600 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-id: 20250830054128.448363-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpregs.h | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index c9506aa6d57..1d103b577f7 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -408,10 +408,19 @@ FIELD(HFGRTR_EL2, ERXPFGCTL_EL1, 47, 1) FIELD(HFGRTR_EL2, ERXPFGCDN_EL1, 48, 1) FIELD(HFGRTR_EL2, ERXADDR_EL1, 49, 1) FIELD(HFGRTR_EL2, NACCDATA_EL1, 50, 1) -/* 51-53: RES0 */ +/* 51: RES0 */ +FIELD(HFGRTR_EL2, NGCS_EL0, 52, 1) +FIELD(HFGRTR_EL2, NGCS_EL1, 53, 1) FIELD(HFGRTR_EL2, NSMPRI_EL1, 54, 1) FIELD(HFGRTR_EL2, NTPIDR2_EL0, 55, 1) -/* 56-63: RES0 */ +FIELD(HFGRTR_EL2, NRCWMASK_EL1, 56, 1) +FIELD(HFGRTR_EL2, NPIRE0_EL1, 57, 1) +FIELD(HFGRTR_EL2, NPIR_EL1, 58, 1) +FIELD(HFGRTR_EL2, NPOR_EL0, 59, 1) +FIELD(HFGRTR_EL2, NPOR_EL1, 60, 1) +FIELD(HFGRTR_EL2, NS2POR_EL1, 61, 1) +FIELD(HFGRTR_EL2, NMAIR2_EL1, 62, 1) +FIELD(HFGRTR_EL2, NAMAIR2_EL1, 63, 1) =20 /* These match HFGRTR but bits for RO registers are RES0 */ FIELD(HFGWTR_EL2, AFSR0_EL1, 0, 1) @@ -452,8 +461,18 @@ FIELD(HFGWTR_EL2, ERXPFGCTL_EL1, 47, 1) FIELD(HFGWTR_EL2, ERXPFGCDN_EL1, 48, 1) FIELD(HFGWTR_EL2, ERXADDR_EL1, 49, 1) FIELD(HFGWTR_EL2, NACCDATA_EL1, 50, 1) +FIELD(HFGWTR_EL2, NGCS_EL0, 52, 1) +FIELD(HFGWTR_EL2, NGCS_EL1, 53, 1) FIELD(HFGWTR_EL2, NSMPRI_EL1, 54, 1) FIELD(HFGWTR_EL2, NTPIDR2_EL0, 55, 1) +FIELD(HFGWTR_EL2, NRCWMASK_EL1, 56, 1) +FIELD(HFGWTR_EL2, NPIRE0_EL1, 57, 1) +FIELD(HFGWTR_EL2, NPIR_EL1, 58, 1) +FIELD(HFGWTR_EL2, NPOR_EL0, 59, 1) +FIELD(HFGWTR_EL2, NPOR_EL1, 60, 1) +FIELD(HFGWTR_EL2, NS2POR_EL1, 61, 1) +FIELD(HFGWTR_EL2, NMAIR2_EL1, 62, 1) +FIELD(HFGWTR_EL2, NAMAIR2_EL1, 63, 1) =20 FIELD(HFGITR_EL2, ICIALLUIS, 0, 1) FIELD(HFGITR_EL2, ICIALLU, 1, 1) @@ -512,6 +531,11 @@ FIELD(HFGITR_EL2, SVC_EL1, 53, 1) FIELD(HFGITR_EL2, DCCVAC, 54, 1) FIELD(HFGITR_EL2, NBRBINJ, 55, 1) FIELD(HFGITR_EL2, NBRBIALL, 56, 1) +FIELD(HFGITR_EL2, NGCSPUSHM_EL1, 57, 1) +FIELD(HFGITR_EL2, NGCSSTR_EL1, 58, 1) +FIELD(HFGITR_EL2, NGCSEPP, 59, 1) +FIELD(HFGITR_EL2, COSPRCTX, 60, 1) +FIELD(HFGITR_EL2, ATS1E1A, 62, 1) =20 FIELD(HDFGRTR_EL2, DBGBCRN_EL1, 0, 1) FIELD(HDFGRTR_EL2, DBGBVRN_EL1, 1, 1) --=20 2.43.0 From nobody Sat Nov 15 00:45:06 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3e760775880sm23033286f8f.2.2025.09.16.11.06.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 11:06:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758045986; x=1758650786; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=d1YOtX8BVonSDnFz/8OmLW8ozY+GsiqJe/aKd0r4lgo=; b=x7/YZjPlL55MXy3A4ZwyuNX5CMW1jR8AxkLNclQfg3a+GwbvkUoCoWzrEeK0u3dweI jiWNyT9WEEyQHP1rnx8Egd1gd4Aefml51DGdBuaWwSnYui1JSVUYNGD+fKncjf3D+T3a hWIWpFw6KJToAgGjKzj9FznZAWOYsvlt54yaVGH5gDZmK+lk5ECgqwMs3rJipNxujOra uqiuU1UJKdPEhAGChKYF8HKNUXTvKlg1Huzj6uftLq53irsPBODF/adVa1gUlaWiB6jw GIjzO7acYE4+k9MCzICU0rpSAShN/QWr3km2X/bk6XfYTHiq5jatzu6ceipysSh0NVYn CM6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758045986; x=1758650786; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d1YOtX8BVonSDnFz/8OmLW8ozY+GsiqJe/aKd0r4lgo=; b=p+0hYgzt01VuNsAVcZ2w6VY6ni8Xpgv9GbKy6EUWIAA5vc6aSs9RnZ5iT4Vfg3pLdE eGfEESpMRWCCx6oWIQwMgBeeg3lTv09sPO7YOnoqS04CsR8PHz5OVPvBMFn2lv0Fpr7G 5kAE1LbiqikZelq25MqtzpsJzdEM0U6eXqZf/oqwy0E2p+gSiGT4Nr1YAgvAeUrOMY7F Ul9Ff/bzEapzxMU+qSYGaSdN+ls4gh0OzSoStvutgQIixVpyOhiTNJb8NhGojhOf5cK6 Wk47T6iIikaaIvc6jMBnTdg0XfZrcFRjXAdZVtpbzvBXwVfO/OeYrxrNwNHZXC/TmXgQ DW7A== X-Gm-Message-State: AOJu0Yx+ywsRVpivH2dyftwEEi6pyjY4sjcK/Xr9p+HOZEmikDJEzWwA B+sj8hogYNtukxjpF7Tqst91D4ti6QxAHcpzhrhjcmAYKq0Y+M6ZN9W86z3dNdjPFxTF/DBVXvf rabRv X-Gm-Gg: ASbGnctAno1pN842Cc2sMgzys1RhtOIMIV0xYVYXtotntkB/SX6D6wUbttWxRxV7y2q CRSV42fcxnyd4GOdWYslALGW0SpqhTIymU19ZBH+aqzBpg442DDZEgTC3vC6Z4WwTEHmP8NxjcP j4EorFXvT95lawfTbVRqO+EZL+UQMYItlbgfKKQlmTSgyb9ZNPWSdE5dRwJs4UZQEw+hd8Oleow YbzWUhow0J8jSaPP5ZTlAy6dtTo/KsEr9TG5MG1wJCjjVgenz+PFf62K4vNaerDBTqLFadFS9bU LyGhF7qbTuj8uwkIjQJF56nvjK/F8d/SveQDgOA8zqrgw/xNf28VgQfbYXpTLkL75XuhRSLW0IP SPxAow48L9AsmNQvIWjuHX63sz1JM X-Google-Smtp-Source: AGHT+IF1fi3mmM0AQE7XU+b9bNI+eikHNGKr+qetIYt+ByhJZ+ArZzYCMZqtGrdO/xbFb4KugWio6A== X-Received: by 2002:a05:6000:2888:b0:3e8:6b2b:25e0 with SMTP id ffacd0b85a97d-3ec9ffa425emr3004068f8f.25.1758045985797; Tue, 16 Sep 2025 11:06:25 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/36] target/arm: Remove outdated comment for ZCR_EL12 Date: Tue, 16 Sep 2025 19:05:46 +0100 Message-ID: <20250916180611.1481266-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916180611.1481266-1-peter.maydell@linaro.org> References: <20250916180611.1481266-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758046104674116600 Content-Type: text/plain; charset="utf-8" From: Richard Henderson The comment about not being included in the summary table has been out of date for quite a while. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-id: 20250830054128.448363-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 19637e7301b..b641229ba0c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4563,11 +4563,6 @@ static void define_arm_vh_e2h_redirects_aliases(ARMC= PU *cpu) { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0), "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" }, =20 - /* - * Note that redirection of ZCR is mentioned in the description - * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but - * not in the summary table. - */ { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0), "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve }, { K(3, 0, 1, 2, 6), K(3, 4, 1, 2, 6), K(3, 5, 1, 2, 6), --=20 2.43.0 From nobody Sat Nov 15 00:45:06 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758046441; cv=none; d=zohomail.com; s=zohoarc; b=as039kf4sha0uba5Iwe4ScoQcRqwtAufks2D/GdXK0mnnZHmXvNczQtrgeMQxnogXXQVNZaE+8Ta6KiDHbhJ6a2UCj99HGWfubCkzHr+ikJ0OWxi3L0w0cN1zctr2XmdAuoZr2a4n7oYxWnWIUsVTJwyeiRmR/nDc+QRUwBUDsw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758046441; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=U5WkaCtDE6hB+ZTrL4FMHKfsJLEnw9EnHr7t9I7nEEw=; b=CbKpUK3DBM1JBkJB7v1hK+5B14SDBcO29VjnGoJvxIHeRdTAHz+9GNhPTnPzsp0Fb9/Z9UBca8bTHVSW4s2T4YtQZHyvdWO7VBaqtsjCDLfioapvxJAHnNE41jtp/MJkcTRcPJ4Ztx1dENKeeRCvYkbD5LSfb9Ebn8LHsS0TjbA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758046441903831.4884686213416; Tue, 16 Sep 2025 11:14:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uya4X-00035b-S9; Tue, 16 Sep 2025 14:06:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uya4U-00033V-Cg for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:06:30 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uya4S-0001ak-G0 for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:06:30 -0400 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-3e9042021faso2270394f8f.3 for ; Tue, 16 Sep 2025 11:06:28 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3e760775880sm23033286f8f.2.2025.09.16.11.06.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 11:06:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758045987; x=1758650787; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=U5WkaCtDE6hB+ZTrL4FMHKfsJLEnw9EnHr7t9I7nEEw=; b=ycEIoMRtfCaiWaqKpbeUHIvBQ3j2g9PISjOcsvoXGpwD0831+tqon5Mg1Fmh4DNhPM 6bKR5krq2A907EYJC7JnK2Dore4yKmw8WcHAYzKo7OuYSjL5LckQ8M5f1WDWyBikHfcF 2sAHLCMx6uCgt1/NgBIdITc8WzdMqM5GlMrBV/QpZPFNlMz2e1OcWsaWcjTSv9HWR330 mNXtz+FAbMI4Roi/uDOeXqEB0HGSuWEXRknNp9R897agaRvkMjqU44t42E48DhFXBtee k1qHeIj44OD+/u449j2+NC6Aw+lIGR0BI/M01fBXuDshXqWNqvYFXWJea2J7GcXK30Vb ecCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758045987; x=1758650787; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=U5WkaCtDE6hB+ZTrL4FMHKfsJLEnw9EnHr7t9I7nEEw=; b=nLGuNcNQ37ZHwUEP9F2pWRpYe8ID0XunHMYLLDUsyxE0mZTU1KI+SfWJzfNZ3xCk0z /gPmhVn5ljrHVygNMWtL6roCEbhuzG1OYVBzWu+UU6rJylCBk76RSogHhzgW0wvwE+es oJMo596EWvPt1kNBGhKlGERNtEyQ7ou3YOKzcketPxcZWkFpCHeGnuLMU22QMO/Ptqfc iFtKrlvqTyyTFIpydwHGIj6zqVxV3Wnx8R0GU9hMGfmf1kvG9o4dwKaFJHASflzM/JNi hkRdizkWOm74SxrdQtW8qkSOguChvjpKQ/nhqsaV/tKKOj5de5nw1kDb+9CbNjf7KuPl Kzag== X-Gm-Message-State: AOJu0Yy07wB84uIjgWQk57NzDZYUagfmSJN9cN/JjForc3e2PrlKvaH/ FtaIj0awtWWIygpvnI5Hct4Qf6E7QbpV1+6Sl4ti0zLYMBCQJM+dEgqsDvpri/+3WKcDB9b2uJt PFmlD X-Gm-Gg: ASbGncuX8mGaCNch5MHPnreScZujYbqFllJ9NB4NvOqjAk8wZcmZcYUMZmns24dOSbA N51ZztfdlZFhioKA12dDDIAAvXTLUZP73CvjsExKSpVLh0Dg3fFO02xuAcU1Op+0cgLDZgc3YZh You5i39OwWYvNhboFfAuWrdzJ0KbeKHVf072k93B7hTFOGZLlDd5gflAGxFtf7RG2Izb0uLyzSd aQFKPMVaBbW/SGJeIbACbjjx8kL9eZQcuP633L1gqwSQZC8Rr2N5r2WMnja0NpS8ICznIAUeeGN 2kk0nuPTSPtjhD+6gelNzsgw5QDtvj0AmErHZLEzXSTuKF/VhTPzA4f+8Uwn3339mkj8MJOIhK8 uNrd71YNhnnswX/StGK/YLbsq7hS3yMw98dJm1gg= X-Google-Smtp-Source: AGHT+IGZjMjkLH887yNnbk033Mg4Lza5UHfaMOYATFEYAzPLuwZSGYlxavMS1ZD/7Ap+usL9Hhncsw== X-Received: by 2002:a05:6000:2084:b0:3ec:2529:b4e5 with SMTP id ffacd0b85a97d-3ec2529b4ffmr5139199f8f.38.1758045986832; Tue, 16 Sep 2025 11:06:26 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/36] target/arm: Implement FEAT_ATS1A Date: Tue, 16 Sep 2025 19:05:47 +0100 Message-ID: <20250916180611.1481266-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916180611.1481266-1-peter.maydell@linaro.org> References: <20250916180611.1481266-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758046443359116600 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Implement FEAT_ATS1A and enable for -cpu max. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-id: 20250830054128.448363-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 1 + target/arm/cpregs.h | 1 + target/arm/cpu-features.h | 5 ++++ target/arm/tcg/cpregs-at.c | 44 +++++++++++++++++++++++++++++++++++ target/arm/tcg/cpu64.c | 1 + 5 files changed, 52 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 4e8aca8b5d5..6b04c96c8c4 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -23,6 +23,7 @@ the following architecture extensions: - FEAT_AFP (Alternate floating-point behavior) - FEAT_Armv9_Crypto (Armv9 Cryptographic Extension) - FEAT_ASID16 (16 bit ASID) +- FEAT_ATS1A (Address Translation operations that ignore stage 1 permissio= ns) - FEAT_BBM at level 2 (Translation table break-before-make levels) - FEAT_BF16 (AArch64 BFloat16 instructions) - FEAT_BTI (Branch Target Identification) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 1d103b577f7..2a4826f5c4f 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -854,6 +854,7 @@ typedef enum FGTBit { DO_BIT(HFGITR, DVPRCTX), DO_BIT(HFGITR, CPPRCTX), DO_BIT(HFGITR, DCCVAC), + DO_BIT(HFGITR, ATS1E1A), } FGTBit; =20 #undef DO_BIT diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index e49e0ae3af0..512eeaf551e 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -619,6 +619,11 @@ static inline bool isar_feature_aa64_lut(const ARMISAR= egisters *id) return FIELD_EX64_IDREG(id, ID_AA64ISAR2, LUT); } =20 +static inline bool isar_feature_aa64_ats1a(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64ISAR2, ATS1A); +} + static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) { /* We always set the AdvSIMD and FP fields identically. */ diff --git a/target/arm/tcg/cpregs-at.c b/target/arm/tcg/cpregs-at.c index bebf1689970..0e8f229aa7f 100644 --- a/target/arm/tcg/cpregs-at.c +++ b/target/arm/tcg/cpregs-at.c @@ -488,6 +488,47 @@ static const ARMCPRegInfo ats1cp_reginfo[] =3D { .writefn =3D ats_write }, }; =20 +static void ats_s1e1a(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) +{ + uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); + bool regime_e20 =3D (hcr_el2 & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | = HCR_TGE); + ARMMMUIdx mmu_idx =3D regime_e20 ? ARMMMUIdx_E20_2 : ARMMMUIdx_Stage1_= E1; + ARMSecuritySpace ss =3D arm_security_space_below_el3(env); + + env->cp15.par_el[1] =3D do_ats_write(env, value, 0, mmu_idx, ss); +} + +static void ats_s1e2a(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) +{ + uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); + ARMMMUIdx mmu_idx =3D hcr_el2 & HCR_E2H ? ARMMMUIdx_E20_2 : ARMMMUIdx_= E2; + ARMSecuritySpace ss =3D arm_security_space_below_el3(env); + + env->cp15.par_el[1] =3D do_ats_write(env, value, 0, mmu_idx, ss); +} + +static void ats_s1e3a(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) +{ + env->cp15.par_el[1] =3D do_ats_write(env, value, 0, ARMMMUIdx_E3, + arm_security_space(env)); +} + +static const ARMCPRegInfo ats1a_reginfo[] =3D { + { .name =3D "AT_S1E1A", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 2, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .fgt =3D FGT_ATS1E1A, + .accessfn =3D at_s1e01_access, .writefn =3D ats_s1e1a }, + { .name =3D "AT_S1E2A", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 9, .opc2 =3D 2, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .accessfn =3D at_s1e2_access, .writefn =3D ats_s1e2a }, + { .name =3D "AT_S1E3A", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 7, .crm =3D 9, .opc2 =3D 2, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn =3D ats_s1e3a }, +}; + void define_at_insn_regs(ARMCPU *cpu) { CPUARMState *env =3D &cpu->env; @@ -509,4 +550,7 @@ void define_at_insn_regs(ARMCPU *cpu) if (cpu_isar_feature(aa32_ats1e1, cpu)) { define_arm_cp_regs(cpu, ats1cp_reginfo); } + if (cpu_isar_feature(aa64_ats1a, cpu)) { + define_arm_cp_regs(cpu, ats1a_reginfo); + } } diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index b8b1981e702..abef6a246e8 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1179,6 +1179,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR2, BC, 1); /* FEAT_HBC */ t =3D FIELD_DP64(t, ID_AA64ISAR2, WFXT, 2); /* FEAT_WFxT */ t =3D FIELD_DP64(t, ID_AA64ISAR2, CSSC, 1); /* FEAT_CSSC */ + t =3D FIELD_DP64(t, ID_AA64ISAR2, ATS1A, 1); /* FEAT_ATS1A */ SET_IDREG(isar, ID_AA64ISAR2, t); =20 t =3D GET_IDREG(isar, ID_AA64PFR0); --=20 2.43.0 From nobody Sat Nov 15 00:45:06 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758046443; cv=none; d=zohomail.com; s=zohoarc; b=EP8GHGBgu5+8K/bWs5b08KCKHji0hMZBowznetMCu7/7aMaWhq6uUVBbQrJs2vaObewgJXRNRu1jYtTJGQjI5A3nyZblpSRBUaaYrRPgNA8d9UprdZS0oIRezcE7P7m0yjqhHtgFyTng6oD7k07yIH4o2E85LhRS7pYqOrF3zjQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758046443; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=81pXE1kDQVjDPPfH3enW9tfmeo8/1W7sfykAV4zpEFs=; b=CQ10GEN+DwlC7YPLDXU49b3OZAZKtXIfg7/oDQWO/2P0VtEKcbOxWGAFZy9wEX3JaxECY2jUpRZLmpPnOiNzEri2et5rAZhKERnRcjy5RgEZ8WnR7pVXdVIjl8YM827/kuVoftSgliKB/7bKPBxRRC/0yK0T16faR7k0Vo2fc2Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758046443686590.8819618090431; Tue, 16 Sep 2025 11:14:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uya4X-00035g-TC; Tue, 16 Sep 2025 14:06:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uya4V-00034z-SX for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:06:32 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uya4T-0001au-Ph for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:06:31 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-45dec026c78so58632485e9.0 for ; Tue, 16 Sep 2025 11:06:29 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3e760775880sm23033286f8f.2.2025.09.16.11.06.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 11:06:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758045988; x=1758650788; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=81pXE1kDQVjDPPfH3enW9tfmeo8/1W7sfykAV4zpEFs=; b=Duo4Xph9P8dB94M7JP3EYvNJQYV+eF2Cqa9GOCsek7DYZVT8C/97Wbabe4wo22jxQO 5b1U/RZW1pkgsxpo+CJ5eMqPWph5JXM+McWipLE+qUMy8FlPh8iXHlbjEaz+j3GWCFVD v8hWeaFV/466BUOfbm3XJhMqFnZCEQC9iMvqAeC4jS8SBND46dXTBXavDXfOSA23bOXF tKxwKDhkp2ZCEl/fH82VIFp3fEmXNA7XgLUSe5jdw6vMJmHMn6IYMufsf+lM2axtesfH 3jQO8DjQTw6LOac4gEyMeHw2rHip0EBwEbnFwTeXTvqFoVPXnFmQv2kPw5UlRqRsvixj Gt3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758045988; x=1758650788; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=81pXE1kDQVjDPPfH3enW9tfmeo8/1W7sfykAV4zpEFs=; b=orDqWXn/Bd6fboGtv4IkN7fU+vO/Nyhl70y/mAp0gfOW84e12pZ2ba2UVsyQhX6WD/ Cekc6rQ5dnXNNP8o+kO6N7t30Du1i7YopoqBW57YHxWDyvFME6khiEzoiY7OnHIx8KxT AMOV/fW0F3kWBwBJE5QGPns7bLJO16nqpycBTf7Ok7xAkfA/+ScZTjmaM4lypis81R7G L1NRnuLIsm1Bk43dH8MupNgBhNJXzDk2dDqbWdiXkYJ/VzF1uN9I8V/iahWeQZq+97Hx zvGixhCzq4AOMsWmggerq5b769XHkXiWaKb8RQp3cdOoYrrdodHI2eTD8duu42G+Ir3B 40Qg== X-Gm-Message-State: AOJu0YyJiIYAr3o/hff+ht/CXJMcjd0BcQ5DcS+AdJKJnXrKoNuQN7O/ h1b8tAgTx2GAry4Vjw216PrHJ+fEp++4SDwC0wzMrsgqeTsBaSYcF5AMxuY1zaI7wMG1YMrgbmm 26XQr X-Gm-Gg: ASbGnctwB1v4feEYVjJNiTcab9OgV3z7ynqGuz3c43yCGEVfiJUw1Qumk9X2hFfWODM oUvrjRNPXGH195SYaMgpMXetEoGDlM45ecrkS2qgiQh2DYHYA68reDZyAtMDggRBoZF2xuthGso B77TNN07f1PpNLvH/813uOLN98KK56YGSXj2oE3XYa3+ReOn0T+4ackzIpwEC0wRE9mKbwnSi5L ABDRJ/cydCa6DOWYEV+eyyvIXu6cOZ6NkoZTWVMyEc3b9dnAKhOsgbJ1BhGUAM/Vqi/c33ZZakV MrNB07//wr+fVmGvXhK0rlxPYzoKGVSHePeBZ9nHJhtXEc3ctQEiPzLdlkQXeKi5wcdbLkNigMG XHTHgo2KsAV5iiCgKhDhe/6HaaBOr X-Google-Smtp-Source: AGHT+IHuQGlsxLMbpaL+EqVM2QX50MEwqvKvApkrj9WmAGhTEMnKjhUDKB2tUdOV5tKszyJBPgOTnA== X-Received: by 2002:a05:600c:458a:b0:45d:d1a3:ba6a with SMTP id 5b1f17b1804b1-45f2218d97dmr179878095e9.33.1758045987756; Tue, 16 Sep 2025 11:06:27 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/36] hw/arm/raspi4b: remove redundant check in raspi_add_memory_node Date: Tue, 16 Sep 2025 19:05:48 +0100 Message-ID: <20250916180611.1481266-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916180611.1481266-1-peter.maydell@linaro.org> References: <20250916180611.1481266-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758046445195116600 From: Osama Abdelkader The if (acells =3D=3D 0 || scells =3D=3D 0) check is redundant in raspi_add_memory_node, since it is already checked in the call chain, arm_load_dtb. Also the return value of the function is not checked/used so it's removed. Signed-off-by: Osama Abdelkader Reviewed-by: Alex Benn=C3=A9e Tested-by: Alex Benn=C3=A9e Message-id: 20250902200818.43305-1-osama.abdelkader@gmail.com Signed-off-by: Peter Maydell --- hw/arm/raspi4b.c | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/hw/arm/raspi4b.c b/hw/arm/raspi4b.c index 20082d52667..4df951a0d82 100644 --- a/hw/arm/raspi4b.c +++ b/hw/arm/raspi4b.c @@ -36,9 +36,8 @@ struct Raspi4bMachineState { * (see https://datasheets.raspberrypi.com/bcm2711/bcm2711-peripherals.pdf * 1.2 Address Map) */ -static int raspi_add_memory_node(void *fdt, hwaddr mem_base, hwaddr mem_le= n) +static void raspi_add_memory_node(void *fdt, hwaddr mem_base, hwaddr mem_l= en) { - int ret; uint32_t acells, scells; char *nodename =3D g_strdup_printf("/memory@%" PRIx64, mem_base); =20 @@ -46,19 +45,16 @@ static int raspi_add_memory_node(void *fdt, hwaddr mem_= base, hwaddr mem_len) NULL, &error_fatal); scells =3D qemu_fdt_getprop_cell(fdt, "/", "#size-cells", NULL, &error_fatal); - if (acells =3D=3D 0 || scells =3D=3D 0) { - fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0= )\n"); - ret =3D -1; - } else { - qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); - ret =3D qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", - acells, mem_base, - scells, mem_len); - } + /* validated by arm_load_dtb */ + g_assert(acells && scells); + + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); + qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", + acells, mem_base, + scells, mem_len); =20 g_free(nodename); - return ret; } =20 static void raspi4_modify_dtb(const struct arm_boot_info *info, void *fdt) --=20 2.43.0 From nobody Sat Nov 15 00:45:06 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758046319; cv=none; d=zohomail.com; s=zohoarc; b=BySBnu52sGD7HRFzjcjiJWdmehXe5ndSkd6m/zV1Sppgb/pqz/wczOtdR5aux62lWXZCPkV8YtllWH0Qho6UGlC1RPoG5IzzYWWd/wVGltprzyjQHAMbDLeUn7/zyJrHw0wosGThD+71IrdXc2QF4xxsw6MqeYCG0qILhzf6/48= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758046319; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=962IUHk4Fm5KFmeKbrFTpPCwGn8ge5yNRC9E10wxbT4=; b=UebZcCyHMLrsy4XX/gNDYaO0B4JuBibVzYiskhFqwQZ6LryDVZCktqzTnxo0st2GbRIjVmzMfPhVqQOzsgHRYkwSb7GgvncGR+eH5N8q/LGA5CbDu0ZeeSa1RwpAE7yhBI7r1k8/1JLFCXOvm0MXeHJFolhBBklIhCDixDY3/io= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175804631907374.48352829275564; Tue, 16 Sep 2025 11:11:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uya4a-000370-Cj; Tue, 16 Sep 2025 14:06:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uya4X-00035i-Rs for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:06:34 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uya4U-0001bH-IC for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:06:33 -0400 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-45dcfecdc0fso58276305e9.1 for ; Tue, 16 Sep 2025 11:06:30 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3e760775880sm23033286f8f.2.2025.09.16.11.06.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 11:06:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758045989; x=1758650789; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=962IUHk4Fm5KFmeKbrFTpPCwGn8ge5yNRC9E10wxbT4=; b=sPaQS4P+BSRsyuDiiWdQgMOdQ94/Fc/UqV8VlGd9skSAN6pMZ8ZGehUJV2xPhvenc4 8vODIVtkwGbHM6Yvv2gfnC/RiDa79MSid66CiMhB5VOOhJo7jmwkJxF/TOlAl2oHyWU4 tmAENKpEKvxl4voWMo0ip+s23puvJ9rqdEd3mWOhvhJzmZR5e/bHj3NE8qZmajWRYW2B pnFFuPVqJUhxI05kW3Gw+iD5a8m4swtVCM8xmT2sMlbquB8nsF5xCAY3LNgf6a97dAFq miTqYn+0CBaa00MKqIZXB9jL2Wa2tsl/plib4S66UKnneKRkJBLLDohV9+jDZ2lmHB7F 1rxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758045989; x=1758650789; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=962IUHk4Fm5KFmeKbrFTpPCwGn8ge5yNRC9E10wxbT4=; b=Pnkjn/pf70TGtN/GxmDPm8rT/0hmoK7PPy2uPaRtuKGAASgsv6s3PimSqoc6AEozhi Yz9vCY91csBLK204w56k6AmhkK2+y4bFUZryeQYD1KDQ4HgY5kz3WJahS6drjIdmpc2u bF+qJ9PY7bQEW6tWzfXMBMs1Iyv6OhkrHkcL5jJCI9ESpdvxtnUUYMPAvRwDrVeU4aGN 7O/ZVOi2pjtNN2ABO6oT51UIqBRR2CEkB4KXzD59nLqVkHPLa6UDlku3FkVynNYYgGe1 NH3wjf7TRzpTfu1m908BWHNhAhXrx4QiqAqV4pdPIzvZW4QFiRFmwjAgGGlgXv3ofdQb jctg== X-Gm-Message-State: AOJu0YxAI2Z8/7upxZ90vXOixyRl+dXc/2VA5hu1WBU7LUFc2TQZntU1 C48pG5V2q2a3oW+dIZAXbWf1xN82he/5SMT2GROfcdRcOZBkFjE2VRTXqXgADDNNqh2kxBZ5Q1x 8P1KR X-Gm-Gg: ASbGnctPM1Fa+q42ocyW4DxLP66Nz7hXPqNE7TERaNYK+mP9HRdWATdPprwJI1SMoyK +fsWhJ3jOE44d2YyPWLwhQ8HJ0stZ4YxHb0Ejqo8Gu8CRIB5yUmqSmDnWWRf+V6TQCpCBcPIS57 COemJn7pFdE6EUb1rI9rDsnRtLdLoAO6LQVcz26cVyV8wOTIdueR1T0QO8n3xBiMvYbrb31zPLD iOh2mCDsY+hju24AaNTIDQCigts38+6xy8p82d2ehjXciKnHjU3ZWtQQ+wvdo/bntxVF1TAUHDc abM0OmXky93hf/wxXdBcwPahSh5icLQaXPWacoA5/yFz5GBa2plTBQZgUumRV+I7NiXY8Vjsb8e VbDCXhT98hIezXFtStxzpi/C6EiJZ X-Google-Smtp-Source: AGHT+IFEXCWxSB5HAmMaNbHPRz3FibqOa9ns3O5p9NQ2qAhRyzaKMOqZepNY6usatT4uSFI3CD68Hw== X-Received: by 2002:a7b:cd97:0:b0:45d:f7dc:f71 with SMTP id 5b1f17b1804b1-45f211efc4dmr129586365e9.25.1758045988713; Tue, 16 Sep 2025 11:06:28 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/36] target/arm: Remove deprecated pxa CPU family Date: Tue, 16 Sep 2025 19:05:49 +0100 Message-ID: <20250916180611.1481266-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916180611.1481266-1-peter.maydell@linaro.org> References: <20250916180611.1481266-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758046321487116600 In 10.0 we deprecated the pxa CPU family (pxa250, pxa255, pxa260 pxa261, pxa262, pxa270-a0, pxa270-a1, pxa270, pxa270-b0, pxa270-b1, pxa270-c0, pxa270-c5). Now we have released 10.1 we can remove them. This commit removes only the top level CPU definitions and updates the documentation. Removing the CPUs means that there is now a lot of dead iwMMXt code, which we will delete in subsequent commits. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20250828140422.3271703-2-peter.maydell@linaro.org --- docs/about/deprecated.rst | 21 ---- docs/about/removed-features.rst | 14 +++ target/arm/tcg/cpu32.c | 163 -------------------------------- 3 files changed, 14 insertions(+), 184 deletions(-) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index b2420732e1d..f0314147698 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -236,27 +236,6 @@ Keeping 32-bit host support alive is a substantial bur= den for the QEMU project. Thus QEMU will in future drop the support for all 32-bit host systems. =20 -linux-user mode CPUs --------------------- - -iwMMXt emulation and the ``pxa`` CPUs (since 10.0) -'''''''''''''''''''''''''''''''''''''''''''''''''' - -The ``pxa`` CPU family (``pxa250``, ``pxa255``, ``pxa260``, -``pxa261``, ``pxa262``, ``pxa270-a0``, ``pxa270-a1``, ``pxa270``, -``pxa270-b0``, ``pxa270-b1``, ``pxa270-c0``, ``pxa270-c5``) are no -longer used in system emulation, because all the machine types which -used these CPUs were removed in the QEMU 9.2 release. These CPUs can -now only be used in linux-user mode, and to do that you would have to -explicitly select one of these CPUs with the ``-cpu`` command line -option or the ``QEMU_CPU`` environment variable. - -We don't believe that anybody is using the iwMMXt emulation, and we do -not have any tests to validate it or any real hardware or similar -known-good implementation to test against. GCC is in the process of -dropping their support for iwMMXt codegen. These CPU types are -therefore deprecated in QEMU, and will be removed in a future release. - System emulator CPUs -------------------- =20 diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.= rst index fff781d6b7c..65fd564d229 100644 --- a/docs/about/removed-features.rst +++ b/docs/about/removed-features.rst @@ -1138,6 +1138,20 @@ reason the maintainers strongly suspected no one act= ually used it. QEMU Nios II architecture was orphan; Intel has EOL'ed the Nios II processor IP (see `Intel discontinuance notification`_). =20 +iwMMXt emulation and the ``pxa`` CPUs (removed in 10.2) +''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +The ``pxa`` CPU family (``pxa250``, ``pxa255``, ``pxa260``, +``pxa261``, ``pxa262``, ``pxa270-a0``, ``pxa270-a1``, ``pxa270``, +``pxa270-b0``, ``pxa270-b1``, ``pxa270-c0``, ``pxa270-c5``) were +not available in system emulation, because all the machine types which +used these CPUs were removed in the QEMU 9.2 release. We don't +believe that anybody was using the iwMMXt emulation (which you +would have to explicitly enable on the command line), and we did +not have any tests to validate it or any real hardware or similar +known-good implementation to test against. These CPUs have +therefore been removed in linux-user mode as well. + TCG introspection features -------------------------- =20 diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index a2a23eae0d7..f0761410ad0 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -807,144 +807,6 @@ static void sa1110_initfn(Object *obj) cpu->reset_sctlr =3D 0x00000070; } =20 -static void pxa250_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - cpu->midr =3D 0x69052100; - cpu->ctr =3D 0xd172172; - cpu->reset_sctlr =3D 0x00000078; -} - -static void pxa255_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - cpu->midr =3D 0x69052d00; - cpu->ctr =3D 0xd172172; - cpu->reset_sctlr =3D 0x00000078; -} - -static void pxa260_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - cpu->midr =3D 0x69052903; - cpu->ctr =3D 0xd172172; - cpu->reset_sctlr =3D 0x00000078; -} - -static void pxa261_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - cpu->midr =3D 0x69052d05; - cpu->ctr =3D 0xd172172; - cpu->reset_sctlr =3D 0x00000078; -} - -static void pxa262_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - cpu->midr =3D 0x69052d06; - cpu->ctr =3D 0xd172172; - cpu->reset_sctlr =3D 0x00000078; -} - -static void pxa270a0_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - set_feature(&cpu->env, ARM_FEATURE_IWMMXT); - cpu->midr =3D 0x69054110; - cpu->ctr =3D 0xd172172; - cpu->reset_sctlr =3D 0x00000078; -} - -static void pxa270a1_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - set_feature(&cpu->env, ARM_FEATURE_IWMMXT); - cpu->midr =3D 0x69054111; - cpu->ctr =3D 0xd172172; - cpu->reset_sctlr =3D 0x00000078; -} - -static void pxa270b0_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - set_feature(&cpu->env, ARM_FEATURE_IWMMXT); - cpu->midr =3D 0x69054112; - cpu->ctr =3D 0xd172172; - cpu->reset_sctlr =3D 0x00000078; -} - -static void pxa270b1_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - set_feature(&cpu->env, ARM_FEATURE_IWMMXT); - cpu->midr =3D 0x69054113; - cpu->ctr =3D 0xd172172; - cpu->reset_sctlr =3D 0x00000078; -} - -static void pxa270c0_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - set_feature(&cpu->env, ARM_FEATURE_IWMMXT); - cpu->midr =3D 0x69054114; - cpu->ctr =3D 0xd172172; - cpu->reset_sctlr =3D 0x00000078; -} - -static void pxa270c5_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - set_feature(&cpu->env, ARM_FEATURE_IWMMXT); - cpu->midr =3D 0x69054117; - cpu->ctr =3D 0xd172172; - cpu->reset_sctlr =3D 0x00000078; -} - #ifndef TARGET_AARCH64 /* * -cpu max: a CPU with as many features enabled as our emulation supports. @@ -1032,31 +894,6 @@ static const ARMCPUInfo arm_tcg_cpus[] =3D { { .name =3D "ti925t", .initfn =3D ti925t_initfn }, { .name =3D "sa1100", .initfn =3D sa1100_initfn }, { .name =3D "sa1110", .initfn =3D sa1110_initfn }, - { .name =3D "pxa250", .initfn =3D pxa250_initfn, - .deprecation_note =3D "iwMMXt CPUs are no longer supported", }, - { .name =3D "pxa255", .initfn =3D pxa255_initfn, - .deprecation_note =3D "iwMMXt CPUs are no longer supported", }, - { .name =3D "pxa260", .initfn =3D pxa260_initfn, - .deprecation_note =3D "iwMMXt CPUs are no longer supported", }, - { .name =3D "pxa261", .initfn =3D pxa261_initfn, - .deprecation_note =3D "iwMMXt CPUs are no longer supported", }, - { .name =3D "pxa262", .initfn =3D pxa262_initfn, - .deprecation_note =3D "iwMMXt CPUs are no longer supported", }, - /* "pxa270" is an alias for "pxa270-a0" */ - { .name =3D "pxa270", .initfn =3D pxa270a0_initfn, - .deprecation_note =3D "iwMMXt CPUs are no longer supported", }, - { .name =3D "pxa270-a0", .initfn =3D pxa270a0_initfn, - .deprecation_note =3D "iwMMXt CPUs are no longer supported", }, - { .name =3D "pxa270-a1", .initfn =3D pxa270a1_initfn, - .deprecation_note =3D "iwMMXt CPUs are no longer supported", }, - { .name =3D "pxa270-b0", .initfn =3D pxa270b0_initfn, - .deprecation_note =3D "iwMMXt CPUs are no longer supported", }, - { .name =3D "pxa270-b1", .initfn =3D pxa270b1_initfn, - .deprecation_note =3D "iwMMXt CPUs are no longer supported", }, - { .name =3D "pxa270-c0", .initfn =3D pxa270c0_initfn, - .deprecation_note =3D "iwMMXt CPUs are no longer supported", }, - { .name =3D "pxa270-c5", .initfn =3D pxa270c5_initfn, - .deprecation_note =3D "iwMMXt CPUs are no longer supported", }, #ifndef TARGET_AARCH64 { .name =3D "max", .initfn =3D arm_max_initfn }, #endif --=20 2.43.0 From nobody Sat Nov 15 00:45:06 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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This includes the xscale-only cp15_cpar TB flags and cpu_{V0,V1,M0} TCG temps. The no-longer-used helper functions will be removed in a separate commit. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20250828140422.3271703-3-peter.maydell@linaro.org --- target/arm/cpu.h | 7 - target/arm/tcg/translate.h | 2 - target/arm/tcg/hflags.c | 13 +- target/arm/tcg/translate.c | 1324 +----------------------------------- 4 files changed, 7 insertions(+), 1339 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c15d79a106b..f56fa6df8dd 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3025,13 +3025,6 @@ FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cach= ed. */ */ FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ -/* - * We store the bottom two bits of the CPAR as TB flags and handle - * checks on the other bits at runtime. This shares the same bits as - * VECSTRIDE, which is OK as no XScale CPU has VFP. - * Not cached, because VECLEN+VECSTRIDE are not cached. - */ -FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2) FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index f974996f3f8..ec4755ae3fd 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -175,8 +175,6 @@ typedef struct DisasContext { uint8_t gm_blocksize; /* True if the current insn_start has been updated. */ bool insn_start_updated; - /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ - int c15_cpar; /* Offset from VNCR_EL2 when FEAT_NV2 redirects this reg to memory */ uint32_t nv2_redirect_offset; } DisasContext; diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index 59ab5263753..01894226cc9 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -624,16 +624,9 @@ TCGTBCPUState arm_get_tb_cpu_state(CPUState *cs) DP_TBFLAG_M32(flags, MVE_NO_PRED, 1); } } else { - /* - * Note that XSCALE_CPAR shares bits with VECSTRIDE. - * Note that VECLEN+VECSTRIDE are RES0 for M-profile. - */ - if (arm_feature(env, ARM_FEATURE_XSCALE)) { - DP_TBFLAG_A32(flags, XSCALE_CPAR, env->cp15.c15_cpar); - } else { - DP_TBFLAG_A32(flags, VECLEN, env->vfp.vec_len); - DP_TBFLAG_A32(flags, VECSTRIDE, env->vfp.vec_stride); - } + /* Note that VECLEN+VECSTRIDE are RES0 for M-profile. */ + DP_TBFLAG_A32(flags, VECLEN, env->vfp.vec_len); + DP_TBFLAG_A32(flags, VECSTRIDE, env->vfp.vec_stride); if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { DP_TBFLAG_A32(flags, VFPEN, 1); } diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index f7d6d8ce196..e62dcc5d85d 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -44,8 +44,6 @@ #define ENABLE_ARCH_7 arm_dc_feature(s, ARM_FEATURE_V7) #define ENABLE_ARCH_8 arm_dc_feature(s, ARM_FEATURE_V8) =20 -/* These are TCG temporaries used only by the legacy iwMMXt decoder */ -static TCGv_i64 cpu_V0, cpu_V1, cpu_M0; /* These are TCG globals which alias CPUARMState fields */ static TCGv_i32 cpu_R[16]; TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF; @@ -1252,1263 +1250,6 @@ void write_neon_element64(TCGv_i64 src, int reg, i= nt ele, MemOp memop) } } =20 -#define ARM_CP_RW_BIT (1 << 20) - -static inline void iwmmxt_load_reg(TCGv_i64 var, int reg) -{ - tcg_gen_ld_i64(var, tcg_env, offsetof(CPUARMState, iwmmxt.regs[reg])); -} - -static inline void iwmmxt_store_reg(TCGv_i64 var, int reg) -{ - tcg_gen_st_i64(var, tcg_env, offsetof(CPUARMState, iwmmxt.regs[reg])); -} - -static inline TCGv_i32 iwmmxt_load_creg(int reg) -{ - TCGv_i32 var =3D tcg_temp_new_i32(); - tcg_gen_ld_i32(var, tcg_env, offsetof(CPUARMState, iwmmxt.cregs[reg])); - return var; -} - -static inline void iwmmxt_store_creg(int reg, TCGv_i32 var) -{ - tcg_gen_st_i32(var, tcg_env, offsetof(CPUARMState, iwmmxt.cregs[reg])); -} - -static inline void gen_op_iwmmxt_movq_wRn_M0(int rn) -{ - iwmmxt_store_reg(cpu_M0, rn); -} - -static inline void gen_op_iwmmxt_movq_M0_wRn(int rn) -{ - iwmmxt_load_reg(cpu_M0, rn); -} - -static inline void gen_op_iwmmxt_orq_M0_wRn(int rn) -{ - iwmmxt_load_reg(cpu_V1, rn); - tcg_gen_or_i64(cpu_M0, cpu_M0, cpu_V1); -} - -static inline void gen_op_iwmmxt_andq_M0_wRn(int rn) -{ - iwmmxt_load_reg(cpu_V1, rn); - tcg_gen_and_i64(cpu_M0, cpu_M0, cpu_V1); -} - -static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn) -{ - iwmmxt_load_reg(cpu_V1, rn); - tcg_gen_xor_i64(cpu_M0, cpu_M0, cpu_V1); -} - -#define IWMMXT_OP(name) \ -static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \ -{ \ - iwmmxt_load_reg(cpu_V1, rn); \ - gen_helper_iwmmxt_##name(cpu_M0, cpu_M0, cpu_V1); \ -} - -#define IWMMXT_OP_ENV(name) \ -static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \ -{ \ - iwmmxt_load_reg(cpu_V1, rn); \ - gen_helper_iwmmxt_##name(cpu_M0, tcg_env, cpu_M0, cpu_V1); \ -} - -#define IWMMXT_OP_ENV_SIZE(name) \ -IWMMXT_OP_ENV(name##b) \ -IWMMXT_OP_ENV(name##w) \ -IWMMXT_OP_ENV(name##l) - -#define IWMMXT_OP_ENV1(name) \ -static inline void gen_op_iwmmxt_##name##_M0(void) \ -{ \ - gen_helper_iwmmxt_##name(cpu_M0, tcg_env, cpu_M0); \ -} - -IWMMXT_OP(maddsq) -IWMMXT_OP(madduq) -IWMMXT_OP(sadb) -IWMMXT_OP(sadw) -IWMMXT_OP(mulslw) -IWMMXT_OP(mulshw) -IWMMXT_OP(mululw) -IWMMXT_OP(muluhw) -IWMMXT_OP(macsw) -IWMMXT_OP(macuw) - -IWMMXT_OP_ENV_SIZE(unpackl) -IWMMXT_OP_ENV_SIZE(unpackh) - -IWMMXT_OP_ENV1(unpacklub) -IWMMXT_OP_ENV1(unpackluw) -IWMMXT_OP_ENV1(unpacklul) -IWMMXT_OP_ENV1(unpackhub) -IWMMXT_OP_ENV1(unpackhuw) -IWMMXT_OP_ENV1(unpackhul) -IWMMXT_OP_ENV1(unpacklsb) -IWMMXT_OP_ENV1(unpacklsw) -IWMMXT_OP_ENV1(unpacklsl) -IWMMXT_OP_ENV1(unpackhsb) -IWMMXT_OP_ENV1(unpackhsw) -IWMMXT_OP_ENV1(unpackhsl) - -IWMMXT_OP_ENV_SIZE(cmpeq) -IWMMXT_OP_ENV_SIZE(cmpgtu) -IWMMXT_OP_ENV_SIZE(cmpgts) - -IWMMXT_OP_ENV_SIZE(mins) -IWMMXT_OP_ENV_SIZE(minu) -IWMMXT_OP_ENV_SIZE(maxs) -IWMMXT_OP_ENV_SIZE(maxu) - -IWMMXT_OP_ENV_SIZE(subn) -IWMMXT_OP_ENV_SIZE(addn) -IWMMXT_OP_ENV_SIZE(subu) -IWMMXT_OP_ENV_SIZE(addu) -IWMMXT_OP_ENV_SIZE(subs) -IWMMXT_OP_ENV_SIZE(adds) - -IWMMXT_OP_ENV(avgb0) -IWMMXT_OP_ENV(avgb1) -IWMMXT_OP_ENV(avgw0) -IWMMXT_OP_ENV(avgw1) - -IWMMXT_OP_ENV(packuw) -IWMMXT_OP_ENV(packul) -IWMMXT_OP_ENV(packuq) -IWMMXT_OP_ENV(packsw) -IWMMXT_OP_ENV(packsl) -IWMMXT_OP_ENV(packsq) - -static void gen_op_iwmmxt_set_mup(void) -{ - TCGv_i32 tmp; - tmp =3D load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]); - tcg_gen_ori_i32(tmp, tmp, 2); - store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]); -} - -static void gen_op_iwmmxt_set_cup(void) -{ - TCGv_i32 tmp; - tmp =3D load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]); - tcg_gen_ori_i32(tmp, tmp, 1); - store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]); -} - -static void gen_op_iwmmxt_setpsr_nz(void) -{ - TCGv_i32 tmp =3D tcg_temp_new_i32(); - gen_helper_iwmmxt_setpsr_nz(tmp, cpu_M0); - store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCASF]); -} - -static inline void gen_op_iwmmxt_addl_M0_wRn(int rn) -{ - iwmmxt_load_reg(cpu_V1, rn); - tcg_gen_ext32u_i64(cpu_V1, cpu_V1); - tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1); -} - -static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn, - TCGv_i32 dest) -{ - int rd; - uint32_t offset; - TCGv_i32 tmp; - - rd =3D (insn >> 16) & 0xf; - tmp =3D load_reg(s, rd); - - offset =3D (insn & 0xff) << ((insn >> 7) & 2); - if (insn & (1 << 24)) { - /* Pre indexed */ - if (insn & (1 << 23)) - tcg_gen_addi_i32(tmp, tmp, offset); - else - tcg_gen_addi_i32(tmp, tmp, -offset); - tcg_gen_mov_i32(dest, tmp); - if (insn & (1 << 21)) { - store_reg(s, rd, tmp); - } - } else if (insn & (1 << 21)) { - /* Post indexed */ - tcg_gen_mov_i32(dest, tmp); - if (insn & (1 << 23)) - tcg_gen_addi_i32(tmp, tmp, offset); - else - tcg_gen_addi_i32(tmp, tmp, -offset); - store_reg(s, rd, tmp); - } else if (!(insn & (1 << 23))) - return 1; - return 0; -} - -static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask, TCGv_i32 = dest) -{ - int rd =3D (insn >> 0) & 0xf; - TCGv_i32 tmp; - - if (insn & (1 << 8)) { - if (rd < ARM_IWMMXT_wCGR0 || rd > ARM_IWMMXT_wCGR3) { - return 1; - } else { - tmp =3D iwmmxt_load_creg(rd); - } - } else { - tmp =3D tcg_temp_new_i32(); - iwmmxt_load_reg(cpu_V0, rd); - tcg_gen_extrl_i64_i32(tmp, cpu_V0); - } - tcg_gen_andi_i32(tmp, tmp, mask); - tcg_gen_mov_i32(dest, tmp); - return 0; -} - -/* Disassemble an iwMMXt instruction. Returns nonzero if an error occurred - (ie. an undefined instruction). */ -static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) -{ - int rd, wrd; - int rdhi, rdlo, rd0, rd1, i; - TCGv_i32 addr; - TCGv_i32 tmp, tmp2, tmp3; - - if ((insn & 0x0e000e00) =3D=3D 0x0c000000) { - if ((insn & 0x0fe00ff0) =3D=3D 0x0c400000) { - wrd =3D insn & 0xf; - rdlo =3D (insn >> 12) & 0xf; - rdhi =3D (insn >> 16) & 0xf; - if (insn & ARM_CP_RW_BIT) { /* TMRRC */ - iwmmxt_load_reg(cpu_V0, wrd); - tcg_gen_extrl_i64_i32(cpu_R[rdlo], cpu_V0); - tcg_gen_extrh_i64_i32(cpu_R[rdhi], cpu_V0); - } else { /* TMCRR */ - tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]); - iwmmxt_store_reg(cpu_V0, wrd); - gen_op_iwmmxt_set_mup(); - } - return 0; - } - - wrd =3D (insn >> 12) & 0xf; - addr =3D tcg_temp_new_i32(); - if (gen_iwmmxt_address(s, insn, addr)) { - return 1; - } - if (insn & ARM_CP_RW_BIT) { - if ((insn >> 28) =3D=3D 0xf) { /* WLDRW wCx */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - iwmmxt_store_creg(wrd, tmp); - } else { - i =3D 1; - if (insn & (1 << 8)) { - if (insn & (1 << 22)) { /* WLDRD */ - gen_aa32_ld64(s, cpu_M0, addr, get_mem_index(s)); - i =3D 0; - } else { /* WLDRW wRd */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - } - } else { - tmp =3D tcg_temp_new_i32(); - if (insn & (1 << 22)) { /* WLDRH */ - gen_aa32_ld16u(s, tmp, addr, get_mem_index(s)); - } else { /* WLDRB */ - gen_aa32_ld8u(s, tmp, addr, get_mem_index(s)); - } - } - if (i) { - tcg_gen_extu_i32_i64(cpu_M0, tmp); - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - } - } else { - if ((insn >> 28) =3D=3D 0xf) { /* WSTRW wCx */ - tmp =3D iwmmxt_load_creg(wrd); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - } else { - gen_op_iwmmxt_movq_M0_wRn(wrd); - tmp =3D tcg_temp_new_i32(); - if (insn & (1 << 8)) { - if (insn & (1 << 22)) { /* WSTRD */ - gen_aa32_st64(s, cpu_M0, addr, get_mem_index(s)); - } else { /* WSTRW wRd */ - tcg_gen_extrl_i64_i32(tmp, cpu_M0); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - } - } else { - if (insn & (1 << 22)) { /* WSTRH */ - tcg_gen_extrl_i64_i32(tmp, cpu_M0); - gen_aa32_st16(s, tmp, addr, get_mem_index(s)); - } else { /* WSTRB */ - tcg_gen_extrl_i64_i32(tmp, cpu_M0); - gen_aa32_st8(s, tmp, addr, get_mem_index(s)); - } - } - } - } - return 0; - } - - if ((insn & 0x0f000000) !=3D 0x0e000000) - return 1; - - switch (((insn >> 12) & 0xf00) | ((insn >> 4) & 0xff)) { - case 0x000: /* WOR */ - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 0) & 0xf; - rd1 =3D (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - gen_op_iwmmxt_orq_M0_wRn(rd1); - gen_op_iwmmxt_setpsr_nz(); - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x011: /* TMCR */ - if (insn & 0xf) - return 1; - rd =3D (insn >> 12) & 0xf; - wrd =3D (insn >> 16) & 0xf; - switch (wrd) { - case ARM_IWMMXT_wCID: - case ARM_IWMMXT_wCASF: - break; - case ARM_IWMMXT_wCon: - gen_op_iwmmxt_set_cup(); - /* Fall through. */ - case ARM_IWMMXT_wCSSF: - tmp =3D iwmmxt_load_creg(wrd); - tmp2 =3D load_reg(s, rd); - tcg_gen_andc_i32(tmp, tmp, tmp2); - iwmmxt_store_creg(wrd, tmp); - break; - case ARM_IWMMXT_wCGR0: - case ARM_IWMMXT_wCGR1: - case ARM_IWMMXT_wCGR2: - case ARM_IWMMXT_wCGR3: - gen_op_iwmmxt_set_cup(); - tmp =3D load_reg(s, rd); - iwmmxt_store_creg(wrd, tmp); - break; - default: - return 1; - } - break; - case 0x100: /* WXOR */ - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 0) & 0xf; - rd1 =3D (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - gen_op_iwmmxt_xorq_M0_wRn(rd1); - gen_op_iwmmxt_setpsr_nz(); - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x111: /* TMRC */ - if (insn & 0xf) - return 1; - rd =3D (insn >> 12) & 0xf; - wrd =3D (insn >> 16) & 0xf; - tmp =3D iwmmxt_load_creg(wrd); - store_reg(s, rd, tmp); - break; - case 0x300: /* WANDN */ - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 0) & 0xf; - rd1 =3D (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - tcg_gen_neg_i64(cpu_M0, cpu_M0); - gen_op_iwmmxt_andq_M0_wRn(rd1); - gen_op_iwmmxt_setpsr_nz(); - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x200: /* WAND */ - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 0) & 0xf; - rd1 =3D (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - gen_op_iwmmxt_andq_M0_wRn(rd1); - gen_op_iwmmxt_setpsr_nz(); - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x810: case 0xa10: /* WMADD */ - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 0) & 0xf; - rd1 =3D (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - if (insn & (1 << 21)) - gen_op_iwmmxt_maddsq_M0_wRn(rd1); - else - gen_op_iwmmxt_madduq_M0_wRn(rd1); - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - break; - case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */ - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - rd1 =3D (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - switch ((insn >> 22) & 3) { - case 0: - gen_op_iwmmxt_unpacklb_M0_wRn(rd1); - break; - case 1: - gen_op_iwmmxt_unpacklw_M0_wRn(rd1); - break; - case 2: - gen_op_iwmmxt_unpackll_M0_wRn(rd1); - break; - case 3: - return 1; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */ - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - rd1 =3D (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - switch ((insn >> 22) & 3) { - case 0: - gen_op_iwmmxt_unpackhb_M0_wRn(rd1); - break; - case 1: - gen_op_iwmmxt_unpackhw_M0_wRn(rd1); - break; - case 2: - gen_op_iwmmxt_unpackhl_M0_wRn(rd1); - break; - case 3: - return 1; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */ - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - rd1 =3D (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - if (insn & (1 << 22)) - gen_op_iwmmxt_sadw_M0_wRn(rd1); - else - gen_op_iwmmxt_sadb_M0_wRn(rd1); - if (!(insn & (1 << 20))) - gen_op_iwmmxt_addl_M0_wRn(wrd); - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - break; - case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */ - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - rd1 =3D (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - if (insn & (1 << 21)) { - if (insn & (1 << 20)) - gen_op_iwmmxt_mulshw_M0_wRn(rd1); - else - gen_op_iwmmxt_mulslw_M0_wRn(rd1); - } else { - if (insn & (1 << 20)) - gen_op_iwmmxt_muluhw_M0_wRn(rd1); - else - gen_op_iwmmxt_mululw_M0_wRn(rd1); - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - break; - case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */ - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - rd1 =3D (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - if (insn & (1 << 21)) - gen_op_iwmmxt_macsw_M0_wRn(rd1); - else - gen_op_iwmmxt_macuw_M0_wRn(rd1); - if (!(insn & (1 << 20))) { - iwmmxt_load_reg(cpu_V1, wrd); - tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1); - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - break; - case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */ - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - rd1 =3D (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - switch ((insn >> 22) & 3) { - case 0: - gen_op_iwmmxt_cmpeqb_M0_wRn(rd1); - break; - case 1: - gen_op_iwmmxt_cmpeqw_M0_wRn(rd1); - break; - case 2: - gen_op_iwmmxt_cmpeql_M0_wRn(rd1); - break; - case 3: - return 1; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */ - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - rd1 =3D (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - if (insn & (1 << 22)) { - if (insn & (1 << 20)) - gen_op_iwmmxt_avgw1_M0_wRn(rd1); - else - gen_op_iwmmxt_avgw0_M0_wRn(rd1); - } else { - if (insn & (1 << 20)) - gen_op_iwmmxt_avgb1_M0_wRn(rd1); - else - gen_op_iwmmxt_avgb0_M0_wRn(rd1); - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */ - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - rd1 =3D (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - tmp =3D iwmmxt_load_creg(ARM_IWMMXT_wCGR0 + ((insn >> 20) & 3)); - tcg_gen_andi_i32(tmp, tmp, 7); - iwmmxt_load_reg(cpu_V1, rd1); - gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp); - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - break; - case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */ - if (((insn >> 6) & 3) =3D=3D 3) - return 1; - rd =3D (insn >> 12) & 0xf; - wrd =3D (insn >> 16) & 0xf; - tmp =3D load_reg(s, rd); - gen_op_iwmmxt_movq_M0_wRn(wrd); - switch ((insn >> 6) & 3) { - case 0: - tmp2 =3D tcg_constant_i32(0xff); - tmp3 =3D tcg_constant_i32((insn & 7) << 3); - break; - case 1: - tmp2 =3D tcg_constant_i32(0xffff); - tmp3 =3D tcg_constant_i32((insn & 3) << 4); - break; - case 2: - tmp2 =3D tcg_constant_i32(0xffffffff); - tmp3 =3D tcg_constant_i32((insn & 1) << 5); - break; - default: - g_assert_not_reached(); - } - gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, tmp, tmp2, tmp3); - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - break; - case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */ - rd =3D (insn >> 12) & 0xf; - wrd =3D (insn >> 16) & 0xf; - if (rd =3D=3D 15 || ((insn >> 22) & 3) =3D=3D 3) - return 1; - gen_op_iwmmxt_movq_M0_wRn(wrd); - tmp =3D tcg_temp_new_i32(); - switch ((insn >> 22) & 3) { - case 0: - tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 7) << 3); - tcg_gen_extrl_i64_i32(tmp, cpu_M0); - if (insn & 8) { - tcg_gen_ext8s_i32(tmp, tmp); - } else { - tcg_gen_andi_i32(tmp, tmp, 0xff); - } - break; - case 1: - tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 3) << 4); - tcg_gen_extrl_i64_i32(tmp, cpu_M0); - if (insn & 8) { - tcg_gen_ext16s_i32(tmp, tmp); - } else { - tcg_gen_andi_i32(tmp, tmp, 0xffff); - } - break; - case 2: - tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 1) << 5); - tcg_gen_extrl_i64_i32(tmp, cpu_M0); - break; - } - store_reg(s, rd, tmp); - break; - case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */ - if ((insn & 0x000ff008) !=3D 0x0003f000 || ((insn >> 22) & 3) =3D= =3D 3) - return 1; - tmp =3D iwmmxt_load_creg(ARM_IWMMXT_wCASF); - switch ((insn >> 22) & 3) { - case 0: - tcg_gen_shri_i32(tmp, tmp, ((insn & 7) << 2) + 0); - break; - case 1: - tcg_gen_shri_i32(tmp, tmp, ((insn & 3) << 3) + 4); - break; - case 2: - tcg_gen_shri_i32(tmp, tmp, ((insn & 1) << 4) + 12); - break; - } - tcg_gen_shli_i32(tmp, tmp, 28); - gen_set_nzcv(tmp); - break; - case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */ - if (((insn >> 6) & 3) =3D=3D 3) - return 1; - rd =3D (insn >> 12) & 0xf; - wrd =3D (insn >> 16) & 0xf; - tmp =3D load_reg(s, rd); - switch ((insn >> 6) & 3) { - case 0: - gen_helper_iwmmxt_bcstb(cpu_M0, tmp); - break; - case 1: - gen_helper_iwmmxt_bcstw(cpu_M0, tmp); - break; - case 2: - gen_helper_iwmmxt_bcstl(cpu_M0, tmp); - break; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - break; - case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */ - if ((insn & 0x000ff00f) !=3D 0x0003f000 || ((insn >> 22) & 3) =3D= =3D 3) - return 1; - tmp =3D iwmmxt_load_creg(ARM_IWMMXT_wCASF); - tmp2 =3D tcg_temp_new_i32(); - tcg_gen_mov_i32(tmp2, tmp); - switch ((insn >> 22) & 3) { - case 0: - for (i =3D 0; i < 7; i ++) { - tcg_gen_shli_i32(tmp2, tmp2, 4); - tcg_gen_and_i32(tmp, tmp, tmp2); - } - break; - case 1: - for (i =3D 0; i < 3; i ++) { - tcg_gen_shli_i32(tmp2, tmp2, 8); - tcg_gen_and_i32(tmp, tmp, tmp2); - } - break; - case 2: - tcg_gen_shli_i32(tmp2, tmp2, 16); - tcg_gen_and_i32(tmp, tmp, tmp2); - break; - } - gen_set_nzcv(tmp); - break; - case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */ - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - switch ((insn >> 22) & 3) { - case 0: - gen_helper_iwmmxt_addcb(cpu_M0, cpu_M0); - break; - case 1: - gen_helper_iwmmxt_addcw(cpu_M0, cpu_M0); - break; - case 2: - gen_helper_iwmmxt_addcl(cpu_M0, cpu_M0); - break; - case 3: - return 1; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - break; - case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */ - if ((insn & 0x000ff00f) !=3D 0x0003f000 || ((insn >> 22) & 3) =3D= =3D 3) - return 1; - tmp =3D iwmmxt_load_creg(ARM_IWMMXT_wCASF); - tmp2 =3D tcg_temp_new_i32(); - tcg_gen_mov_i32(tmp2, tmp); - switch ((insn >> 22) & 3) { - case 0: - for (i =3D 0; i < 7; i ++) { - tcg_gen_shli_i32(tmp2, tmp2, 4); - tcg_gen_or_i32(tmp, tmp, tmp2); - } - break; - case 1: - for (i =3D 0; i < 3; i ++) { - tcg_gen_shli_i32(tmp2, tmp2, 8); - tcg_gen_or_i32(tmp, tmp, tmp2); - } - break; - case 2: - tcg_gen_shli_i32(tmp2, tmp2, 16); - tcg_gen_or_i32(tmp, tmp, tmp2); - break; - } - gen_set_nzcv(tmp); - break; - case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */ - rd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - if ((insn & 0xf) !=3D 0 || ((insn >> 22) & 3) =3D=3D 3) - return 1; - gen_op_iwmmxt_movq_M0_wRn(rd0); - tmp =3D tcg_temp_new_i32(); - switch ((insn >> 22) & 3) { - case 0: - gen_helper_iwmmxt_msbb(tmp, cpu_M0); - break; - case 1: - gen_helper_iwmmxt_msbw(tmp, cpu_M0); - break; - case 2: - gen_helper_iwmmxt_msbl(tmp, cpu_M0); - break; - } - store_reg(s, rd, tmp); - break; - case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */ - case 0x906: case 0xb06: case 0xd06: case 0xf06: - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - rd1 =3D (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - switch ((insn >> 22) & 3) { - case 0: - if (insn & (1 << 21)) - gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1); - else - gen_op_iwmmxt_cmpgtub_M0_wRn(rd1); - break; - case 1: - if (insn & (1 << 21)) - gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1); - else - gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1); - break; - case 2: - if (insn & (1 << 21)) - gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1); - else - gen_op_iwmmxt_cmpgtul_M0_wRn(rd1); - break; - case 3: - return 1; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */ - case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e: - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - switch ((insn >> 22) & 3) { - case 0: - if (insn & (1 << 21)) - gen_op_iwmmxt_unpacklsb_M0(); - else - gen_op_iwmmxt_unpacklub_M0(); - break; - case 1: - if (insn & (1 << 21)) - gen_op_iwmmxt_unpacklsw_M0(); - else - gen_op_iwmmxt_unpackluw_M0(); - break; - case 2: - if (insn & (1 << 21)) - gen_op_iwmmxt_unpacklsl_M0(); - else - gen_op_iwmmxt_unpacklul_M0(); - break; - case 3: - return 1; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */ - case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c: - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - switch ((insn >> 22) & 3) { - case 0: - if (insn & (1 << 21)) - gen_op_iwmmxt_unpackhsb_M0(); - else - gen_op_iwmmxt_unpackhub_M0(); - break; - case 1: - if (insn & (1 << 21)) - gen_op_iwmmxt_unpackhsw_M0(); - else - gen_op_iwmmxt_unpackhuw_M0(); - break; - case 2: - if (insn & (1 << 21)) - gen_op_iwmmxt_unpackhsl_M0(); - else - gen_op_iwmmxt_unpackhul_M0(); - break; - case 3: - return 1; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */ - case 0x214: case 0x614: case 0xa14: case 0xe14: - if (((insn >> 22) & 3) =3D=3D 0) - return 1; - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - tmp =3D tcg_temp_new_i32(); - if (gen_iwmmxt_shift(insn, 0xff, tmp)) { - return 1; - } - switch ((insn >> 22) & 3) { - case 1: - gen_helper_iwmmxt_srlw(cpu_M0, tcg_env, cpu_M0, tmp); - break; - case 2: - gen_helper_iwmmxt_srll(cpu_M0, tcg_env, cpu_M0, tmp); - break; - case 3: - gen_helper_iwmmxt_srlq(cpu_M0, tcg_env, cpu_M0, tmp); - break; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */ - case 0x014: case 0x414: case 0x814: case 0xc14: - if (((insn >> 22) & 3) =3D=3D 0) - return 1; - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - tmp =3D tcg_temp_new_i32(); - if (gen_iwmmxt_shift(insn, 0xff, tmp)) { - return 1; - } - switch ((insn >> 22) & 3) { - case 1: - gen_helper_iwmmxt_sraw(cpu_M0, tcg_env, cpu_M0, tmp); - break; - case 2: - gen_helper_iwmmxt_sral(cpu_M0, tcg_env, cpu_M0, tmp); - break; - case 3: - gen_helper_iwmmxt_sraq(cpu_M0, tcg_env, cpu_M0, tmp); - break; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */ - case 0x114: case 0x514: case 0x914: case 0xd14: - if (((insn >> 22) & 3) =3D=3D 0) - return 1; - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - tmp =3D tcg_temp_new_i32(); - if (gen_iwmmxt_shift(insn, 0xff, tmp)) { - return 1; - } - switch ((insn >> 22) & 3) { - case 1: - gen_helper_iwmmxt_sllw(cpu_M0, tcg_env, cpu_M0, tmp); - break; - case 2: - gen_helper_iwmmxt_slll(cpu_M0, tcg_env, cpu_M0, tmp); - break; - case 3: - gen_helper_iwmmxt_sllq(cpu_M0, tcg_env, cpu_M0, tmp); - break; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */ - case 0x314: case 0x714: case 0xb14: case 0xf14: - if (((insn >> 22) & 3) =3D=3D 0) - return 1; - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - tmp =3D tcg_temp_new_i32(); - switch ((insn >> 22) & 3) { - case 1: - if (gen_iwmmxt_shift(insn, 0xf, tmp)) { - return 1; - } - gen_helper_iwmmxt_rorw(cpu_M0, tcg_env, cpu_M0, tmp); - break; - case 2: - if (gen_iwmmxt_shift(insn, 0x1f, tmp)) { - return 1; - } - gen_helper_iwmmxt_rorl(cpu_M0, tcg_env, cpu_M0, tmp); - break; - case 3: - if (gen_iwmmxt_shift(insn, 0x3f, tmp)) { - return 1; - } - gen_helper_iwmmxt_rorq(cpu_M0, tcg_env, cpu_M0, tmp); - break; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */ - case 0x916: case 0xb16: case 0xd16: case 0xf16: - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - rd1 =3D (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - switch ((insn >> 22) & 3) { - case 0: - if (insn & (1 << 21)) - gen_op_iwmmxt_minsb_M0_wRn(rd1); - else - gen_op_iwmmxt_minub_M0_wRn(rd1); - break; - case 1: - if (insn & (1 << 21)) - gen_op_iwmmxt_minsw_M0_wRn(rd1); - else - gen_op_iwmmxt_minuw_M0_wRn(rd1); - break; - case 2: - if (insn & (1 << 21)) - gen_op_iwmmxt_minsl_M0_wRn(rd1); - else - gen_op_iwmmxt_minul_M0_wRn(rd1); - break; - case 3: - return 1; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - break; - case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */ - case 0x816: case 0xa16: case 0xc16: case 0xe16: - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - rd1 =3D (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - switch ((insn >> 22) & 3) { - case 0: - if (insn & (1 << 21)) - gen_op_iwmmxt_maxsb_M0_wRn(rd1); - else - gen_op_iwmmxt_maxub_M0_wRn(rd1); - break; - case 1: - if (insn & (1 << 21)) - gen_op_iwmmxt_maxsw_M0_wRn(rd1); - else - gen_op_iwmmxt_maxuw_M0_wRn(rd1); - break; - case 2: - if (insn & (1 << 21)) - gen_op_iwmmxt_maxsl_M0_wRn(rd1); - else - gen_op_iwmmxt_maxul_M0_wRn(rd1); - break; - case 3: - return 1; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - break; - case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */ - case 0x402: case 0x502: case 0x602: case 0x702: - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - rd1 =3D (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - iwmmxt_load_reg(cpu_V1, rd1); - gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, - tcg_constant_i32((insn >> 20) & 3)); - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - break; - case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */ - case 0x41a: case 0x51a: case 0x61a: case 0x71a: - case 0x81a: case 0x91a: case 0xa1a: case 0xb1a: - case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a: - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - rd1 =3D (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - switch ((insn >> 20) & 0xf) { - case 0x0: - gen_op_iwmmxt_subnb_M0_wRn(rd1); - break; - case 0x1: - gen_op_iwmmxt_subub_M0_wRn(rd1); - break; - case 0x3: - gen_op_iwmmxt_subsb_M0_wRn(rd1); - break; - case 0x4: - gen_op_iwmmxt_subnw_M0_wRn(rd1); - break; - case 0x5: - gen_op_iwmmxt_subuw_M0_wRn(rd1); - break; - case 0x7: - gen_op_iwmmxt_subsw_M0_wRn(rd1); - break; - case 0x8: - gen_op_iwmmxt_subnl_M0_wRn(rd1); - break; - case 0x9: - gen_op_iwmmxt_subul_M0_wRn(rd1); - break; - case 0xb: - gen_op_iwmmxt_subsl_M0_wRn(rd1); - break; - default: - return 1; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */ - case 0x41e: case 0x51e: case 0x61e: case 0x71e: - case 0x81e: case 0x91e: case 0xa1e: case 0xb1e: - case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e: - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - tmp =3D tcg_constant_i32(((insn >> 16) & 0xf0) | (insn & 0x0f)); - gen_helper_iwmmxt_shufh(cpu_M0, tcg_env, cpu_M0, tmp); - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */ - case 0x418: case 0x518: case 0x618: case 0x718: - case 0x818: case 0x918: case 0xa18: case 0xb18: - case 0xc18: case 0xd18: case 0xe18: case 0xf18: - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - rd1 =3D (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - switch ((insn >> 20) & 0xf) { - case 0x0: - gen_op_iwmmxt_addnb_M0_wRn(rd1); - break; - case 0x1: - gen_op_iwmmxt_addub_M0_wRn(rd1); - break; - case 0x3: - gen_op_iwmmxt_addsb_M0_wRn(rd1); - break; - case 0x4: - gen_op_iwmmxt_addnw_M0_wRn(rd1); - break; - case 0x5: - gen_op_iwmmxt_adduw_M0_wRn(rd1); - break; - case 0x7: - gen_op_iwmmxt_addsw_M0_wRn(rd1); - break; - case 0x8: - gen_op_iwmmxt_addnl_M0_wRn(rd1); - break; - case 0x9: - gen_op_iwmmxt_addul_M0_wRn(rd1); - break; - case 0xb: - gen_op_iwmmxt_addsl_M0_wRn(rd1); - break; - default: - return 1; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */ - case 0x408: case 0x508: case 0x608: case 0x708: - case 0x808: case 0x908: case 0xa08: case 0xb08: - case 0xc08: case 0xd08: case 0xe08: case 0xf08: - if (!(insn & (1 << 20)) || ((insn >> 22) & 3) =3D=3D 0) - return 1; - wrd =3D (insn >> 12) & 0xf; - rd0 =3D (insn >> 16) & 0xf; - rd1 =3D (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - switch ((insn >> 22) & 3) { - case 1: - if (insn & (1 << 21)) - gen_op_iwmmxt_packsw_M0_wRn(rd1); - else - gen_op_iwmmxt_packuw_M0_wRn(rd1); - break; - case 2: - if (insn & (1 << 21)) - gen_op_iwmmxt_packsl_M0_wRn(rd1); - else - gen_op_iwmmxt_packul_M0_wRn(rd1); - break; - case 3: - if (insn & (1 << 21)) - gen_op_iwmmxt_packsq_M0_wRn(rd1); - else - gen_op_iwmmxt_packuq_M0_wRn(rd1); - break; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x201: case 0x203: case 0x205: case 0x207: - case 0x209: case 0x20b: case 0x20d: case 0x20f: - case 0x211: case 0x213: case 0x215: case 0x217: - case 0x219: case 0x21b: case 0x21d: case 0x21f: - wrd =3D (insn >> 5) & 0xf; - rd0 =3D (insn >> 12) & 0xf; - rd1 =3D (insn >> 0) & 0xf; - if (rd0 =3D=3D 0xf || rd1 =3D=3D 0xf) - return 1; - gen_op_iwmmxt_movq_M0_wRn(wrd); - tmp =3D load_reg(s, rd0); - tmp2 =3D load_reg(s, rd1); - switch ((insn >> 16) & 0xf) { - case 0x0: /* TMIA */ - gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2); - break; - case 0x8: /* TMIAPH */ - gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2); - break; - case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy = */ - if (insn & (1 << 16)) - tcg_gen_shri_i32(tmp, tmp, 16); - if (insn & (1 << 17)) - tcg_gen_shri_i32(tmp2, tmp2, 16); - gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2); - break; - default: - return 1; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - break; - default: - return 1; - } - - return 0; -} - -/* Disassemble an XScale DSP instruction. Returns nonzero if an error occ= urred - (ie. an undefined instruction). */ -static int disas_dsp_insn(DisasContext *s, uint32_t insn) -{ - int acc, rd0, rd1, rdhi, rdlo; - TCGv_i32 tmp, tmp2; - - if ((insn & 0x0ff00f10) =3D=3D 0x0e200010) { - /* Multiply with Internal Accumulate Format */ - rd0 =3D (insn >> 12) & 0xf; - rd1 =3D insn & 0xf; - acc =3D (insn >> 5) & 7; - - if (acc !=3D 0) - return 1; - - tmp =3D load_reg(s, rd0); - tmp2 =3D load_reg(s, rd1); - switch ((insn >> 16) & 0xf) { - case 0x0: /* MIA */ - gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2); - break; - case 0x8: /* MIAPH */ - gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2); - break; - case 0xc: /* MIABB */ - case 0xd: /* MIABT */ - case 0xe: /* MIATB */ - case 0xf: /* MIATT */ - if (insn & (1 << 16)) - tcg_gen_shri_i32(tmp, tmp, 16); - if (insn & (1 << 17)) - tcg_gen_shri_i32(tmp2, tmp2, 16); - gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2); - break; - default: - return 1; - } - - gen_op_iwmmxt_movq_wRn_M0(acc); - return 0; - } - - if ((insn & 0x0fe00ff8) =3D=3D 0x0c400000) { - /* Internal Accumulator Access Format */ - rdhi =3D (insn >> 16) & 0xf; - rdlo =3D (insn >> 12) & 0xf; - acc =3D insn & 7; - - if (acc !=3D 0) - return 1; - - if (insn & ARM_CP_RW_BIT) { /* MRA */ - iwmmxt_load_reg(cpu_V0, acc); - tcg_gen_extrl_i64_i32(cpu_R[rdlo], cpu_V0); - tcg_gen_extrh_i64_i32(cpu_R[rdhi], cpu_V0); - tcg_gen_andi_i32(cpu_R[rdhi], cpu_R[rdhi], (1 << (40 - 32)) - = 1); - } else { /* MAR */ - tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]); - iwmmxt_store_reg(cpu_V0, acc); - } - return 0; - } - - return 1; -} - static void gen_goto_ptr(void) { tcg_gen_lookup_and_goto_ptr(); @@ -3048,13 +1789,10 @@ static void do_coproc_insn(DisasContext *s, int cpn= um, int is64, } =20 if ((s->hstr_active && s->current_el =3D=3D 0) || ri->accessfn || - (ri->fgt && s->fgt_active) || - (arm_dc_feature(s, ARM_FEATURE_XSCALE) && cpnum < 14)) { + (ri->fgt && s->fgt_active)) { /* * Emit code to perform further access permissions checks at * runtime; this may result in an exception. - * Note that on XScale all cp0..c13 registers do an access check - * call in order to handle c15_cpar. */ gen_set_condexec(s); gen_update_pc(s, 0); @@ -3192,24 +1930,6 @@ static void do_coproc_insn(DisasContext *s, int cpnu= m, int is64, } } =20 -/* Decode XScale DSP or iWMMXt insn (in the copro space, cp=3D0 or 1) */ -static void disas_xscale_insn(DisasContext *s, uint32_t insn) -{ - int cpnum =3D (insn >> 8) & 0xf; - - if (extract32(s->c15_cpar, cpnum, 1) =3D=3D 0) { - unallocated_encoding(s); - } else if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { - if (disas_iwmmxt_insn(s, insn)) { - unallocated_encoding(s); - } - } else if (arm_dc_feature(s, ARM_FEATURE_XSCALE)) { - if (disas_dsp_insn(s, insn)) { - unallocated_encoding(s); - } - } -} - /* Store a 64-bit value to a register pair. Clobbers val. */ static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 = val) { @@ -3569,14 +2289,7 @@ static bool valid_cp(DisasContext *s, int cp) * only cp14 and cp15 are valid, and other values aren't considered * to be in the coprocessor-instruction space at all. v8M still * permits coprocessors 0..7. - * For XScale, we must not decode the XScale cp0, cp1 space as - * a standard coprocessor insn, because we want to fall through to - * the legacy disas_xscale_insn() decoder after decodetree is done. */ - if (arm_dc_feature(s, ARM_FEATURE_XSCALE) && (cp =3D=3D 0 || cp =3D=3D= 1)) { - return false; - } - if (arm_dc_feature(s, ARM_FEATURE_V8) && !arm_dc_feature(s, ARM_FEATURE_M)) { return cp >=3D 14; @@ -7343,18 +6056,6 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) disas_neon_shared(s, insn)) { return; } - /* fall back to legacy decoder */ - - if ((insn & 0x0e000f00) =3D=3D 0x0c000100) { - if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { - /* iWMMXt register transfer. */ - if (extract32(s->c15_cpar, 1, 1)) { - if (!disas_iwmmxt_insn(s, insn)) { - return; - } - } - } - } goto illegal_op; } if (cond !=3D 0xe) { @@ -7368,16 +6069,7 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) disas_vfp(s, insn)) { return; } - /* fall back to legacy decoder */ - /* TODO: convert xscale/iwmmxt decoder to decodetree ?? */ - if (arm_dc_feature(s, ARM_FEATURE_XSCALE)) { - if (((insn & 0x0c000e00) =3D=3D 0x0c000000) - && ((insn & 0x03000000) !=3D 0x03000000)) { - /* Coprocessor insn, coprocessor 0 or 1 */ - disas_xscale_insn(s, insn); - return; - } - } + /* We didn't match anything in the decoder: UNDEF */ =20 illegal_op: unallocated_encoding(s); @@ -7606,12 +6298,8 @@ static void arm_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) dc->hstr_active =3D EX_TBFLAG_A32(tb_flags, HSTR_ACTIVE); dc->ns =3D EX_TBFLAG_A32(tb_flags, NS); dc->vfp_enabled =3D EX_TBFLAG_A32(tb_flags, VFPEN); - if (arm_feature(env, ARM_FEATURE_XSCALE)) { - dc->c15_cpar =3D EX_TBFLAG_A32(tb_flags, XSCALE_CPAR); - } else { - dc->vec_len =3D EX_TBFLAG_A32(tb_flags, VECLEN); - dc->vec_stride =3D EX_TBFLAG_A32(tb_flags, VECSTRIDE); - } + dc->vec_len =3D EX_TBFLAG_A32(tb_flags, VECLEN); + dc->vec_stride =3D EX_TBFLAG_A32(tb_flags, VECSTRIDE); dc->sme_trap_nonstreaming =3D EX_TBFLAG_A32(tb_flags, SME_TRAP_NONSTREAMING); } @@ -7651,10 +6339,6 @@ static void arm_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) int bound =3D -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; dc->base.max_insns =3D MIN(dc->base.max_insns, bound); } - - cpu_V0 =3D tcg_temp_new_i64(); - cpu_V1 =3D tcg_temp_new_i64(); - cpu_M0 =3D tcg_temp_new_i64(); } =20 static void arm_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu) --=20 2.43.0 From nobody Sat Nov 15 00:45:06 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758046175; cv=none; d=zohomail.com; s=zohoarc; b=Lu3hJoImtOyWl+KhHvCslqNh8ZM5G2Kk2/G1+Poxq3oiHhScOJN0sfSR+UruWq56BWu6pucUJlwISNR5/05Qv53X8dBPl8HgmgUCHGavuAuhfD5rZ+gchAHylY1kPGFfVFsA1fYoKpxCBa/hYuLxvM5arLrqzWm+OJYWVsCZcAc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758046175; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=eVUYoZqnYMK4s3Lt2y/CTWDewwQXx/+g/NEEF8AEsyA=; b=VOj+kBuDcYdZWBoUFB9J7ya3Xqaer8h+LKDaSlHHYTDBfeNgxqwImHhEqshp+yiLHL/CzPupBqSQv9yNLoEyWbI4RgDFRfd+hNQ2sIZGclydf1rPLV3nDsx0X9hk+N+Vws0VLP5am6zS1gfedAsGiRf1/HsJUqHAZdYTK3ZukFc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758046175646327.9456877301843; Tue, 16 Sep 2025 11:09:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uya4y-0003Av-MM; Tue, 16 Sep 2025 14:07:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uya4b-00037i-Vr for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:06:41 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uya4Y-0001bx-1a for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:06:37 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-45f2313dd86so39834135e9.2 for ; Tue, 16 Sep 2025 11:06:33 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20250828140422.3271703-4-peter.maydell@linaro.org --- target/arm/tcg/helper.h | 95 ----- target/arm/tcg/iwmmxt_helper.c | 672 --------------------------------- target/arm/tcg/meson.build | 2 - 3 files changed, 769 deletions(-) delete mode 100644 target/arm/tcg/iwmmxt_helper.c diff --git a/target/arm/tcg/helper.h b/target/arm/tcg/helper.h index 4da32db9021..4636d1bc039 100644 --- a/target/arm/tcg/helper.h +++ b/target/arm/tcg/helper.h @@ -444,101 +444,6 @@ DEF_HELPER_3(neon_acgt_f32, i32, i32, i32, fpst) DEF_HELPER_3(neon_acge_f64, i64, i64, i64, fpst) DEF_HELPER_3(neon_acgt_f64, i64, i64, i64, fpst) =20 -/* iwmmxt_helper.c */ -DEF_HELPER_2(iwmmxt_maddsq, i64, i64, i64) -DEF_HELPER_2(iwmmxt_madduq, i64, i64, i64) -DEF_HELPER_2(iwmmxt_sadb, i64, i64, i64) -DEF_HELPER_2(iwmmxt_sadw, i64, i64, i64) -DEF_HELPER_2(iwmmxt_mulslw, i64, i64, i64) -DEF_HELPER_2(iwmmxt_mulshw, i64, i64, i64) -DEF_HELPER_2(iwmmxt_mululw, i64, i64, i64) -DEF_HELPER_2(iwmmxt_muluhw, i64, i64, i64) -DEF_HELPER_2(iwmmxt_macsw, i64, i64, i64) -DEF_HELPER_2(iwmmxt_macuw, i64, i64, i64) -DEF_HELPER_1(iwmmxt_setpsr_nz, i32, i64) - -#define DEF_IWMMXT_HELPER_SIZE_ENV(name) \ -DEF_HELPER_3(iwmmxt_##name##b, i64, env, i64, i64) \ -DEF_HELPER_3(iwmmxt_##name##w, i64, env, i64, i64) \ -DEF_HELPER_3(iwmmxt_##name##l, i64, env, i64, i64) \ - -DEF_IWMMXT_HELPER_SIZE_ENV(unpackl) -DEF_IWMMXT_HELPER_SIZE_ENV(unpackh) - -DEF_HELPER_2(iwmmxt_unpacklub, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackluw, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpacklul, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackhub, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackhuw, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackhul, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpacklsb, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpacklsw, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpacklsl, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackhsb, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackhsw, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackhsl, i64, env, i64) - -DEF_IWMMXT_HELPER_SIZE_ENV(cmpeq) -DEF_IWMMXT_HELPER_SIZE_ENV(cmpgtu) -DEF_IWMMXT_HELPER_SIZE_ENV(cmpgts) - -DEF_IWMMXT_HELPER_SIZE_ENV(mins) -DEF_IWMMXT_HELPER_SIZE_ENV(minu) -DEF_IWMMXT_HELPER_SIZE_ENV(maxs) -DEF_IWMMXT_HELPER_SIZE_ENV(maxu) - -DEF_IWMMXT_HELPER_SIZE_ENV(subn) -DEF_IWMMXT_HELPER_SIZE_ENV(addn) -DEF_IWMMXT_HELPER_SIZE_ENV(subu) -DEF_IWMMXT_HELPER_SIZE_ENV(addu) -DEF_IWMMXT_HELPER_SIZE_ENV(subs) -DEF_IWMMXT_HELPER_SIZE_ENV(adds) - -DEF_HELPER_3(iwmmxt_avgb0, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_avgb1, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_avgw0, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_avgw1, i64, env, i64, i64) - -DEF_HELPER_3(iwmmxt_align, i64, i64, i64, i32) -DEF_HELPER_4(iwmmxt_insr, i64, i64, i32, i32, i32) - -DEF_HELPER_1(iwmmxt_bcstb, i64, i32) -DEF_HELPER_1(iwmmxt_bcstw, i64, i32) -DEF_HELPER_1(iwmmxt_bcstl, i64, i32) - -DEF_HELPER_1(iwmmxt_addcb, i64, i64) -DEF_HELPER_1(iwmmxt_addcw, i64, i64) -DEF_HELPER_1(iwmmxt_addcl, i64, i64) - -DEF_HELPER_1(iwmmxt_msbb, i32, i64) -DEF_HELPER_1(iwmmxt_msbw, i32, i64) -DEF_HELPER_1(iwmmxt_msbl, i32, i64) - -DEF_HELPER_3(iwmmxt_srlw, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_srll, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_srlq, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_sllw, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_slll, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_sllq, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_sraw, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_sral, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_sraq, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_rorw, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_rorl, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_rorq, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_shufh, i64, env, i64, i32) - -DEF_HELPER_3(iwmmxt_packuw, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_packul, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_packuq, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_packsw, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_packsl, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_packsq, i64, env, i64, i64) - -DEF_HELPER_3(iwmmxt_muladdsl, i64, i64, i32, i32) -DEF_HELPER_3(iwmmxt_muladdsw, i64, i64, i32, i32) -DEF_HELPER_3(iwmmxt_muladdswl, i64, i64, i32, i32) - DEF_HELPER_FLAGS_2(neon_unzip8, TCG_CALL_NO_RWG, void, ptr, ptr) DEF_HELPER_FLAGS_2(neon_unzip16, TCG_CALL_NO_RWG, void, ptr, ptr) DEF_HELPER_FLAGS_2(neon_qunzip8, TCG_CALL_NO_RWG, void, ptr, ptr) diff --git a/target/arm/tcg/iwmmxt_helper.c b/target/arm/tcg/iwmmxt_helper.c deleted file mode 100644 index ba054b6b4db..00000000000 --- a/target/arm/tcg/iwmmxt_helper.c +++ /dev/null @@ -1,672 +0,0 @@ -/* - * iwMMXt micro operations for XScale. - * - * Copyright (c) 2007 OpenedHand, Ltd. - * Written by Andrzej Zaborowski - * Copyright (c) 2008 CodeSourcery - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ - -#include "qemu/osdep.h" - -#include "cpu.h" - -#define HELPER_H "tcg/helper.h" -#include "exec/helper-proto.h.inc" - -/* iwMMXt macros extracted from GNU gdb. */ - -/* Set the SIMD wCASF flags for 8, 16, 32 or 64-bit operations. */ -#define SIMD8_SET(v, n, b) ((v !=3D 0) << ((((b) + 1) * 4) + (n))) -#define SIMD16_SET(v, n, h) ((v !=3D 0) << ((((h) + 1) * 8) + (n))) -#define SIMD32_SET(v, n, w) ((v !=3D 0) << ((((w) + 1) * 16) + (n))) -#define SIMD64_SET(v, n) ((v !=3D 0) << (32 + (n))) -/* Flags to pass as "n" above. */ -#define SIMD_NBIT -1 -#define SIMD_ZBIT -2 -#define SIMD_CBIT -3 -#define SIMD_VBIT -4 -/* Various status bit macros. */ -#define NBIT8(x) ((x) & 0x80) -#define NBIT16(x) ((x) & 0x8000) -#define NBIT32(x) ((x) & 0x80000000) -#define NBIT64(x) ((x) & 0x8000000000000000ULL) -#define ZBIT8(x) (((x) & 0xff) =3D=3D 0) -#define ZBIT16(x) (((x) & 0xffff) =3D=3D 0) -#define ZBIT32(x) (((x) & 0xffffffff) =3D=3D 0) -#define ZBIT64(x) (x =3D=3D 0) -/* Sign extension macros. */ -#define EXTEND8H(a) ((uint16_t) (int8_t) (a)) -#define EXTEND8(a) ((uint32_t) (int8_t) (a)) -#define EXTEND16(a) ((uint32_t) (int16_t) (a)) -#define EXTEND16S(a) ((int32_t) (int16_t) (a)) -#define EXTEND32(a) ((uint64_t) (int32_t) (a)) - -uint64_t HELPER(iwmmxt_maddsq)(uint64_t a, uint64_t b) -{ - a =3D (( - EXTEND16S((a >> 0) & 0xffff) * EXTEND16S((b >> 0) & 0xffff) + - EXTEND16S((a >> 16) & 0xffff) * EXTEND16S((b >> 16) & 0xffff) - ) & 0xffffffff) | ((uint64_t) ( - EXTEND16S((a >> 32) & 0xffff) * EXTEND16S((b >> 32) & 0xffff) + - EXTEND16S((a >> 48) & 0xffff) * EXTEND16S((b >> 48) & 0xffff) - ) << 32); - return a; -} - -uint64_t HELPER(iwmmxt_madduq)(uint64_t a, uint64_t b) -{ - a =3D (( - ((a >> 0) & 0xffff) * ((b >> 0) & 0xffff) + - ((a >> 16) & 0xffff) * ((b >> 16) & 0xffff) - ) & 0xffffffff) | (( - ((a >> 32) & 0xffff) * ((b >> 32) & 0xffff) + - ((a >> 48) & 0xffff) * ((b >> 48) & 0xffff) - ) << 32); - return a; -} - -uint64_t HELPER(iwmmxt_sadb)(uint64_t a, uint64_t b) -{ -#define abs(x) (((x) >=3D 0) ? x : -x) -#define SADB(SHR) abs((int) ((a >> SHR) & 0xff) - (int) ((b >> SHR) & 0xff= )) - return - SADB(0) + SADB(8) + SADB(16) + SADB(24) + - SADB(32) + SADB(40) + SADB(48) + SADB(56); -#undef SADB -} - -uint64_t HELPER(iwmmxt_sadw)(uint64_t a, uint64_t b) -{ -#define SADW(SHR) \ - abs((int) ((a >> SHR) & 0xffff) - (int) ((b >> SHR) & 0xffff)) - return SADW(0) + SADW(16) + SADW(32) + SADW(48); -#undef SADW -} - -uint64_t HELPER(iwmmxt_mulslw)(uint64_t a, uint64_t b) -{ -#define MULS(SHR) ((uint64_t) ((( \ - EXTEND16S((a >> SHR) & 0xffff) * EXTEND16S((b >> SHR) & 0xffff) \ - ) >> 0) & 0xffff) << SHR) - return MULS(0) | MULS(16) | MULS(32) | MULS(48); -#undef MULS -} - -uint64_t HELPER(iwmmxt_mulshw)(uint64_t a, uint64_t b) -{ -#define MULS(SHR) ((uint64_t) ((( \ - EXTEND16S((a >> SHR) & 0xffff) * EXTEND16S((b >> SHR) & 0xffff) \ - ) >> 16) & 0xffff) << SHR) - return MULS(0) | MULS(16) | MULS(32) | MULS(48); -#undef MULS -} - -uint64_t HELPER(iwmmxt_mululw)(uint64_t a, uint64_t b) -{ -#define MULU(SHR) ((uint64_t) ((( \ - ((a >> SHR) & 0xffff) * ((b >> SHR) & 0xffff) \ - ) >> 0) & 0xffff) << SHR) - return MULU(0) | MULU(16) | MULU(32) | MULU(48); -#undef MULU -} - -uint64_t HELPER(iwmmxt_muluhw)(uint64_t a, uint64_t b) -{ -#define MULU(SHR) ((uint64_t) ((( \ - ((a >> SHR) & 0xffff) * ((b >> SHR) & 0xffff) \ - ) >> 16) & 0xffff) << SHR) - return MULU(0) | MULU(16) | MULU(32) | MULU(48); -#undef MULU -} - -uint64_t HELPER(iwmmxt_macsw)(uint64_t a, uint64_t b) -{ -#define MACS(SHR) ( \ - EXTEND16((a >> SHR) & 0xffff) * EXTEND16S((b >> SHR) & 0xffff)) - return (int64_t) (MACS(0) + MACS(16) + MACS(32) + MACS(48)); -#undef MACS -} - -uint64_t HELPER(iwmmxt_macuw)(uint64_t a, uint64_t b) -{ -#define MACU(SHR) ( \ - (uint32_t) ((a >> SHR) & 0xffff) * \ - (uint32_t) ((b >> SHR) & 0xffff)) - return MACU(0) + MACU(16) + MACU(32) + MACU(48); -#undef MACU -} - -#define NZBIT8(x, i) \ - SIMD8_SET(NBIT8((x) & 0xff), SIMD_NBIT, i) | \ - SIMD8_SET(ZBIT8((x) & 0xff), SIMD_ZBIT, i) -#define NZBIT16(x, i) \ - SIMD16_SET(NBIT16((x) & 0xffff), SIMD_NBIT, i) | \ - SIMD16_SET(ZBIT16((x) & 0xffff), SIMD_ZBIT, i) -#define NZBIT32(x, i) \ - SIMD32_SET(NBIT32((x) & 0xffffffff), SIMD_NBIT, i) | \ - SIMD32_SET(ZBIT32((x) & 0xffffffff), SIMD_ZBIT, i) -#define NZBIT64(x) \ - SIMD64_SET(NBIT64(x), SIMD_NBIT) | \ - SIMD64_SET(ZBIT64(x), SIMD_ZBIT) -#define IWMMXT_OP_UNPACK(S, SH0, SH1, SH2, SH3) \ -uint64_t HELPER(glue(iwmmxt_unpack, glue(S, b)))(CPUARMState *env, \ - uint64_t a, uint64_t b) \ -{ \ - a =3D \ - (((a >> SH0) & 0xff) << 0) | (((b >> SH0) & 0xff) << 8) | \ - (((a >> SH1) & 0xff) << 16) | (((b >> SH1) & 0xff) << 24) | \ - (((a >> SH2) & 0xff) << 32) | (((b >> SH2) & 0xff) << 40) | \ - (((a >> SH3) & 0xff) << 48) | (((b >> SH3) & 0xff) << 56); \ - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =3D \ - NZBIT8(a >> 0, 0) | NZBIT8(a >> 8, 1) | \ - NZBIT8(a >> 16, 2) | NZBIT8(a >> 24, 3) | \ - NZBIT8(a >> 32, 4) | NZBIT8(a >> 40, 5) | \ - NZBIT8(a >> 48, 6) | NZBIT8(a >> 56, 7); \ - return a; \ -} \ -uint64_t HELPER(glue(iwmmxt_unpack, glue(S, w)))(CPUARMState *env, \ - uint64_t a, uint64_t b) \ -{ \ - a =3D \ - (((a >> SH0) & 0xffff) << 0) | \ - (((b >> SH0) & 0xffff) << 16) | \ - (((a >> SH2) & 0xffff) << 32) | \ - (((b >> SH2) & 0xffff) << 48); \ - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =3D \ - NZBIT8(a >> 0, 0) | NZBIT8(a >> 16, 1) | \ - NZBIT8(a >> 32, 2) | NZBIT8(a >> 48, 3); \ - return a; \ -} \ -uint64_t HELPER(glue(iwmmxt_unpack, glue(S, l)))(CPUARMState *env, \ - uint64_t a, uint64_t b) \ -{ \ - a =3D \ - (((a >> SH0) & 0xffffffff) << 0) | \ - (((b >> SH0) & 0xffffffff) << 32); \ - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =3D \ - NZBIT32(a >> 0, 0) | NZBIT32(a >> 32, 1); \ - return a; \ -} \ -uint64_t HELPER(glue(iwmmxt_unpack, glue(S, ub)))(CPUARMState *env, \ - uint64_t x) \ -{ \ - x =3D \ - (((x >> SH0) & 0xff) << 0) | \ - (((x >> SH1) & 0xff) << 16) | \ - (((x >> SH2) & 0xff) << 32) | \ - (((x >> SH3) & 0xff) << 48); \ - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =3D \ - NZBIT16(x >> 0, 0) | NZBIT16(x >> 16, 1) | \ - NZBIT16(x >> 32, 2) | NZBIT16(x >> 48, 3); \ - return x; \ -} \ -uint64_t HELPER(glue(iwmmxt_unpack, glue(S, uw)))(CPUARMState *env, \ - uint64_t x) \ -{ \ - x =3D \ - (((x >> SH0) & 0xffff) << 0) | \ - (((x >> SH2) & 0xffff) << 32); \ - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =3D \ - NZBIT32(x >> 0, 0) | NZBIT32(x >> 32, 1); \ - return x; \ -} \ -uint64_t HELPER(glue(iwmmxt_unpack, glue(S, ul)))(CPUARMState *env, \ - uint64_t x) \ -{ \ - x =3D (((x >> SH0) & 0xffffffff) << 0); \ - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =3D NZBIT64(x >> 0); \ - return x; \ -} \ -uint64_t HELPER(glue(iwmmxt_unpack, glue(S, sb)))(CPUARMState *env, \ - uint64_t x) \ -{ \ - x =3D \ - ((uint64_t) EXTEND8H((x >> SH0) & 0xff) << 0) | \ - ((uint64_t) EXTEND8H((x >> SH1) & 0xff) << 16) | \ - ((uint64_t) EXTEND8H((x >> SH2) & 0xff) << 32) | \ - ((uint64_t) EXTEND8H((x >> SH3) & 0xff) << 48); \ - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =3D \ - NZBIT16(x >> 0, 0) | NZBIT16(x >> 16, 1) | \ - NZBIT16(x >> 32, 2) | NZBIT16(x >> 48, 3); \ - return x; \ -} \ -uint64_t HELPER(glue(iwmmxt_unpack, glue(S, sw)))(CPUARMState *env, \ - uint64_t x) \ -{ \ - x =3D \ - ((uint64_t) EXTEND16((x >> SH0) & 0xffff) << 0) | \ - ((uint64_t) EXTEND16((x >> SH2) & 0xffff) << 32); \ - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =3D \ - NZBIT32(x >> 0, 0) | NZBIT32(x >> 32, 1); \ - return x; \ -} \ -uint64_t HELPER(glue(iwmmxt_unpack, glue(S, sl)))(CPUARMState *env, \ - uint64_t x) \ -{ \ - x =3D EXTEND32((x >> SH0) & 0xffffffff); \ - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =3D NZBIT64(x >> 0); \ - return x; \ -} -IWMMXT_OP_UNPACK(l, 0, 8, 16, 24) -IWMMXT_OP_UNPACK(h, 32, 40, 48, 56) - -#define IWMMXT_OP_CMP(SUFF, Tb, Tw, Tl, O) \ -uint64_t HELPER(glue(iwmmxt_, glue(SUFF, b)))(CPUARMState *env, \ - uint64_t a, uint64_t b) \ -{ \ - a =3D \ - CMP(0, Tb, O, 0xff) | CMP(8, Tb, O, 0xff) | \ - CMP(16, Tb, O, 0xff) | CMP(24, Tb, O, 0xff) | \ - CMP(32, Tb, O, 0xff) | CMP(40, Tb, O, 0xff) | \ - CMP(48, Tb, O, 0xff) | CMP(56, Tb, O, 0xff); \ - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =3D \ - NZBIT8(a >> 0, 0) | NZBIT8(a >> 8, 1) | \ - NZBIT8(a >> 16, 2) | NZBIT8(a >> 24, 3) | \ - NZBIT8(a >> 32, 4) | NZBIT8(a >> 40, 5) | \ - NZBIT8(a >> 48, 6) | NZBIT8(a >> 56, 7); \ - return a; \ -} \ -uint64_t HELPER(glue(iwmmxt_, glue(SUFF, w)))(CPUARMState *env, \ - uint64_t a, uint64_t b) \ -{ \ - a =3D CMP(0, Tw, O, 0xffff) | CMP(16, Tw, O, 0xffff) | \ - CMP(32, Tw, O, 0xffff) | CMP(48, Tw, O, 0xffff); \ - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =3D \ - NZBIT16(a >> 0, 0) | NZBIT16(a >> 16, 1) | \ - NZBIT16(a >> 32, 2) | NZBIT16(a >> 48, 3); \ - return a; \ -} \ -uint64_t HELPER(glue(iwmmxt_, glue(SUFF, l)))(CPUARMState *env, \ - uint64_t a, uint64_t b) \ -{ \ - a =3D CMP(0, Tl, O, 0xffffffff) | \ - CMP(32, Tl, O, 0xffffffff); \ - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =3D \ - NZBIT32(a >> 0, 0) | NZBIT32(a >> 32, 1); \ - return a; \ -} -#define CMP(SHR, TYPE, OPER, MASK) ((((TYPE) ((a >> SHR) & MASK) OPER \ - (TYPE) ((b >> SHR) & MASK)) ? (uint64_t) MASK : 0) << SHR) -IWMMXT_OP_CMP(cmpeq, uint8_t, uint16_t, uint32_t, =3D=3D) -IWMMXT_OP_CMP(cmpgts, int8_t, int16_t, int32_t, >) -IWMMXT_OP_CMP(cmpgtu, uint8_t, uint16_t, uint32_t, >) -#undef CMP -#define CMP(SHR, TYPE, OPER, MASK) ((((TYPE) ((a >> SHR) & MASK) OPER \ - (TYPE) ((b >> SHR) & MASK)) ? a : b) & ((uint64_t) MASK << SHR= )) -IWMMXT_OP_CMP(mins, int8_t, int16_t, int32_t, <) -IWMMXT_OP_CMP(minu, uint8_t, uint16_t, uint32_t, <) -IWMMXT_OP_CMP(maxs, int8_t, int16_t, int32_t, >) -IWMMXT_OP_CMP(maxu, uint8_t, uint16_t, uint32_t, >) -#undef CMP -#define CMP(SHR, TYPE, OPER, MASK) ((uint64_t) (((TYPE) ((a >> SHR) & MASK= ) \ - OPER (TYPE) ((b >> SHR) & MASK)) & MASK) << SHR) -IWMMXT_OP_CMP(subn, uint8_t, uint16_t, uint32_t, -) -IWMMXT_OP_CMP(addn, uint8_t, uint16_t, uint32_t, +) -#undef CMP -/* TODO Signed- and Unsigned-Saturation */ -#define CMP(SHR, TYPE, OPER, MASK) ((uint64_t) (((TYPE) ((a >> SHR) & MASK= ) \ - OPER (TYPE) ((b >> SHR) & MASK)) & MASK) << SHR) -IWMMXT_OP_CMP(subu, uint8_t, uint16_t, uint32_t, -) -IWMMXT_OP_CMP(addu, uint8_t, uint16_t, uint32_t, +) -IWMMXT_OP_CMP(subs, int8_t, int16_t, int32_t, -) -IWMMXT_OP_CMP(adds, int8_t, int16_t, int32_t, +) -#undef CMP -#undef IWMMXT_OP_CMP - -#define AVGB(SHR) ((( \ - ((a >> SHR) & 0xff) + ((b >> SHR) & 0xff) + round) >> 1) << SHR) -#define IWMMXT_OP_AVGB(r) \ -uint64_t HELPER(iwmmxt_avgb##r)(CPUARMState *env, uint64_t a, uint64_t b) = \ -{ \ - const int round =3D r; = \ - a =3D AVGB(0) | AVGB(8) | AVGB(16) | AVGB(24) | = \ - AVGB(32) | AVGB(40) | AVGB(48) | AVGB(56); \ - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =3D = \ - SIMD8_SET(ZBIT8((a >> 0) & 0xff), SIMD_ZBIT, 0) | \ - SIMD8_SET(ZBIT8((a >> 8) & 0xff), SIMD_ZBIT, 1) | \ - SIMD8_SET(ZBIT8((a >> 16) & 0xff), SIMD_ZBIT, 2) | \ - SIMD8_SET(ZBIT8((a >> 24) & 0xff), SIMD_ZBIT, 3) | \ - SIMD8_SET(ZBIT8((a >> 32) & 0xff), SIMD_ZBIT, 4) | \ - SIMD8_SET(ZBIT8((a >> 40) & 0xff), SIMD_ZBIT, 5) | \ - SIMD8_SET(ZBIT8((a >> 48) & 0xff), SIMD_ZBIT, 6) | \ - SIMD8_SET(ZBIT8((a >> 56) & 0xff), SIMD_ZBIT, 7); \ - return a; \ -} -IWMMXT_OP_AVGB(0) -IWMMXT_OP_AVGB(1) -#undef IWMMXT_OP_AVGB -#undef AVGB - -#define AVGW(SHR) ((( \ - ((a >> SHR) & 0xffff) + ((b >> SHR) & 0xffff) + round) >> 1) << SH= R) -#define IWMMXT_OP_AVGW(r) \ -uint64_t HELPER(iwmmxt_avgw##r)(CPUARMState *env, uint64_t a, uint64_t b) = \ -{ \ - const int round =3D r; \ - a =3D AVGW(0) | AVGW(16) | AVGW(32) | AVGW(48); \ - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =3D \ - SIMD16_SET(ZBIT16((a >> 0) & 0xffff), SIMD_ZBIT, 0) | \ - SIMD16_SET(ZBIT16((a >> 16) & 0xffff), SIMD_ZBIT, 1) | \ - SIMD16_SET(ZBIT16((a >> 32) & 0xffff), SIMD_ZBIT, 2) | \ - SIMD16_SET(ZBIT16((a >> 48) & 0xffff), SIMD_ZBIT, 3); \ - return a; \ -} -IWMMXT_OP_AVGW(0) -IWMMXT_OP_AVGW(1) -#undef IWMMXT_OP_AVGW -#undef AVGW - -uint64_t HELPER(iwmmxt_align)(uint64_t a, uint64_t b, uint32_t n) -{ - a >>=3D n << 3; - a |=3D b << (64 - (n << 3)); - return a; -} - -uint64_t HELPER(iwmmxt_insr)(uint64_t x, uint32_t a, uint32_t b, uint32_t = n) -{ - x &=3D ~((uint64_t) b << n); - x |=3D (uint64_t) (a & b) << n; - return x; -} - -uint32_t HELPER(iwmmxt_setpsr_nz)(uint64_t x) -{ - return SIMD64_SET((x =3D=3D 0), SIMD_ZBIT) | - SIMD64_SET((x & (1ULL << 63)), SIMD_NBIT); -} - -uint64_t HELPER(iwmmxt_bcstb)(uint32_t arg) -{ - arg &=3D 0xff; - return - ((uint64_t) arg << 0 ) | ((uint64_t) arg << 8 ) | - ((uint64_t) arg << 16) | ((uint64_t) arg << 24) | - ((uint64_t) arg << 32) | ((uint64_t) arg << 40) | - ((uint64_t) arg << 48) | ((uint64_t) arg << 56); -} - -uint64_t HELPER(iwmmxt_bcstw)(uint32_t arg) -{ - arg &=3D 0xffff; - return - ((uint64_t) arg << 0 ) | ((uint64_t) arg << 16) | - ((uint64_t) arg << 32) | ((uint64_t) arg << 48); -} - -uint64_t HELPER(iwmmxt_bcstl)(uint32_t arg) -{ - return arg | ((uint64_t) arg << 32); -} - -uint64_t HELPER(iwmmxt_addcb)(uint64_t x) -{ - return - ((x >> 0) & 0xff) + ((x >> 8) & 0xff) + - ((x >> 16) & 0xff) + ((x >> 24) & 0xff) + - ((x >> 32) & 0xff) + ((x >> 40) & 0xff) + - ((x >> 48) & 0xff) + ((x >> 56) & 0xff); -} - -uint64_t HELPER(iwmmxt_addcw)(uint64_t x) -{ - return - ((x >> 0) & 0xffff) + ((x >> 16) & 0xffff) + - ((x >> 32) & 0xffff) + ((x >> 48) & 0xffff); -} - -uint64_t HELPER(iwmmxt_addcl)(uint64_t x) -{ - return (x & 0xffffffff) + (x >> 32); -} - -uint32_t HELPER(iwmmxt_msbb)(uint64_t x) -{ - return - ((x >> 7) & 0x01) | ((x >> 14) & 0x02) | - ((x >> 21) & 0x04) | ((x >> 28) & 0x08) | - ((x >> 35) & 0x10) | ((x >> 42) & 0x20) | - ((x >> 49) & 0x40) | ((x >> 56) & 0x80); -} - -uint32_t HELPER(iwmmxt_msbw)(uint64_t x) -{ - return - ((x >> 15) & 0x01) | ((x >> 30) & 0x02) | - ((x >> 45) & 0x04) | ((x >> 52) & 0x08); -} - -uint32_t HELPER(iwmmxt_msbl)(uint64_t x) -{ - return ((x >> 31) & 0x01) | ((x >> 62) & 0x02); -} - -/* FIXME: Split wCASF setting into a separate op to avoid env use. */ -uint64_t HELPER(iwmmxt_srlw)(CPUARMState *env, uint64_t x, uint32_t n) -{ - x =3D (((x & (0xffffll << 0)) >> n) & (0xffffll << 0)) | - (((x & (0xffffll << 16)) >> n) & (0xffffll << 16)) | - (((x & (0xffffll << 32)) >> n) & (0xffffll << 32)) | - (((x & (0xffffll << 48)) >> n) & (0xffffll << 48)); - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =3D - NZBIT16(x >> 0, 0) | NZBIT16(x >> 16, 1) | - NZBIT16(x >> 32, 2) | NZBIT16(x >> 48, 3); - return x; -} - -uint64_t HELPER(iwmmxt_srll)(CPUARMState *env, uint64_t x, uint32_t n) -{ - x =3D ((x & (0xffffffffll << 0)) >> n) | - ((x >> n) & (0xffffffffll << 32)); - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =3D - NZBIT32(x >> 0, 0) | NZBIT32(x >> 32, 1); - return x; -} - -uint64_t HELPER(iwmmxt_srlq)(CPUARMState *env, uint64_t x, uint32_t n) -{ - x >>=3D n; - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =3D NZBIT64(x); - return x; -} - -uint64_t HELPER(iwmmxt_sllw)(CPUARMState *env, uint64_t x, uint32_t n) -{ - x =3D (((x & (0xffffll << 0)) << n) & (0xffffll << 0)) | - (((x & (0xffffll << 16)) << n) & (0xffffll << 16)) | - (((x & (0xffffll << 32)) << n) & (0xffffll << 32)) | - (((x & (0xffffll << 48)) << n) & (0xffffll << 48)); - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =3D - NZBIT16(x >> 0, 0) | NZBIT16(x >> 16, 1) | - NZBIT16(x >> 32, 2) | NZBIT16(x >> 48, 3); - return x; -} - -uint64_t HELPER(iwmmxt_slll)(CPUARMState *env, uint64_t x, uint32_t n) -{ - x =3D ((x << n) & (0xffffffffll << 0)) | - ((x & (0xffffffffll << 32)) << n); - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =3D - NZBIT32(x >> 0, 0) | NZBIT32(x >> 32, 1); - return x; -} - -uint64_t HELPER(iwmmxt_sllq)(CPUARMState *env, uint64_t x, uint32_t n) -{ - x <<=3D n; - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =3D NZBIT64(x); - return x; -} - -uint64_t HELPER(iwmmxt_sraw)(CPUARMState *env, uint64_t x, uint32_t n) -{ - x =3D ((uint64_t) ((EXTEND16(x >> 0) >> n) & 0xffff) << 0) | - ((uint64_t) ((EXTEND16(x >> 16) >> n) & 0xffff) << 16) | - ((uint64_t) ((EXTEND16(x >> 32) >> n) & 0xffff) << 32) | - ((uint64_t) ((EXTEND16(x >> 48) >> n) & 0xffff) << 48); - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =3D - NZBIT16(x >> 0, 0) | NZBIT16(x >> 16, 1) | - NZBIT16(x >> 32, 2) | NZBIT16(x >> 48, 3); - return x; -} - -uint64_t HELPER(iwmmxt_sral)(CPUARMState *env, uint64_t x, uint32_t n) -{ - x =3D (((EXTEND32(x >> 0) >> n) & 0xffffffff) << 0) | - (((EXTEND32(x >> 32) >> n) & 0xffffffff) << 32); - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =3D - NZBIT32(x >> 0, 0) | NZBIT32(x >> 32, 1); - return x; -} - -uint64_t HELPER(iwmmxt_sraq)(CPUARMState *env, uint64_t x, uint32_t n) -{ - x =3D (int64_t) x >> n; - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =3D NZBIT64(x); - return x; -} - -uint64_t HELPER(iwmmxt_rorw)(CPUARMState *env, uint64_t x, uint32_t n) -{ - x =3D ((((x & (0xffffll << 0)) >> n) | - ((x & (0xffffll << 0)) << (16 - n))) & (0xffffll << 0)) | - ((((x & (0xffffll << 16)) >> n) | - ((x & (0xffffll << 16)) << (16 - n))) & (0xffffll << 16)) | - ((((x & (0xffffll << 32)) >> n) | - ((x & (0xffffll << 32)) << (16 - n))) & (0xffffll << 32)) | - ((((x & (0xffffll << 48)) >> n) | - ((x & (0xffffll << 48)) << (16 - n))) & (0xffffll << 48)); - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =3D - NZBIT16(x >> 0, 0) | NZBIT16(x >> 16, 1) | - NZBIT16(x >> 32, 2) | NZBIT16(x >> 48, 3); - return x; -} - -uint64_t HELPER(iwmmxt_rorl)(CPUARMState *env, uint64_t x, uint32_t n) -{ - x =3D ((x & (0xffffffffll << 0)) >> n) | - ((x >> n) & (0xffffffffll << 32)) | - ((x << (32 - n)) & (0xffffffffll << 0)) | - ((x & (0xffffffffll << 32)) << (32 - n)); - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =3D - NZBIT32(x >> 0, 0) | NZBIT32(x >> 32, 1); - return x; -} - -uint64_t HELPER(iwmmxt_rorq)(CPUARMState *env, uint64_t x, uint32_t n) -{ - x =3D ror64(x, n); - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =3D NZBIT64(x); - return x; -} - -uint64_t HELPER(iwmmxt_shufh)(CPUARMState *env, uint64_t x, uint32_t n) -{ - x =3D (((x >> ((n << 4) & 0x30)) & 0xffff) << 0) | - (((x >> ((n << 2) & 0x30)) & 0xffff) << 16) | - (((x >> ((n << 0) & 0x30)) & 0xffff) << 32) | - (((x >> ((n >> 2) & 0x30)) & 0xffff) << 48); - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =3D - NZBIT16(x >> 0, 0) | NZBIT16(x >> 16, 1) | - NZBIT16(x >> 32, 2) | NZBIT16(x >> 48, 3); - return x; -} - -/* TODO: Unsigned-Saturation */ -uint64_t HELPER(iwmmxt_packuw)(CPUARMState *env, uint64_t a, uint64_t b) -{ - a =3D (((a >> 0) & 0xff) << 0) | (((a >> 16) & 0xff) << 8) | - (((a >> 32) & 0xff) << 16) | (((a >> 48) & 0xff) << 24) | - (((b >> 0) & 0xff) << 32) | (((b >> 16) & 0xff) << 40) | - (((b >> 32) & 0xff) << 48) | (((b >> 48) & 0xff) << 56); - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =3D - NZBIT8(a >> 0, 0) | NZBIT8(a >> 8, 1) | - NZBIT8(a >> 16, 2) | NZBIT8(a >> 24, 3) | - NZBIT8(a >> 32, 4) | NZBIT8(a >> 40, 5) | - NZBIT8(a >> 48, 6) | NZBIT8(a >> 56, 7); - return a; -} - -uint64_t HELPER(iwmmxt_packul)(CPUARMState *env, uint64_t a, uint64_t b) -{ - a =3D (((a >> 0) & 0xffff) << 0) | (((a >> 32) & 0xffff) << 16) | - (((b >> 0) & 0xffff) << 32) | (((b >> 32) & 0xffff) << 48); - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =3D - NZBIT16(a >> 0, 0) | NZBIT16(a >> 16, 1) | - NZBIT16(a >> 32, 2) | NZBIT16(a >> 48, 3); - return a; -} - -uint64_t HELPER(iwmmxt_packuq)(CPUARMState *env, uint64_t a, uint64_t b) -{ - a =3D (a & 0xffffffff) | ((b & 0xffffffff) << 32); - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =3D - NZBIT32(a >> 0, 0) | NZBIT32(a >> 32, 1); - return a; -} - -/* TODO: Signed-Saturation */ -uint64_t HELPER(iwmmxt_packsw)(CPUARMState *env, uint64_t a, uint64_t b) -{ - a =3D (((a >> 0) & 0xff) << 0) | (((a >> 16) & 0xff) << 8) | - (((a >> 32) & 0xff) << 16) | (((a >> 48) & 0xff) << 24) | - (((b >> 0) & 0xff) << 32) | (((b >> 16) & 0xff) << 40) | - (((b >> 32) & 0xff) << 48) | (((b >> 48) & 0xff) << 56); - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =3D - NZBIT8(a >> 0, 0) | NZBIT8(a >> 8, 1) | - NZBIT8(a >> 16, 2) | NZBIT8(a >> 24, 3) | - NZBIT8(a >> 32, 4) | NZBIT8(a >> 40, 5) | - NZBIT8(a >> 48, 6) | NZBIT8(a >> 56, 7); - return a; -} - -uint64_t HELPER(iwmmxt_packsl)(CPUARMState *env, uint64_t a, uint64_t b) -{ - a =3D (((a >> 0) & 0xffff) << 0) | (((a >> 32) & 0xffff) << 16) | - (((b >> 0) & 0xffff) << 32) | (((b >> 32) & 0xffff) << 48); - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =3D - NZBIT16(a >> 0, 0) | NZBIT16(a >> 16, 1) | - NZBIT16(a >> 32, 2) | NZBIT16(a >> 48, 3); - return a; -} - -uint64_t HELPER(iwmmxt_packsq)(CPUARMState *env, uint64_t a, uint64_t b) -{ - a =3D (a & 0xffffffff) | ((b & 0xffffffff) << 32); - env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =3D - NZBIT32(a >> 0, 0) | NZBIT32(a >> 32, 1); - return a; -} - -uint64_t HELPER(iwmmxt_muladdsl)(uint64_t c, uint32_t a, uint32_t b) -{ - return c + ((int32_t) EXTEND32(a) * (int32_t) EXTEND32(b)); -} - -uint64_t HELPER(iwmmxt_muladdsw)(uint64_t c, uint32_t a, uint32_t b) -{ - c +=3D EXTEND32(EXTEND16S((a >> 0) & 0xffff) * - EXTEND16S((b >> 0) & 0xffff)); - c +=3D EXTEND32(EXTEND16S((a >> 16) & 0xffff) * - EXTEND16S((b >> 16) & 0xffff)); - return c; -} - -uint64_t HELPER(iwmmxt_muladdswl)(uint64_t c, uint32_t a, uint32_t b) -{ - return c + (EXTEND32(EXTEND16S(a & 0xffff) * - EXTEND16S(b & 0xffff))); -} diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 895facdc30b..1b115656c46 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -66,7 +66,6 @@ arm_common_ss.add(files( arm_common_system_ss.add(files( 'cpregs-at.c', 'hflags.c', - 'iwmmxt_helper.c', 'neon_helper.c', 'tlb_helper.c', 'tlb-insns.c', @@ -74,7 +73,6 @@ arm_common_system_ss.add(files( )) arm_user_ss.add(files( 'hflags.c', - 'iwmmxt_helper.c', 'neon_helper.c', 'tlb_helper.c', 'vfp_helper.c', --=20 2.43.0 From nobody Sat Nov 15 00:45:06 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3e760775880sm23033286f8f.2.2025.09.16.11.06.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 11:06:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758045993; x=1758650793; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=aFlwhTu+WV4Da4c9Ts1Xd5fh6JlTMno61ShmjJipyoQ=; b=h+OYDVposlNtv2cp2hb+qGbqGv+G05AJ1e5MZKIjbC5TBwKuJPjeDfuRuhh8GJRJo6 eLWNz6CXoSii7DKCLwbB/lUY9llQOZ94K2u4c/i25Yen7VkcJDuXG1b++3NLf8vUCtTC 0lsUZ8ilyLddqTOnM74HkWGjxiO9SXlmSqMzDsOqbqCdHaGkzKPRhc6a/S1qNNL804m2 OuFvXboqq6VQNIU43X+iHcwX264H3PbOwry7P/8Ce/IT5Qe5jNof60wTEb2I2kpLwPxP qEgrkTiaJgJZCo42PBcx8HaLjhLpWRPevvnvtrlUdJqlLcE5NLl5niQK+ilHvvq3Zjkr Em4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758045993; x=1758650793; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aFlwhTu+WV4Da4c9Ts1Xd5fh6JlTMno61ShmjJipyoQ=; b=RdM9LLrstGEU1bRStR6Nu6fT1jGsNdAuvgbNLvwAEdCyOJDJ9ZXxWnLKKHjx4seMTJ mM8BlkOEyyuMc/2/ONzir7A7BhXOfjALQsobIYwcSatVgMmC6y1bnCleQTS4epQHraHy whjA/zOHedJl+SESClfUqiRBZWUcMbNM/+VQFhwdcfpOr/79dYzxXoSkBGU+WIPquyKP Mc14CKMhYh+TjtAlg+64o9MgbS+nCvhZoYNt4musylkHhVugcx/ZqCmRiKqWtDWogWa1 Lm7Ge8fLOF509p7iUz62BO8robpJZrAs0kjx99TsP7WRICyI0xBx9VNVSip5N/mhVg27 9aFw== X-Gm-Message-State: AOJu0YxHzJpbjoiezHMSc+JSFLop4/Y8C6zeK0n++AdS7C4LGo3kwwIR qX4mRpq1Svzx4hvLJg6W/RBx25XVlGs47gakIGfR5CliU3sPbGm5GaGJGo1rfdrF8WylhRyw5aJ 0tdQj X-Gm-Gg: ASbGncueXiPmD7PSAhQFwMLqYKbtYSfevCXjTi/mJkJE9kKAUfjHykCjxOAKa5UOAHx 3AYvptmjMtUPutl28TVGN2rdyjBzh/b7G7dt+GLgZKsULlt6a3iX7ybio/XkBKZoLbEbCl+5yTa 5zQZK+2+t82v3/SonI8GlEy4tjOQ8VWsSLkpvkAmqpyOBaWyXVbJiOQ5ppWC2HfNx2xtCzunTBr cIHgnX8jB7ZiPK3opinPJD1SeFlnGOhlAnOekA9RRcVJlpbqtsoMIgRQKFZuphbvJsFanoPb+ug VBgkvgOfPPk7R0OCVQYbeGGgDEodnmflBhMunW7fV6BZLltRMo3uZ9BHFMOHhujUjCdbEqGtjbK BR5VI5RViem5AfPAxR9iZrcZfCUx4Xi4Pgmp0ouM= X-Google-Smtp-Source: AGHT+IHOWsltYzx1lUTIYdfLU50A6gHqAmdVVR6zCWJ9DYXtd7JfST6SZsn9WF5xE0fyYp7l4bG9yA== X-Received: by 2002:a05:600c:19c9:b0:45d:d50d:c0db with SMTP id 5b1f17b1804b1-45f211dac1emr152370385e9.15.1758045993116; Tue, 16 Sep 2025 11:06:33 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/36] target/arm: Drop ARM_FEATURE_XSCALE handling Date: Tue, 16 Sep 2025 19:05:52 +0100 Message-ID: <20250916180611.1481266-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916180611.1481266-1-peter.maydell@linaro.org> References: <20250916180611.1481266-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758046416779116600 We have now removed all the CPU types which had the Intel XScale extensions indicated via ARM_FEATURE_XSCALE, so this feature bit is never set. Remove all the code that can only be reached when using this flag. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20250828140422.3271703-5-peter.maydell@linaro.org --- target/arm/cpu.h | 3 --- target/arm/cpu.c | 13 --------- target/arm/helper.c | 54 -------------------------------------- target/arm/ptw.c | 7 +++-- target/arm/tcg/op_helper.c | 6 ----- 5 files changed, 3 insertions(+), 80 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f56fa6df8dd..92fcb96671e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -341,7 +341,6 @@ typedef struct CPUArchState { uint64_t vsctlr; /* Virtualization System control register. */ uint64_t cpacr_el1; /* Architectural feature access control regist= er */ uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ - uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ uint64_t sder; /* Secure debug enable register. */ uint32_t nsacr; /* Non-secure access control register. */ union { /* MMU translation table base 0. */ @@ -513,7 +512,6 @@ typedef struct CPUArchState { uint64_t cntvoff_el2; /* Counter Virtual Offset register */ uint64_t cntpoff_el2; /* Counter Physical Offset register */ ARMGenericTimer c14_timer[NUM_GTIMERS]; - uint32_t c15_cpar; /* XScale Coprocessor Access Register */ uint32_t c15_ticonfig; /* TI925T configuration byte. */ uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ @@ -2444,7 +2442,6 @@ QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= =3D R_V7M_CSSELR_INDEX_MASK); */ enum arm_features { ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ - ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ ARM_FEATURE_V6, ARM_FEATURE_V6K, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d0f6fcdfcea..9781055bdc1 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -349,11 +349,6 @@ static void arm_cpu_reset_hold(Object *obj, ResetType = type) env->uncached_cpsr =3D ARM_CPU_MODE_USR; /* For user mode we must enable access to coprocessors */ env->vfp.xregs[ARM_VFP_FPEXC] =3D 1 << 30; - if (arm_feature(env, ARM_FEATURE_IWMMXT)) { - env->cp15.c15_cpar =3D 3; - } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { - env->cp15.c15_cpar =3D 1; - } #else =20 /* @@ -2259,14 +2254,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) } =20 =20 - /* - * We rely on no XScale CPU having VFP so we can use the same bits in = the - * TB flags field for VECSTRIDE and XSCALE_CPAR. - */ - assert(arm_feature(env, ARM_FEATURE_AARCH64) || - !cpu_isar_feature(aa32_vfp_simd, cpu) || - !arm_feature(env, ARM_FEATURE_XSCALE)); - #ifndef CONFIG_USER_ONLY { int pagebits; diff --git a/target/arm/helper.c b/target/arm/helper.c index b641229ba0c..fa8dfac2998 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2923,39 +2923,6 @@ static const ARMCPRegInfo omap_cp_reginfo[] =3D { .type =3D ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue =3D 0 }, }; =20 -static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - env->cp15.c15_cpar =3D value & 0x3fff; -} - -static const ARMCPRegInfo xscale_cp_reginfo[] =3D { - { .name =3D "XSCALE_CPAR", - .cp =3D 15, .crn =3D 15, .crm =3D 1, .opc1 =3D 0, .opc2 =3D 0, .acce= ss =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = =3D 0, - .writefn =3D xscale_cpar_write, }, - { .name =3D "XSCALE_AUXCR", - .cp =3D 15, .crn =3D 1, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 1, .acces= s =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.c1_xscaleauxcr), - .resetvalue =3D 0, }, - /* - * XScale specific cache-lockdown: since we have no cache we NOP these - * and hope the guest does not really rely on cache behaviour. - */ - { .name =3D "XSCALE_LOCK_ICACHE_LINE", - .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 1, .opc2 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, - { .name =3D "XSCALE_UNLOCK_ICACHE", - .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 1, .opc2 =3D 1, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, - { .name =3D "XSCALE_DCACHE_LOCK", - .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 2, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_NOP }, - { .name =3D "XSCALE_UNLOCK_DCACHE", - .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 2, .opc2 =3D 1, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, -}; - static const ARMCPRegInfo dummy_c15_cp_reginfo[] =3D { /* * RAZ/WI the whole crn=3D15 space, when we don't have a more specific @@ -3346,16 +3313,6 @@ static void sctlr_write(CPUARMState *env, const ARMC= PRegInfo *ri, =20 /* This may enable/disable the MMU, so do a TLB flush. */ tlb_flush(CPU(cpu)); - - if (tcg_enabled() && ri->type & ARM_CP_SUPPRESS_TB_END) { - /* - * Normally we would always end the TB on an SCTLR write; see the - * comment in ARMCPRegInfo sctlr initialization below for why Xsca= le - * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebu= ild - * of hflags from the translator, so do it here. - */ - arm_rebuild_hflags(env); - } } =20 static void mdcr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -6894,9 +6851,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (arm_feature(env, ARM_FEATURE_STRONGARM)) { define_arm_cp_regs(cpu, strongarm_cp_reginfo); } - if (arm_feature(env, ARM_FEATURE_XSCALE)) { - define_arm_cp_regs(cpu, xscale_cp_reginfo); - } if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) { define_arm_cp_regs(cpu, dummy_c15_cp_reginfo); } @@ -7245,14 +7199,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .writefn =3D sctlr_write, .resetvalue =3D cpu->reset_sctlr, .raw_writefn =3D raw_write, }; - if (arm_feature(env, ARM_FEATURE_XSCALE)) { - /* - * Normally we would always end the TB on an SCTLR write, but = Linux - * arch/arm/mach-pxa/sleep.S expects two instructions following - * an MMU enable to execute from cache. Imitate this behaviou= r. - */ - sctlr.type |=3D ARM_CP_SUPPRESS_TB_END; - } define_one_arm_cp_reg(cpu, &sctlr); =20 if (arm_feature(env, ARM_FEATURE_PMSA) && diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 089eeff845c..6344971fa64 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1074,11 +1074,10 @@ static bool get_phys_addr_v5(CPUARMState *env, S1Tr= anslate *ptw, ap =3D (desc >> (4 + ((address >> 9) & 6))) & 3; result->f.lg_page_size =3D 12; break; - case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */ + case 3: /* 1k page, or ARMv6 "extended small (4k) page" */ if (type =3D=3D 1) { - /* ARMv6/XScale extended small page format */ - if (arm_feature(env, ARM_FEATURE_XSCALE) - || arm_feature(env, ARM_FEATURE_V6)) { + /* ARMv6 extended small page format */ + if (arm_feature(env, ARM_FEATURE_V6)) { phys_addr =3D (desc & 0xfffff000) | (address & 0xfff); result->f.lg_page_size =3D 12; } else { diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 575e566280b..5373e0e998c 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -768,12 +768,6 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *e= nv, uint32_t key, =20 assert(ri !=3D NULL); =20 - if (arm_feature(env, ARM_FEATURE_XSCALE) && ri->cp < 14 - && extract32(env->cp15.c15_cpar, ri->cp, 1) =3D=3D 0) { - res =3D CP_ACCESS_UNDEFINED; - goto fail; - } - if (ri->accessfn) { res =3D ri->accessfn(env, ri, isread); } --=20 2.43.0 From nobody Sat Nov 15 00:45:06 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758046452; cv=none; d=zohomail.com; s=zohoarc; b=TIyzgxkid+LXMZS8mzhBAQ6QXOvZIqy1zbGo1x+GXrZtUCqiUH4Y0ZgyoFFSO/08DF9Mu/ICNtkLLeDEW5txeIHCFxC0iScETdEwuNBs9oqF7ylUAAnvaHFx8538jrN5D8h9I8lnPXQMYhkpiHaFsqzgGl++RnpED+6SWlsoTCY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758046452; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=1mgWq+XLJB78p1c1ZffyK1tRiq8+FbVO+cvOUHxJI0A=; b=Jcpx7CFWwZO0Z/cpcPq2mdFIiF32XddP6MvPw0optZQ2dcjVKwQGpVSpwZCjse6fOuvp4ifgUtPRRKg+tBNFM1XgqcWhJowklha/RD6AkvxeMYhIfWtrx9clq/hyD0NU/TxcLK66CZZ9yKSr96iiu0EHg517Zf2v3XMKiCm7Dzg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758046452037354.5265599848053; Tue, 16 Sep 2025 11:14:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uya5V-0003qq-Hb; Tue, 16 Sep 2025 14:07:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uya4c-00037n-O1 for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:06:46 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uya4Z-0001cE-V4 for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:06:38 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-45dcff2f313so36463695e9.0 for ; Tue, 16 Sep 2025 11:06:35 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3e760775880sm23033286f8f.2.2025.09.16.11.06.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 11:06:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758045994; x=1758650794; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=1mgWq+XLJB78p1c1ZffyK1tRiq8+FbVO+cvOUHxJI0A=; b=g6E6Hs2L2sz3aXYoapdgO6irdKa8S+TLloMP4/+Tm9ohxUG+AnQwrqGzgtbJCDuNTn hR2TNNII5QFZ0A4EY0RRKNhljV4vQOnfQJPYDcjiM4KXZjqrDy+8nelSKARYFfm4T7Qi AZdeKBrOxzwCq4zQigjAKCI41M5yt3Fsb+vrXwzqrzVnv2gSQXTrhV0NCbdj7lXzp4qm 7t2/O7vnip0EC4iCnCKWUY4fHb1CcamzbK76qNFnfEaf5+ACqzN7bjgQ2/YFmhjKMCSS +M91DMT4c4hmqpir0wbLU0QHwoI6vxoX0sfxZVpVPBJ7TB255X13X5Xbal05uyD5XsHH ZjqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758045994; x=1758650794; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1mgWq+XLJB78p1c1ZffyK1tRiq8+FbVO+cvOUHxJI0A=; b=XJZ0qWewOaL85Qf/k4uEgiHrvNrO4AQCPXhWAZzWvsrHyiToya8svt8z+Pa4FpvNeF ZwP3RY+GSygs/mpMKsxUd9Jz+H5u/N1iYlCDq0Z8awVXDxffAuugMUke2RdkzZB/W32f iyWJKTy9mcvDSLaYYbVaYt0wSXhzeKv/M8oyvZwJsfsnABbkI4FhOjnCYKNhSC2NNMsP BgJDyHguui4HOqc24Ye1rsKQw2r1G+VU1VQhcq/ATT2B8esXM5QGls3acYr/GBOdIRnK LgKNoQAIOKmD49N9e1emazbd3UPVHFxh3j1XAgF5K9rzcHdnKXTgUm5Frkqx0VhtGEXZ CPWA== X-Gm-Message-State: AOJu0YyqPJqSg4n6rQF2tZc3o0QVWwwnWPutvfbXTM/Zrwd5zTl4Bmgn Por3LohTbbaVfOGEsuMewGi1yIQdT3TH64EK7k1es7sNP68uT9DTvqB7uonOmMAKIzZUonk3x72 bP2Vr X-Gm-Gg: ASbGncvHu49blPCQM234/njsHRAab7RR2wjM0+hvEW/qNnaadcEbbcYRCyqE+mqlg9e N4Zj8dsecdl046q7e57jJEZ8E2z0InSE9IRSdloDieuMqoWNddxKxiRKng02Rb/xYRFLC5oBvAn qF2QkzBQ7eCV5pb44mFncK+OKyaxsLKDGl8P3M6AIvS+Ay8c4I9TPj3/vOX0MCwn+CMUd7Ga/M4 lDtD+PgAUlxWUdJ7j4Thn7lw+O34b2a9Kue3EszqRC44zcvLvTUKeXhbAUctPQJklQr8994++Fx 3+JuejFrXA7tuS7z0/t2HXeS+IPwj/ybE+IKbBQ6eJNVpWPJDOwP6UaCch8xFJC0je7D4Pn0j2e d47HFeYAK4eInhgf41ya7cY3opZTo X-Google-Smtp-Source: AGHT+IG+2a7Mn7vaI0A/l4I1viiqGG+69vkh5BaStzwV3frau6XAXLY/GHzLS4yFfBCIttICoTO11g== X-Received: by 2002:a05:600c:19c9:b0:45d:d291:5dc1 with SMTP id 5b1f17b1804b1-45f211da6aamr149292015e9.15.1758045994156; Tue, 16 Sep 2025 11:06:34 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/36] target/arm: Drop ARM_FEATURE_IWMMXT handling Date: Tue, 16 Sep 2025 19:05:53 +0100 Message-ID: <20250916180611.1481266-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916180611.1481266-1-peter.maydell@linaro.org> References: <20250916180611.1481266-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758046453434116600 We have now removed all the CPU types which had the Intel XScale extensions indicated via ARM_FEATURE_IWMMXT, so this feature bit is never set. Remove all the code that can only be reached when using this flag. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20250828140422.3271703-6-peter.maydell@linaro.org --- bsd-user/arm/target_arch_elf.h | 1 - target/arm/cpu.h | 19 ---------- linux-user/arm/elfload.c | 1 - linux-user/arm/signal.c | 67 ---------------------------------- target/arm/cpu.c | 8 ---- target/arm/machine.c | 21 ----------- 6 files changed, 117 deletions(-) diff --git a/bsd-user/arm/target_arch_elf.h b/bsd-user/arm/target_arch_elf.h index b1c0fd2b320..b54bf5fbc69 100644 --- a/bsd-user/arm/target_arch_elf.h +++ b/bsd-user/arm/target_arch_elf.h @@ -86,7 +86,6 @@ static uint32_t get_elf_hwcap(void) /* probe for the extra features */ /* EDSP is in v5TE and above */ GET_FEATURE(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP); - GET_FEATURE(ARM_FEATURE_IWMMXT, ARM_HWCAP_ARM_IWMMXT); GET_FEATURE(ARM_FEATURE_THUMB2EE, ARM_HWCAP_ARM_THUMBEE); GET_FEATURE(ARM_FEATURE_NEON, ARM_HWCAP_ARM_NEON); GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS); diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 92fcb96671e..6644043f4c2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -697,14 +697,6 @@ typedef struct CPUArchState { */ uint64_t exclusive_high; =20 - /* iwMMXt coprocessor state. */ - struct { - uint64_t regs[16]; - uint64_t val; - - uint32_t cregs[16]; - } iwmmxt; - struct { ARMPACKey apia; ARMPACKey apib; @@ -1863,16 +1855,6 @@ enum arm_cpu_mode { /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ #define QEMU_VFP_FPSCR_NZCV 0xffff =20 -/* iwMMXt coprocessor control registers. */ -#define ARM_IWMMXT_wCID 0 -#define ARM_IWMMXT_wCon 1 -#define ARM_IWMMXT_wCSSF 2 -#define ARM_IWMMXT_wCASF 3 -#define ARM_IWMMXT_wCGR0 8 -#define ARM_IWMMXT_wCGR1 9 -#define ARM_IWMMXT_wCGR2 10 -#define ARM_IWMMXT_wCGR3 11 - /* V7M CCR bits */ FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) FIELD(V7M_CCR, USERSETMPEND, 1, 1) @@ -2442,7 +2424,6 @@ QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= =3D R_V7M_CSSELR_INDEX_MASK); */ enum arm_features { ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ - ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ ARM_FEATURE_V6, ARM_FEATURE_V6K, ARM_FEATURE_V7, diff --git a/linux-user/arm/elfload.c b/linux-user/arm/elfload.c index 308ed23fcbd..b1a4db44660 100644 --- a/linux-user/arm/elfload.c +++ b/linux-user/arm/elfload.c @@ -76,7 +76,6 @@ abi_ulong get_elf_hwcap(CPUState *cs) =20 /* EDSP is in v5TE and above, but all our v5 CPUs are v5TE */ GET_FEATURE(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP); - GET_FEATURE(ARM_FEATURE_IWMMXT, ARM_HWCAP_ARM_IWMMXT); GET_FEATURE(ARM_FEATURE_THUMB2EE, ARM_HWCAP_ARM_THUMBEE); GET_FEATURE(ARM_FEATURE_NEON, ARM_HWCAP_ARM_NEON); GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS); diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c index 8db1c4b2338..3b387cd6d78 100644 --- a/linux-user/arm/signal.c +++ b/linux-user/arm/signal.c @@ -76,21 +76,7 @@ struct target_vfp_sigframe { struct target_user_vfp_exc ufp_exc; } __attribute__((__aligned__(8))); =20 -struct target_iwmmxt_sigframe { - abi_ulong magic; - abi_ulong size; - uint64_t regs[16]; - /* Note that not all the coprocessor control registers are stored here= */ - uint32_t wcssf; - uint32_t wcasf; - uint32_t wcgr0; - uint32_t wcgr1; - uint32_t wcgr2; - uint32_t wcgr3; -} __attribute__((__aligned__(8))); - #define TARGET_VFP_MAGIC 0x56465001 -#define TARGET_IWMMXT_MAGIC 0x12ef842a =20 struct sigframe { @@ -267,25 +253,6 @@ static abi_ulong *setup_sigframe_vfp(abi_ulong *regspa= ce, CPUARMState *env) return (abi_ulong*)(vfpframe+1); } =20 -static abi_ulong *setup_sigframe_iwmmxt(abi_ulong *regspace, CPUARMState *= env) -{ - int i; - struct target_iwmmxt_sigframe *iwmmxtframe; - iwmmxtframe =3D (struct target_iwmmxt_sigframe *)regspace; - __put_user(TARGET_IWMMXT_MAGIC, &iwmmxtframe->magic); - __put_user(sizeof(*iwmmxtframe), &iwmmxtframe->size); - for (i =3D 0; i < 16; i++) { - __put_user(env->iwmmxt.regs[i], &iwmmxtframe->regs[i]); - } - __put_user(env->vfp.xregs[ARM_IWMMXT_wCSSF], &iwmmxtframe->wcssf); - __put_user(env->vfp.xregs[ARM_IWMMXT_wCASF], &iwmmxtframe->wcssf); - __put_user(env->vfp.xregs[ARM_IWMMXT_wCGR0], &iwmmxtframe->wcgr0); - __put_user(env->vfp.xregs[ARM_IWMMXT_wCGR1], &iwmmxtframe->wcgr1); - __put_user(env->vfp.xregs[ARM_IWMMXT_wCGR2], &iwmmxtframe->wcgr2); - __put_user(env->vfp.xregs[ARM_IWMMXT_wCGR3], &iwmmxtframe->wcgr3); - return (abi_ulong*)(iwmmxtframe+1); -} - static void setup_sigframe(struct target_ucontext *uc, target_sigset_t *set, CPUARMState *env) { @@ -306,9 +273,6 @@ static void setup_sigframe(struct target_ucontext *uc, if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { regspace =3D setup_sigframe_vfp(regspace, env); } - if (arm_feature(env, ARM_FEATURE_IWMMXT)) { - regspace =3D setup_sigframe_iwmmxt(regspace, env); - } =20 /* Write terminating magic word */ __put_user(0, regspace); @@ -435,31 +399,6 @@ static abi_ulong *restore_sigframe_vfp(CPUARMState *en= v, abi_ulong *regspace) return (abi_ulong*)(vfpframe + 1); } =20 -static abi_ulong *restore_sigframe_iwmmxt(CPUARMState *env, - abi_ulong *regspace) -{ - int i; - abi_ulong magic, sz; - struct target_iwmmxt_sigframe *iwmmxtframe; - iwmmxtframe =3D (struct target_iwmmxt_sigframe *)regspace; - - __get_user(magic, &iwmmxtframe->magic); - __get_user(sz, &iwmmxtframe->size); - if (magic !=3D TARGET_IWMMXT_MAGIC || sz !=3D sizeof(*iwmmxtframe)) { - return 0; - } - for (i =3D 0; i < 16; i++) { - __get_user(env->iwmmxt.regs[i], &iwmmxtframe->regs[i]); - } - __get_user(env->vfp.xregs[ARM_IWMMXT_wCSSF], &iwmmxtframe->wcssf); - __get_user(env->vfp.xregs[ARM_IWMMXT_wCASF], &iwmmxtframe->wcssf); - __get_user(env->vfp.xregs[ARM_IWMMXT_wCGR0], &iwmmxtframe->wcgr0); - __get_user(env->vfp.xregs[ARM_IWMMXT_wCGR1], &iwmmxtframe->wcgr1); - __get_user(env->vfp.xregs[ARM_IWMMXT_wCGR2], &iwmmxtframe->wcgr2); - __get_user(env->vfp.xregs[ARM_IWMMXT_wCGR3], &iwmmxtframe->wcgr3); - return (abi_ulong*)(iwmmxtframe + 1); -} - static int do_sigframe_return(CPUARMState *env, target_ulong context_addr, struct target_ucontext *uc) @@ -482,12 +421,6 @@ static int do_sigframe_return(CPUARMState *env, return 1; } } - if (arm_feature(env, ARM_FEATURE_IWMMXT)) { - regspace =3D restore_sigframe_iwmmxt(env, regspace); - if (!regspace) { - return 1; - } - } =20 target_restore_altstack(&uc->tuc_stack, env); =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9781055bdc1..02e2a31a863 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -247,10 +247,6 @@ static void arm_cpu_reset_hold(Object *obj, ResetType = type) =20 cpu->power_state =3D cs->start_powered_off ? PSCI_OFF : PSCI_ON; =20 - if (arm_feature(env, ARM_FEATURE_IWMMXT)) { - env->iwmmxt.cregs[ARM_IWMMXT_wCID] =3D 0x69051000 | 'Q'; - } - if (arm_feature(env, ARM_FEATURE_AARCH64)) { /* 64 bit CPUs always start in 64 bit mode */ env->aarch64 =3D true; @@ -2610,14 +2606,10 @@ static const Property arm_cpu_properties[] =3D { static const gchar *arm_gdb_arch_name(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; =20 if (arm_gdbstub_is_aarch64(cpu)) { return "aarch64"; } - if (arm_feature(env, ARM_FEATURE_IWMMXT)) { - return "iwmmxt"; - } return "arm"; } =20 diff --git a/target/arm/machine.c b/target/arm/machine.c index 6986915bee8..6666a0c50c4 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -221,26 +221,6 @@ static const VMStateDescription vmstate_vfp =3D { } }; =20 -static bool iwmmxt_needed(void *opaque) -{ - ARMCPU *cpu =3D opaque; - CPUARMState *env =3D &cpu->env; - - return arm_feature(env, ARM_FEATURE_IWMMXT); -} - -static const VMStateDescription vmstate_iwmmxt =3D { - .name =3D "cpu/iwmmxt", - .version_id =3D 1, - .minimum_version_id =3D 1, - .needed =3D iwmmxt_needed, - .fields =3D (const VMStateField[]) { - VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16), - VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16), - VMSTATE_END_OF_LIST() - } -}; - /* The expression ARM_MAX_VQ - 2 is 0 for pure AArch32 build, * and ARMPredicateReg is actively empty. This triggers errors * in the expansion of the VMSTATE macros. @@ -1102,7 +1082,6 @@ const VMStateDescription vmstate_arm_cpu =3D { }, .subsections =3D (const VMStateDescription * const []) { &vmstate_vfp, - &vmstate_iwmmxt, &vmstate_m, &vmstate_thumb2ee, /* pmsav7_rnr must come before pmsav7 so that we have the --=20 2.43.0 From nobody Sat Nov 15 00:45:06 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758046443; cv=none; d=zohomail.com; s=zohoarc; b=Sxh2ZK+tUXh62LJwtobxfPLj+tXqpCQ6pw1uIIy1gDSgO7gihLtKU+nCOKhI22ouGmHhmUmat8mxiL1Ylr1IzI5nG9JnzWE8kNPYTwITyVVuxX1RKKNKY7v75UefkCOTMI6JjfhcIbCI73ZnwViYUwJbclQv4kAt0U2IX2je6Sg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758046443; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=iUSGbKecK/il7MHJUX3WdtSZLN2LPW6TZ0vx6cLCdjI=; b=T8e0LKJlESfPIMQrvgn+WB6NHBDaBiinvWwEIVgLHP3jc+LNjqipxI7CFxJvy6pINdoftlbUn2sVzbaI0yinOYQg0LsgztrZsTq7y77ZSYlyYATzdOpg/LCm2WtB0lKMk8RVfMLOo2xyXiW2u3ptpZsXqakeCW3LEK7QeQ78g0w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758046443160573.3730987661169; Tue, 16 Sep 2025 11:14:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uya5p-0004nS-TM; Tue, 16 Sep 2025 14:07:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uya4m-000399-SQ for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:06:52 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uya4c-0001cK-EE for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:06:40 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-45f2c5ef00fso24679365e9.1 for ; Tue, 16 Sep 2025 11:06:37 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3e760775880sm23033286f8f.2.2025.09.16.11.06.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 11:06:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758045996; x=1758650796; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=iUSGbKecK/il7MHJUX3WdtSZLN2LPW6TZ0vx6cLCdjI=; b=lMo3ZMXr41HWUPrXx1/FZR3jAUna+ItSSNOkh3qOooHVvxNEhaJn8ZmySJsm6FqGer PvK9D4ljsErESQIppa2JRcYj2nqdQKRs1JhXCP/Sw1mPX/OqchHCJEAz0WU/xCwOXRF4 nPMxauXvDQog2D3exTMXE7d1AHOfyfJGcHAn4i3pTZrNTlkQMaBYjrcJAXNF76hj3mhF 4EBC0FbLuGJwOUPaCzJGktLa3stMNURJigm3jA5b4MRsRsRnK13ilD9PIiGnoWnP/Tub 3a6oOD0Rtj2kru9n2IhHeLzy8/5KyuXpX9s5ePTlhm8nAP+KjiQg3xI+Bin5ZsJ8Z2iR P3iw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758045996; x=1758650796; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iUSGbKecK/il7MHJUX3WdtSZLN2LPW6TZ0vx6cLCdjI=; b=fWO3lIYRa0rAX4Wv5qfKxwz4WiBTCupf+LoWAcbT8f0momwG9xNBfFjdQDmJPSRcyy iKSsX7Nh17VEzAOJyC2kbd3iYJHLbwSoE0tgI7zeYOy2epoyfvALV2ZkSvq7NeWW4zTF cyfdEmycbG4fDzUw3RHMRnQ07jpT/IFaXbhJKaOOGU1Rzh8ztpvy3Qro5xlPp4DE+MnJ hTHR+6FloU5jEsfcH98ToNmJzOcvCaNAbuX4G8mL/P4OfhtF+ODfZH0HnhwWuVKxUD6l rCcnq7KliNjLRdiGQL4cVF0ufalNXAC/nfaoeFFGS7QLsrpBaTJf78l+MYTk5q5l5K3H nmYw== X-Gm-Message-State: AOJu0YwkqTyy3CS3XnvNNEaBe2op2FrR906x8ay3ZeEbsxY5AQeZ7CUh /BXp32BmaQnVlSTwOwsz4gcmhp3MEEO7lxF9zYjDhM6xeVmSK2Obt+tLZj/wrvjb4/cut+7vx/G LPo4J X-Gm-Gg: ASbGncvJa7FmDwfauGaAp0Rw4qgIXGhgzWzbB1fX1NFZ4EMmmZ/wdm4qGR+zJ8zfVn0 hDLtRSIvh4UFgCcdrDTa4eFoDdPXC+XbDRDvMn5QsrR6APajVJKDwV8sclf5cQgE6kDDyV9Drd1 7qFCqbMPUF+Mur4SpXOeMzGt9LDM+RNSRWBQMIeybtrwuztfdQtFb20L1Gz0M/siHnq0xRTu1dg QFBKw+/QlCrKBcsX4638WbsXdHQFB9ElOIBvVeb2/G/8b887YXo8QmXHGN8fd2v5zp+TPZrhpUE IM5VbzqOVOT/xgO/XDxs1WQ5W9SrU06+pTGvL61mI3ek0FTlNvGlRHHrv3ppXJer/e3NxjAmmmn IYDcGW79/L6qcN9Exw4rtXu62VwWQ X-Google-Smtp-Source: AGHT+IHxsv5UH8m/FIUnvHir7BW0eDdGEDIGfdLgij1cFOQAbNPYT+wp+3EX8qZfwkgEVFBbzrP93Q== X-Received: by 2002:a05:600c:45c4:b0:45b:9912:9f30 with SMTP id 5b1f17b1804b1-45f211ca9a5mr173953065e9.6.1758045995510; Tue, 16 Sep 2025 11:06:35 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/36] system: drop the -old-param option Date: Tue, 16 Sep 2025 19:05:54 +0100 Message-ID: <20250916180611.1481266-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916180611.1481266-1-peter.maydell@linaro.org> References: <20250916180611.1481266-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758046445300116600 We deprecated the command line option -old-param for the 10.0 release, which allows us to drop it in 10.2. This option was used to boot Arm targets with a very old boot protocol using the 'param_struct' ABI. We only ever needed this on a handful of board types which have all now been removed from QEMU. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Thomas Huth Reviewed-by: Manos Pitsidianakis Reviewed-by: Alex Benn=C3=A9e Message-id: 20250828162700.3308812-1-peter.maydell@linaro.org --- docs/about/deprecated.rst | 13 ------ docs/about/removed-features.rst | 12 +++++ include/system/system.h | 1 - hw/arm/boot.c | 81 +-------------------------------- system/globals.c | 1 - system/vl.c | 4 -- qemu-options.hx | 7 --- 7 files changed, 13 insertions(+), 106 deletions(-) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index f0314147698..03f7cabf730 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -68,19 +68,6 @@ configurations (e.g. -smp drawers=3D1,books=3D1,clusters= =3D1 for x86 PC machine) is marked deprecated since 9.0, users have to ensure that all the topology me= mbers described with -smp are supported by the target machine. =20 -``-old-param`` option for booting Arm kernels via param_struct (since 10.0) -''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' - -The ``-old-param`` command line option is specific to Arm targets: -it is used when directly booting a guest kernel to pass it the -command line and other information via the old ``param_struct`` ABI, -rather than the newer ATAGS or DTB mechanisms. This option was only -ever needed to support ancient kernels on some old board types -like the ``akita`` or ``terrier``; it has been deprecated in the -kernel since 2001. None of the board types QEMU supports need -``param_struct`` support, so this option has been deprecated and will -be removed in a future QEMU version. - QEMU Machine Protocol (QMP) commands ------------------------------------ =20 diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.= rst index 65fd564d229..07ca4079d4b 100644 --- a/docs/about/removed-features.rst +++ b/docs/about/removed-features.rst @@ -560,6 +560,18 @@ the options along with the machine models they were in= tended for. =20 Use ``-run-with user=3D..`` instead. =20 +``-old-param`` option for booting Arm kernels via param_struct (removed in= 10.2) +''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''= '''''' + +The ``-old-param`` command line option was specific to Arm targets: +it was used when directly booting a guest kernel to pass it the +command line and other information via the old ``param_struct`` ABI, +rather than the newer ATAGS or DTB mechanisms. This option was only +ever needed to support ancient kernels on some old board types +like the ``akita`` or ``terrier``; it has been deprecated in the +kernel since 2001. None of the board types QEMU supports need +``param_struct`` support, so this option has been removed. + =20 User-mode emulator command line arguments ----------------------------------------- diff --git a/include/system/system.h b/include/system/system.h index a7effe7dfd8..03a2d0e9005 100644 --- a/include/system/system.h +++ b/include/system/system.h @@ -42,7 +42,6 @@ extern int graphic_height; extern int graphic_depth; extern int display_opengl; extern const char *keyboard_layout; -extern int old_param; extern uint8_t *boot_splash_filedata; extern bool enable_cpu_pm; extern QEMUClockType rtc_clock; diff --git a/hw/arm/boot.c b/hw/arm/boot.c index d0840308f5a..e77d8679d88 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -337,81 +337,6 @@ static void set_kernel_args(const struct arm_boot_info= *info, AddressSpace *as) WRITE_WORD(p, 0); } =20 -static void set_kernel_args_old(const struct arm_boot_info *info, - AddressSpace *as) -{ - hwaddr p; - const char *s; - int initrd_size =3D info->initrd_size; - hwaddr base =3D info->loader_start; - - /* see linux/include/asm-arm/setup.h */ - p =3D base + KERNEL_ARGS_ADDR; - /* page_size */ - WRITE_WORD(p, 4096); - /* nr_pages */ - WRITE_WORD(p, info->ram_size / 4096); - /* ramdisk_size */ - WRITE_WORD(p, 0); -#define FLAG_READONLY 1 -#define FLAG_RDLOAD 4 -#define FLAG_RDPROMPT 8 - /* flags */ - WRITE_WORD(p, FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT); - /* rootdev */ - WRITE_WORD(p, (31 << 8) | 0); /* /dev/mtdblock0 */ - /* video_num_cols */ - WRITE_WORD(p, 0); - /* video_num_rows */ - WRITE_WORD(p, 0); - /* video_x */ - WRITE_WORD(p, 0); - /* video_y */ - WRITE_WORD(p, 0); - /* memc_control_reg */ - WRITE_WORD(p, 0); - /* unsigned char sounddefault */ - /* unsigned char adfsdrives */ - /* unsigned char bytes_per_char_h */ - /* unsigned char bytes_per_char_v */ - WRITE_WORD(p, 0); - /* pages_in_bank[4] */ - WRITE_WORD(p, 0); - WRITE_WORD(p, 0); - WRITE_WORD(p, 0); - WRITE_WORD(p, 0); - /* pages_in_vram */ - WRITE_WORD(p, 0); - /* initrd_start */ - if (initrd_size) { - WRITE_WORD(p, info->initrd_start); - } else { - WRITE_WORD(p, 0); - } - /* initrd_size */ - WRITE_WORD(p, initrd_size); - /* rd_start */ - WRITE_WORD(p, 0); - /* system_rev */ - WRITE_WORD(p, 0); - /* system_serial_low */ - WRITE_WORD(p, 0); - /* system_serial_high */ - WRITE_WORD(p, 0); - /* mem_fclk_21285 */ - WRITE_WORD(p, 0); - /* zero unused fields */ - while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) { - WRITE_WORD(p, 0); - } - s =3D info->kernel_cmdline; - if (s) { - address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, s, strlen(s) + = 1); - } else { - WRITE_WORD(p, 0); - } -} - static int fdt_add_memory_node(void *fdt, uint32_t acells, hwaddr mem_base, uint32_t scells, hwaddr mem_len, int numa_node_id) @@ -802,11 +727,7 @@ static void do_cpu_reset(void *opaque) cpu_set_pc(cs, info->loader_start); =20 if (!have_dtb(info)) { - if (old_param) { - set_kernel_args_old(info, as); - } else { - set_kernel_args(info, as); - } + set_kernel_args(info, as); } } else if (info->secondary_cpu_reset_hook) { info->secondary_cpu_reset_hook(cpu, info); diff --git a/system/globals.c b/system/globals.c index 9640c9511e9..98f9876d5d4 100644 --- a/system/globals.c +++ b/system/globals.c @@ -52,7 +52,6 @@ bool vga_interface_created; Chardev *parallel_hds[MAX_PARALLEL_PORTS]; QEMUOptionRom option_rom[MAX_OPTION_ROMS]; int nb_option_roms; -int old_param; const char *qemu_name; unsigned int nb_prom_envs; const char *prom_envs[MAX_PROM_ENVS]; diff --git a/system/vl.c b/system/vl.c index 3b7057e6c66..00f36947257 100644 --- a/system/vl.c +++ b/system/vl.c @@ -3524,10 +3524,6 @@ void qemu_init(int argc, char **argv) prom_envs[nb_prom_envs] =3D optarg; nb_prom_envs++; break; - case QEMU_OPTION_old_param: - warn_report("-old-param is deprecated"); - old_param =3D 1; - break; case QEMU_OPTION_rtc: opts =3D qemu_opts_parse_noisily(qemu_find_opts("rtc"), op= targ, false); diff --git a/qemu-options.hx b/qemu-options.hx index ab23f14d217..aa44b0e34ae 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -5347,13 +5347,6 @@ SRST specified, the former is passed to semihosting as it always takes precedence. ERST -DEF("old-param", 0, QEMU_OPTION_old_param, - "-old-param old param mode\n", QEMU_ARCH_ARM) -SRST -``-old-param`` - Old param mode (ARM only). -ERST - DEF("sandbox", HAS_ARG, QEMU_OPTION_sandbox, \ "-sandbox on[,obsolete=3Dallow|deny][,elevateprivileges=3Dallow|deny|c= hildren]\n" \ " [,spawn=3Dallow|deny][,resourcecontrol=3Dallow|deny]\n" \ --=20 2.43.0 From nobody Sat Nov 15 00:45:06 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758046173; cv=none; d=zohomail.com; s=zohoarc; b=ItJvWBLjOZ6wE8Vjs7MeKYs+eK+hY1BAqQfqpu7zCO+SmuuZbQvrDSoiwY3fXnDrr7gddIwK9PGVvNiIwkCOednY6c2xhY8Mgk/MRcl/KrRbQG2OsjWHZshyFY44wtC57GsPv4tQDkv0K8qTAVqERLgxOhO7le6TXjEOjYsIFes= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758046173; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=/e4QFB40Kd5xVAD2ukP5PCzshfLjtIczMIicFl3oFOU=; b=QNkVZZYxMIMr4O+KxihsaSe4wJDek/ZAM8m4kc8hT2nITOGjptOOkDVoCn+kp1r6jRxCTqo6lynJS4MzwbhC8KOJqjQrf4xZ13jmshut9cSijP6e89IyrSpZ8RJ5H4V2aVsQA6ntA9KYbf5z4iyky4yZ09rMKJpk5b9VBjkACl8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175804617374770.5421295050603; Tue, 16 Sep 2025 11:09:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uya5H-0003Y9-Kf; Tue, 16 Sep 2025 14:07:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uya4i-00038g-PR for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:06:48 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uya4c-0001cg-IN for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:06:40 -0400 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-3d44d734cabso3517680f8f.3 for ; Tue, 16 Sep 2025 11:06:38 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3e760775880sm23033286f8f.2.2025.09.16.11.06.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 11:06:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758045997; x=1758650797; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=/e4QFB40Kd5xVAD2ukP5PCzshfLjtIczMIicFl3oFOU=; b=PICNvghxoyqK9pUzmAdjyIu/YDyUQxbz2mBr7ffjquT1eioEk+ahXnxG1sPqKkVchL gLrQiP7k3GUuZwxq6w2P6Ik+JbO37OUjTiqXhg9rW7q8Vw5p9nVsjI+sN1PPFnv11I27 oJPbsrzgMdVO7mbvmWCndL+GwFbqLkXCTHubTBlNFLN9W6DwXr5w7pqpPuIOuqqfSyaj r38HeCrh0DuQHeBDmD90R7ua0GivIp3r2C47F89qNqC1mDZemd1dv1HRVhhx1uq0sgGl jx5Nlotn6ec9uCq6cF/hmapYEPKdscRTWAObakZRmGdck+qIIMOKxugEx6/pzAkLheuE 8ugw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758045997; x=1758650797; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/e4QFB40Kd5xVAD2ukP5PCzshfLjtIczMIicFl3oFOU=; b=iBcBJK4rfw5X0tb7d+qnuYdycQcDoYh4Osp8RQd/13WhGsR70VYa7GQz/XslSi/vIf VLjn8Nv8wX4ysJHCjtwN6w6rmrRX5lAPiL4oAWYG/Waus2M4NW6ps9O+PFhAQX0IMffJ lf5DZT/i/e9ig+/Kyiy99bVONKLUI1HSAjJFN/YTLf4fbYyfx59PJImU9+y3BNkbk9bN 9nBc5hbEcJ/BaVjmm9euyQFLTvvSE/SR5akVfopeDnDkto87ayIH5jIL6o4F0MuYQxcR fRd76qInHZQtEWIwmSV1t4lQLlspNqlfVCdN521+b47gbbcYgGsH8x0HY81aDvsFZlxZ 40Ew== X-Gm-Message-State: AOJu0YzD+XEXthEji0al0F8kh2wNigoMtXaxRuDRvPtF7WClH/nClO6q EFxP6qgIdRy4Hf2wqxro2hhy6JnSkzNh3T5np05NQ4632zdG3+dV3atlvqHuND9WQrp6ewQQKdH pvZb0 X-Gm-Gg: ASbGnctiasRT/jJZ5YixwojaA2H7hgqvb/IFKx4a4McWvwLUvUcmOsshdfO58YHEf/K yHNumRJNKYq/ZRRX11YpJBVr13dQab3q2yqMQdSPMeXGIxHVePMPdW3FMvrP6QqZRkj+Fko6gs1 b7ZWvr5paP5+0t8LGtaHfOy2l0SokzFgEPOEeo5+djAhwhqv0RvxCSTfCEC67iBWLxT8TYx+cLO c5kBiT5uX3t9/r5TBW31vu0IuCVmCXLxfhNcGeke+TdAPOqrWF9no8H70k5mBSD+0tR6FdeM0AL g69YRcpz+Y4WyOj4cWg5X0a7giU5i+7zRtRnZsFmlZz6N9Z5HkUHh8w0W5J/pQFmtSYlPzzGVTX 5tZGCzRSjqxR0yEs3YQyXu4h91FlC X-Google-Smtp-Source: AGHT+IHwX706fKouHMa3Qv6J9gvPGyae9Oz61rgIIeyY2z84Apis3lb6BYM+A+PzS3AyuaYdk0dtlA== X-Received: by 2002:a05:6000:230c:b0:3dc:1473:18bc with SMTP id ffacd0b85a97d-3e765530b01mr16650233f8f.0.1758045997000; Tue, 16 Sep 2025 11:06:37 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/36] arm/kvm: report registers we failed to set Date: Tue, 16 Sep 2025 19:05:55 +0100 Message-ID: <20250916180611.1481266-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916180611.1481266-1-peter.maydell@linaro.org> References: <20250916180611.1481266-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758046175529116600 Content-Type: text/plain; charset="utf-8" From: Cornelia Huck If we fail migration because of a mismatch of some registers between source and destination, the error message is not very informative: qemu-system-aarch64: error while loading state for instance 0x0 ofdevice 'c= pu' qemu-system-aarch64: Failed to put registers after init: Invalid argument At least try to give the user a hint which registers had a problem, even if they cannot really do anything about it right now. Sample output: Could not set register op0:3 op1:0 crn:0 crm:0 op2:0 to c00fac31 (is 413fd0= c1) We could be even more helpful once we support writable ID registers, at which point the user might actually be able to configure something that is migratable. Suggested-by: Eric Auger Reviewed-by: Sebastian Ott Signed-off-by: Cornelia Huck Message-id: 20250911154159.158046-1-cohuck@redhat.com Signed-off-by: Peter Maydell --- target/arm/kvm.c | 86 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 66723448554..c1ec6654ca6 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -900,6 +900,58 @@ bool write_kvmstate_to_list(ARMCPU *cpu) return ok; } =20 +/* pretty-print a KVM register */ +#define CP_REG_ARM64_SYSREG_OP(_reg, _op) \ + ((uint8_t)((_reg & CP_REG_ARM64_SYSREG_ ## _op ## _MASK) >> \ + CP_REG_ARM64_SYSREG_ ## _op ## _SHIFT)) + +static gchar *kvm_print_sve_register_name(uint64_t regidx) +{ + uint16_t sve_reg =3D regidx & 0x000000000000ffff; + + if (regidx =3D=3D KVM_REG_ARM64_SVE_VLS) { + return g_strdup_printf("SVE VLS"); + } + /* zreg, preg, ffr */ + switch (sve_reg & 0xfc00) { + case 0: + return g_strdup_printf("SVE zreg n:%d slice:%d", + (sve_reg & 0x03e0) >> 5, sve_reg & 0x001f); + case 0x04: + return g_strdup_printf("SVE preg n:%d slice:%d", + (sve_reg & 0x01e0) >> 5, sve_reg & 0x001f); + case 0x06: + return g_strdup_printf("SVE ffr slice:%d", sve_reg & 0x001f); + default: + return g_strdup_printf("SVE ???"); + } +} + +static gchar *kvm_print_register_name(uint64_t regidx) +{ + switch ((regidx & KVM_REG_ARM_COPROC_MASK)) { + case KVM_REG_ARM_CORE: + return g_strdup_printf("core reg %"PRIx64, regidx); + case KVM_REG_ARM_DEMUX: + return g_strdup_printf("demuxed reg %"PRIx64, regidx); + case KVM_REG_ARM64_SYSREG: + return g_strdup_printf("op0:%d op1:%d crn:%d crm:%d op2:%d", + CP_REG_ARM64_SYSREG_OP(regidx, OP0), + CP_REG_ARM64_SYSREG_OP(regidx, OP1), + CP_REG_ARM64_SYSREG_OP(regidx, CRN), + CP_REG_ARM64_SYSREG_OP(regidx, CRM), + CP_REG_ARM64_SYSREG_OP(regidx, OP2)); + case KVM_REG_ARM_FW: + return g_strdup_printf("fw reg %d", (int)(regidx & 0xffff)); + case KVM_REG_ARM64_SVE: + return kvm_print_sve_register_name(regidx); + case KVM_REG_ARM_FW_FEAT_BMAP: + return g_strdup_printf("fw feat reg %d", (int)(regidx & 0xffff= )); + default: + return g_strdup_printf("%"PRIx64, regidx); + } +} + bool write_list_to_kvmstate(ARMCPU *cpu, int level) { CPUState *cs =3D CPU(cpu); @@ -927,11 +979,45 @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level) g_assert_not_reached(); } if (ret) { + gchar *reg_str =3D kvm_print_register_name(regidx); + /* We might fail for "unknown register" and also for * "you tried to set a register which is constant with * a different value from what it actually contains". */ ok =3D false; + switch (ret) { + case -ENOENT: + error_report("Could not set register %s: unknown to KVM", + reg_str); + break; + case -EINVAL: + if ((regidx & KVM_REG_SIZE_MASK) =3D=3D KVM_REG_SIZE_U32) { + if (!kvm_get_one_reg(cs, regidx, &v32)) { + error_report("Could not set register %s to %x (is = %x)", + reg_str, (uint32_t)cpu->cpreg_values[= i], + v32); + } else { + error_report("Could not set register %s to %x", + reg_str, (uint32_t)cpu->cpreg_values[= i]); + } + } else /* U64 */ { + uint64_t v64; + + if (!kvm_get_one_reg(cs, regidx, &v64)) { + error_report("Could not set register %s to %"PRIx6= 4" (is %"PRIx64")", + reg_str, cpu->cpreg_values[i], v64); + } else { + error_report("Could not set register %s to %"PRIx6= 4, + reg_str, cpu->cpreg_values[i]); + } + } + break; + default: + error_report("Could not set register %s: %s", + reg_str, strerror(-ret)); + } + g_free(reg_str); } } return ok; --=20 2.43.0 From nobody Sat Nov 15 00:45:06 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758046100; cv=none; d=zohomail.com; s=zohoarc; b=h+ByxtGfy7OojYLixi0MXslKlP7mG7N0zLobFl3j4+NPI8NLwGPnZf62arjVp612Yv1KOqn4fyt9P99D3N1FX5xfD8ITonosh95qfb2ej2tThSN1xJJVc9m/w2po4pmFs5KJFN4hnUZ+nYDYX23w6h14uGb3v7pf4z1yjZCVA8g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758046100; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3e760775880sm23033286f8f.2.2025.09.16.11.06.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 11:06:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758045998; x=1758650798; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=MRFSvzFCChYzJp3NpcD51YiWf88/DwCTl/TXq4h9hsM=; b=hLV422k2kanQ1YWc0ioCmjZhBK2tK+Z5b4WOkWwb+2NbR1djer8Xn+1ECHzcjiZPED HMB678jTn8u7WWdyQJDFhDdARloToLD24mSauOqx7D8ZFLXBzv+V7BC0bnKlGGIAorfH q9eCNtEPR9OVmBRJoIiZNOf05N6i4+wII5alLCBTXthVkClIUcIZnfcRnWr0iXPljn2P 6Y6Id1sJt1G87yBCGGT7cxR/MB+ByC5/U1UzxCnCVN5d53ooXTdcJu37ppVNiXDPRdnE tbaF18WcIENx9x9EHF39q//p2sxSpLYBh9BWzDiZX8nSOr945UA1U1GE8rrg8M8xA4od JRyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758045998; x=1758650798; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MRFSvzFCChYzJp3NpcD51YiWf88/DwCTl/TXq4h9hsM=; b=sRxeS+Z1EtyINIQKlz7jhw7eMFuWGIcB7vzm9lghu4CR5wPuhzHmj3YqwtxdDAfk+z 4dA5YAiCtrKv+DwzpxGTlS/gTNUiN+P7TNIU5hhAwrRZ2C2RMvXsu6DL9vPLcjZS0HSY Eya3pf5KtewIc+wV4FPsf7zMFoQZh0cIjDAOK3lgFwxwdDnO9fCP3gmGg4NLK/XkJBbk C1TJMKudBde1XRHWjWrK0/ypsl9JIEljBsBpZkNVPY9r41wRLHzmvUmvqJs5i5l1VtgO yLF5PnORL41LqWk4kIniLXF3yKYNkseKxgjXjS+sA4K84v8X8RHis5Nr7J8mJ24oKWQq CyYw== X-Gm-Message-State: AOJu0Yzf1AZTYkwZb0HE8kzfyJqQCfjct3s2XRWm4/yDv9lcanNFyt4P OAuP3we0OBwBr6/SpSErgLVr+h3JQzljSSgbDRmWi5SZsHwSRpaxJPX8/85jpKpeiyWswjUpEA+ x7tro X-Gm-Gg: ASbGnctPZJrSkEuF9xZURM+O7SagQOLv5EDXzCfedACZ+/p1tBWoSIY/xxcWKy4EIp6 YZHOnLrjixP7na0EuFIUC5Ciy6zLisAoLLREn19WqbdHzBGWU37yslnOWTis2OaK33ABQxtUibQ IKTC4ZoqYYtJrOFOAtozR1S7owyXGIWtNJy5K+n4c5WyTMx6A01KX7J2K+9wdnLTwjjjjtVCwlr rPCRMogb/CtAz7f42nooutZmokzqP8VLe50nVmN1dqRcxZIY93mChsnPZEqGNRn8oyGJLrHA413 bIDQ+9GER1IU0Dv/kMwn+ISCitQuTbuX6HLU6LTLuHWDk9ygzzbAeapFngGbmQoIKNmUdZHzP05 xCd7Sgvw+FLCfNajYEetvmFJckh40 X-Google-Smtp-Source: AGHT+IFvuNkxlE3S11PG4LBPLfMGBCKSJ08y7vOWVR/+Y3rZ45tcOf1kXiE4Btish2XwEgk7zJjmqg== X-Received: by 2002:a5d:5d0a:0:b0:3e5:50:e070 with SMTP id ffacd0b85a97d-3e765a19cbbmr14632391f8f.50.1758045998114; Tue, 16 Sep 2025 11:06:38 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/36] target/arm: Increase MAX_PACKET_LENGTH for SME ZA remote gdb debugging Date: Tue, 16 Sep 2025 19:05:56 +0100 Message-ID: <20250916180611.1481266-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916180611.1481266-1-peter.maydell@linaro.org> References: <20250916180611.1481266-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758046102606116600 Content-Type: text/plain; charset="utf-8" From: Vacha Bhavsar This patch increases the value of the MAX_PACKET_LEGNTH to 131104 from 4096 to allow the GDBState.line_buf to be large enough to accommodate the full contents of the SME ZA storage when the vector length is maximal. This is in preparation for a related patch that allows SME register visibility through remote GDB debugging. Signed-off-by: Vacha Bhavsar Reviewed-by: Peter Maydell Message-id: 20250909161012.2561593-2-vacha.bhavsar@oss.qualcomm.com [PMM: fixed up comment formatting] Signed-off-by: Peter Maydell --- gdbstub/internals.h | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/gdbstub/internals.h b/gdbstub/internals.h index bf5a5c63029..92466b28c18 100644 --- a/gdbstub/internals.h +++ b/gdbstub/internals.h @@ -11,7 +11,27 @@ =20 #include "exec/cpu-common.h" =20 -#define MAX_PACKET_LENGTH 4096 +/* + * Most "large" transfers (e.g. memory reads, feature XML + * transfer) have mechanisms in the gdb protocol for splitting + * them. However, register values in particular cannot currently + * be split. This packet size must therefore be at least big enough + * for the worst-case register size. Currently that is Arm SME + * ZA storage with a 256x256 byte value. We also must account + * for the conversion from raw data to hex in gdb_memtohex(), + * which writes 2 * size bytes, and for other protocol overhead + * including command, register number and checksum which add + * another 4 bytes of overhead. However, to be consistent with + * the changes made in gdbserver to address this same requirement, + * we add a total of 32 bytes to account for protocol overhead + * (unclear why specifically 32 bytes), bringing the value of + * MAX_PACKET_LENGTH to 2 * 256 * 256 + 32 =3D 131104. + * + * The commit making this change for gdbserver can be found here: + * https://sourceware.org/git/?p=3Dbinutils-gdb.git;a=3Dcommit;h=3D + * b816042e88583f280ad186ff124ab84d31fb592b + */ +#define MAX_PACKET_LENGTH 131104 =20 /* * Shared structures and definitions --=20 2.43.0 From nobody Sat Nov 15 00:45:06 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758046094; cv=none; d=zohomail.com; s=zohoarc; b=inPiJpgrls3lo0dNil7hoLwyADYGO7ZE190yQ4kCDHgj9NT46hE2wiobuP0YlyCpiw8zVdeAa0PL5exlT/eVHk9Fcrht6BOobNwTpZVQsKtD0tWsLMJVvQjKbNlSK3gCrFp2t22MvGAzdfJu/dcuzE1nF4IRRbGwfRPzPkImA9Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758046094; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Zw0lxXrZ3sXM9zNmueYN9ABFbXL8fmNkpgwpH4pUGn4=; b=hjUg+hoN4tL4ybelqqPVEvvCtrLnbXqmniOeZSNUYe5khZD/XDLocbAqHu7732exVuULivJXcky5dxxNI/RGYoNxY3bChRnz5DmUfrtFS/Jd3ShiVVJZwXCANgBHFkDq4Ak8K2FTDEZhhBIOxG/ArvOGksQgc+6DHAEfMdFJWXw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758046094784162.75214085589994; Tue, 16 Sep 2025 11:08:14 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uya5h-0004GU-Sk; Tue, 16 Sep 2025 14:07:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uya4w-0003Ae-4l for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:06:59 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uya4n-0001d9-Pw for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:06:51 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-45f2f10502fso15508785e9.0 for ; Tue, 16 Sep 2025 11:06:41 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3e760775880sm23033286f8f.2.2025.09.16.11.06.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 11:06:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758046000; x=1758650800; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Zw0lxXrZ3sXM9zNmueYN9ABFbXL8fmNkpgwpH4pUGn4=; b=LOUYuMo2bzbFZaogDuFWO7aMINxdnzRCJGL/TgsWqoG+XUdmUNkomqHZ5qSRQ2BwxA ZGyLrilSi+/weJMN1HQq4agh8Enxaizyye+ADRX64+QJNnTzIx2SPE1syBt6/GNxgbS0 FPOfeIWkmUP2BskbasN+vnGosEXKPvuBGs7D4dsKpuK7Hmgfz0RUBjfEJqwgAT0D9oih bW3g+z0NVhTFEsKdTTEIsynYmgynKRb2Zl9RUeBuFDqNZyzsBfzCWW591LYlVgblqU0m ehASN+lH36fUb1MQep4C6b6QsFuAnGAMdu2Thd7cfINGt8PanVRtTp7vW4dh3uQjoClP nXFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758046000; x=1758650800; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Zw0lxXrZ3sXM9zNmueYN9ABFbXL8fmNkpgwpH4pUGn4=; b=LJkIzoP8yJmJMPrhKWQu3CYTUcpLYyfl3Ch2B+eSjqXtudWzSN8y7yWzzaClPlV375 LFwhg+q9sUh4VtjxUcFcP63qZG1iWkfgdTAb7JSYgizwj3VWAfS9qqjwRmQtvkZzDvH7 TTYaknL+mZTEvY4mxSl/htA4EA0E8F2DihBT5Y1l4ZFeD4D8EeoVPlZ7Iu7XT7cKyPj4 FPRH2xs+2P0HLEElwXoOPXk3lp7qsehOvawoj6mMlXGZThWFhp4HGkaMa13ITLtl4MDo HsbWsHwWFVyoK4cc+zIpTSQ2YIaRDRKUMwXsgjAwJKgexmfxWAGwpGKsmnZdY5HyTbno 6Fqw== X-Gm-Message-State: AOJu0YxtKWkiLu7CTG09R+KZh0R2WHsTxSx3geqcfDVBoegXrzsdIbw/ jcRRtp2KJPMRKbdJLFaTfc7voLKLcwzrNSKfNBAMeXXaG10at5joJb/oPTh/wfUJQSgLFIoTeRE Q/jNh X-Gm-Gg: ASbGncvz977Tsr23tufhLJuqnYLSvPfGTyrwcyJ9h5Tezr0EHCQm/dF5DVmfK0u2QGJ ksidjnZmF94rmsq1A3ET2rhfTwN2zozfjTeWl1a3sXZFn+Y4rxPqYXikaj/ILpPucOm84kAM6Oc GwaRJLg3lOGSa2fNes3JpCGDToeYgc2suKjS+Mflw3FHjtOF1lBHveMgdagFEhD2hAwgFybTgpB b83j5eW9Z83C4ySaNtUbhWEFwtqIrSn+hM8JYG7hOBRPY/ttJErPFHmA7MmAijtsLMeuFK6jwXT bp4mQS5QRl3dYTOcdGP8RYRDpgajSkEeCvAS6QZR6Pu+rmGWQXJdKTAT9B+mq7zER6RJpwRUvCC bcGeBK6y6AedtOSHrkkhjA4s10rhKmF7tlzJsYig= X-Google-Smtp-Source: AGHT+IFUP6cJ9GMZ0USQ4nlRhELZjWjIF0nhfAcy31LL2DDclTFrkVGy/MtZPfBBIhiga+l4EEvqgA== X-Received: by 2002:a05:600c:22d4:b0:450:6b55:cf91 with SMTP id 5b1f17b1804b1-45f211cb52amr144808095e9.6.1758046000025; Tue, 16 Sep 2025 11:06:40 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/36] target/arm: Added support for SME register exposure to GDB Date: Tue, 16 Sep 2025 19:05:57 +0100 Message-ID: <20250916180611.1481266-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916180611.1481266-1-peter.maydell@linaro.org> References: <20250916180611.1481266-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758046096763116600 Content-Type: text/plain; charset="utf-8" From: Vacha Bhavsar The QEMU GDB stub does not expose the ZA storage SME register to GDB via the remote serial protocol, which can be a useful functionality to debug SME code. To provide this functionality for AArch64 targets, this patch registers the SME register set with the GDB stub. To do so, this patch implements the aarch64_gdb_get_sme_reg() and aarch64_gdb_set_sme_reg() functions to specify how to get and set the SME registers, and the arm_gen_dynamic_smereg_feature() function to generate the target description in XML format to indicate the target architecture supports SME. Finally, this patch includes a dyn_smereg_feature structure to hold this GDB XML description of the SME registers for each CPU. Note that according to the GDB documentation the ZA register is defined as a vector of bytes; however the target description xml retrieved when using gdb natively on a host with SME capabilities represents the ZA register as a vector of vectors of bytes, so this is a GDB documentation error. We follow GDB's own gdbstub implementation and represent the ZA register as a vector of vectors of bytes as is done by GDB here: https://github.com/bminor/binutils-gdb/blob/5cce2b7006daa7073b98e3d1a3b1761= 99d1381d7/gdb/features/aarch64-sme.c#L50 Signed-off-by: Vacha Bhavsar Message-id: 20250909161012.2561593-3-vacha.bhavsar@oss.qualcomm.com Reviewed-by: Peter Maydell [PMM: fixed minor checkpatch nits] Signed-off-by: Peter Maydell --- target/arm/cpu.h | 1 + target/arm/internals.h | 3 ++ target/arm/gdbstub.c | 10 +++- target/arm/gdbstub64.c | 119 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 132 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6644043f4c2..1c0deb723d7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -925,6 +925,7 @@ struct ArchCPU { =20 DynamicGDBFeatureInfo dyn_sysreg_feature; DynamicGDBFeatureInfo dyn_svereg_feature; + DynamicGDBFeatureInfo dyn_smereg_feature; DynamicGDBFeatureInfo dyn_m_systemreg_feature; DynamicGDBFeatureInfo dyn_m_secextreg_feature; =20 diff --git a/target/arm/internals.h b/target/arm/internals.h index 8782594b774..532fabcafc1 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1817,8 +1817,11 @@ static inline uint64_t pmu_counter_mask(CPUARMState = *env) } =20 GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *cpu, int base_reg); +GDBFeature *arm_gen_dynamic_smereg_feature(CPUState *cpu, int base_reg); int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray *buf, int reg); int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf, int reg); +int aarch64_gdb_get_sme_reg(CPUState *cs, GByteArray *buf, int reg); +int aarch64_gdb_set_sme_reg(CPUState *cs, uint8_t *buf, int reg); int aarch64_gdb_get_fpu_reg(CPUState *cs, GByteArray *buf, int reg); int aarch64_gdb_set_fpu_reg(CPUState *cs, uint8_t *buf, int reg); int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int reg); diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index ce4497ad7c3..2d331fff445 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -527,7 +527,8 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) * registers so we don't need to include both. */ #ifdef TARGET_AARCH64 - if (isar_feature_aa64_sve(&cpu->isar)) { + if (isar_feature_aa64_sve(&cpu->isar) || + isar_feature_aa64_sme(&cpu->isar)) { GDBFeature *feature =3D arm_gen_dynamic_svereg_feature(cs, cs-= >gdb_num_regs); gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg, aarch64_gdb_set_sve_reg, feature, 0); @@ -537,6 +538,13 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cp= u) gdb_find_static_feature("aarch64-fpu.= xml"), 0); } + + if (isar_feature_aa64_sme(&cpu->isar)) { + GDBFeature *sme_feature =3D + arm_gen_dynamic_smereg_feature(cs, cs->gdb_num_regs); + gdb_register_coprocessor(cs, aarch64_gdb_get_sme_reg, + aarch64_gdb_set_sme_reg, sme_feature,= 0); + } /* * Note that we report pauth information via the feature name * org.gnu.gdb.aarch64.pauth_v2, not org.gnu.gdb.aarch64.pauth. diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 08e28585396..3bccde2bf25 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -249,6 +249,90 @@ int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf= , int reg) return 0; } =20 +int aarch64_gdb_get_sme_reg(CPUState *cs, GByteArray *buf, int reg) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + switch (reg) { + case 0: /* svg register */ + { + int vq =3D 0; + if (FIELD_EX64(env->svcr, SVCR, SM)) { + vq =3D sve_vqm1_for_el_sm(env, arm_current_el(env), + FIELD_EX64(env->svcr, SVCR, SM)) + 1; + } + /* svg =3D vector granules (2 * vector quardwords) in streaming mo= de */ + return gdb_get_reg64(buf, vq * 2); + } + case 1: /* svcr register */ + return gdb_get_reg64(buf, env->svcr); + case 2: /* za register */ + { + int len =3D 0; + int vq =3D cpu->sme_max_vq; + int svl =3D vq * 16; + for (int i =3D 0; i < svl; i++) { + for (int q =3D 0; q < vq; q++) { + len +=3D gdb_get_reg128(buf, + env->za_state.za[i].d[q * 2 + 1], + env->za_state.za[i].d[q * 2]); + } + } + return len; + } + default: + /* gdbstub asked for something out of range */ + qemu_log_mask(LOG_UNIMP, "%s: out of range register %d", __func__,= reg); + break; + } + + return 0; +} + +int aarch64_gdb_set_sme_reg(CPUState *cs, uint8_t *buf, int reg) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + switch (reg) { + case 0: /* svg register */ + /* cannot set svg via gdbstub */ + return 8; + case 1: /* svcr register */ + aarch64_set_svcr(env, ldq_le_p(buf), + R_SVCR_SM_MASK | R_SVCR_ZA_MASK); + return 8; + case 2: /* za register */ + { + int len =3D 0; + int vq =3D cpu->sme_max_vq; + int svl =3D vq * 16; + for (int i =3D 0; i < svl; i++) { + for (int q =3D 0; q < vq; q++) { + if (target_big_endian()) { + env->za_state.za[i].d[q * 2 + 1] =3D ldq_p(buf); + buf +=3D 8; + env->za_state.za[i].d[q * 2] =3D ldq_p(buf); + } else{ + env->za_state.za[i].d[q * 2] =3D ldq_p(buf); + buf +=3D 8; + env->za_state.za[i].d[q * 2 + 1] =3D ldq_p(buf); + } + buf +=3D 8; + len +=3D 16; + } + } + return len; + } + default: + /* gdbstub asked for something out of range */ + break; + } + + return 0; +} + int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int reg) { ARMCPU *cpu =3D ARM_CPU(cs); @@ -413,6 +497,41 @@ GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *c= s, int base_reg) return &cpu->dyn_svereg_feature.desc; } =20 +GDBFeature *arm_gen_dynamic_smereg_feature(CPUState *cs, int base_reg) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + int vq =3D cpu->sme_max_vq; + int svl =3D vq * 16; + GDBFeatureBuilder builder; + int reg =3D 0; + + gdb_feature_builder_init(&builder, &cpu->dyn_smereg_feature.desc, + "org.gnu.gdb.aarch64.sme", "sme-registers.xml= ", + base_reg); + + + /* Create the sme_bv vector type. */ + gdb_feature_builder_append_tag( + &builder, "", + svl); + + /* Create the sme_bvv vector type. */ + gdb_feature_builder_append_tag( + &builder, "", + svl); + + /* Define the svg, svcr, and za registers. */ + + gdb_feature_builder_append_reg(&builder, "svg", 64, reg++, "int", NULL= ); + gdb_feature_builder_append_reg(&builder, "svcr", 64, reg++, "int", NUL= L); + gdb_feature_builder_append_reg(&builder, "za", svl * svl * 8, reg++, + "sme_bvv", NULL); + + gdb_feature_builder_end(&builder); + + return &cpu->dyn_smereg_feature.desc; +} + #ifdef CONFIG_USER_ONLY int aarch64_gdb_get_tag_ctl_reg(CPUState *cs, GByteArray *buf, int reg) { --=20 2.43.0 From nobody Sat Nov 15 00:45:06 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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This test simply sets and reads SME registers. Signed-off-by: Vacha Bhavsar Message-id: 20250909161012.2561593-4-vacha.bhavsar@oss.qualcomm.com [PMM: fixed various python formatting nits] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- configure | 6 ++ tests/tcg/aarch64/Makefile.target | 29 +++++++ tests/tcg/aarch64/gdbstub/test-sme.py | 117 ++++++++++++++++++++++++++ 3 files changed, 152 insertions(+) create mode 100644 tests/tcg/aarch64/gdbstub/test-sme.py diff --git a/configure b/configure index 274a7787642..9aea02cf6a2 100755 --- a/configure +++ b/configure @@ -1839,6 +1839,12 @@ for target in $target_list; do echo "GDB=3D$gdb_bin" >> $config_target_mak fi =20 + if test "${gdb_arches#*$arch}" !=3D "$gdb_arches" && version_ge $gdb= _version 14.1; then + echo "GDB_HAS_SME_TILES=3Dy" >> $config_target_mak + else + echo "GDB_HAS_SME_TILES=3Dn" >> $config_target_mak + fi + if test "${gdb_arches#*aarch64}" !=3D "$gdb_arches" && version_ge $g= db_version 15.1; then echo "GDB_HAS_MTE=3Dy" >> $config_target_mak fi diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile= .target index 16ddcf4f883..1755874beed 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -134,6 +134,35 @@ run-gdbstub-sve-ioctls: sve-ioctls =20 EXTRA_RUNS +=3D run-gdbstub-sysregs run-gdbstub-sve-ioctls =20 +ifneq ($(CROSS_AS_HAS_ARMV9_SME),) +# SME gdbstub tests + +run-gdbstub-sysregs-sme: sysregs + $(call run-test, $@, $(GDB_SCRIPT) \ + --gdb $(GDB) \ + --qemu $(QEMU) --qargs "$(QEMU_OPTS)" \ + --bin $< --test $(AARCH64_SRC)/gdbstub/test-sme.py \ + -- test_sme --gdb_basic_za_test, \ + basic gdbstub SME support) + +ifeq ($(GDB_HAS_SME_TILES),y) +run-gdbstub-sysregs-sme-tile-slice: sysregs + $(call run-test, $@, $(GDB_SCRIPT) \ + --gdb $(GDB) \ + --qemu $(QEMU) --qargs "$(QEMU_OPTS)" \ + --bin $< --test $(AARCH64_SRC)/gdbstub/test-sme.py \ + -- test_sme --gdb_tile_slice_test, \ + gdbstub SME ZA tile slice support) +else +run-gdbstub-sysregs-sme-tile-slice: sysregs + $(call skip-test,"gdbstub SME ZA tile slice support", \ + "selected gdb ($(GDB)) does not support SME ZA tile slices") +endif + +EXTRA_RUNS +=3D run-gdbstub-sysregs-sme run-gdbstub-sysregs-sme-tile-slice + +endif + ifeq ($(GDB_HAS_MTE),y) run-gdbstub-mte: mte-8 $(call run-test, $@, $(GDB_SCRIPT) \ diff --git a/tests/tcg/aarch64/gdbstub/test-sme.py b/tests/tcg/aarch64/gdbs= tub/test-sme.py new file mode 100644 index 00000000000..ec031896427 --- /dev/null +++ b/tests/tcg/aarch64/gdbstub/test-sme.py @@ -0,0 +1,117 @@ +# +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Test the SME registers are visible and changeable via gdbstub +# +# This is launched via tests/guest-debug/run-test.py +# + +import argparse +import gdb +from test_gdbstub import main, report + +MAGIC =3D 0x01020304 +BASIC_ZA_TEST =3D 0 +TILE_SLICE_TEST =3D 0 + + +def run_test(): + """Run the requested test(s) for SME ZA gdbstub support""" + + if BASIC_ZA_TEST: + run_basic_sme_za_gdbstub_support_test() + if TILE_SLICE_TEST: + run_basic_sme_za_tile_slice_gdbstub_support_test() + + +def run_basic_sme_za_gdbstub_support_test(): + """Test reads and writes to the SME ZA register at the byte level""" + + frame =3D gdb.selected_frame() + rname =3D "za" + za =3D frame.read_register(rname) + report(True, "Reading %s" % rname) + + # Writing to the ZA register, byte by byte. + for i in range(0, 16): + for j in range(0, 16): + cmd =3D "set $za[%d][%d] =3D 0x01" % (i, j) + gdb.execute(cmd) + report(True, "%s" % cmd) + + # Reading from the ZA register, byte by byte. + for i in range(0, 16): + for j in range(0, 16): + reg =3D "$za[%d][%d]" % (i, j) + v =3D gdb.parse_and_eval(reg) + report(str(v.type) =3D=3D "uint8_t", "size of %s" % (reg)) + report(v =3D=3D 0x1, "%s is 0x%x" % (reg, 0x1)) + + +def run_basic_sme_za_tile_slice_gdbstub_support_test(): + """Test reads and writes of SME ZA horizontal and vertical tile slices + + Test if SME ZA tile slices, both horizontal and vertical, + can be correctly read and written to. The sizes to test + are quadwords and doublewords. + """ + + sizes =3D {} + sizes["q"] =3D "uint128_t" + sizes["d"] =3D "uint64_t" + + # Accessing requested sizes of elements of ZA + for size in sizes: + + # Accessing various ZA tiles + for i in range(0, 4): + + # Accessing various horizontal slices for each ZA tile + for j in range(0, 4): + # Writing to various elements in each tile slice + for k in range(0, 4): + cmd =3D "set $za%dh%c%d[%d] =3D 0x%x" % (i, size, j, k= , MAGIC) + gdb.execute(cmd) + report(True, "%s" % cmd) + + # Reading from the written elements in each tile slice + for k in range(0, 4): + reg =3D "$za%dh%c%d[%d]" % (i, size, j, k) + v =3D gdb.parse_and_eval(reg) + report(str(v.type) =3D=3D sizes[size], "size of %s" % = (reg)) + report(v =3D=3D MAGIC, "%s is 0x%x" % (reg, MAGIC)) + + # Accessing various vertical slices for each ZA tile + for j in range(0, 4): + # Writing to various elements in each tile slice + for k in range(0, 4): + cmd =3D "set $za%dv%c%d[%d] =3D 0x%x" % (i, size, j, k= , MAGIC) + gdb.execute(cmd) + report(True, "%s" % cmd) + + # Reading from the written elements in each tile slice + for k in range(0, 4): + reg =3D "$za%dv%c%d[%d]" % (i, size, j, k) + v =3D gdb.parse_and_eval(reg) + report(str(v.type) =3D=3D sizes[size], "size of %s" % = (reg)) + report(v =3D=3D MAGIC, "%s is 0x%x" % (reg, MAGIC)) + + +parser =3D argparse.ArgumentParser(description=3D"A gdbstub test for SME s= upport") +parser.add_argument("--gdb_basic_za_test", + help=3D"Enable test for basic SME ZA support", + action=3D"store_true") +parser.add_argument("--gdb_tile_slice_test", + help=3D"Enable test for ZA tile slice support", + action=3D"store_true") +args =3D parser.parse_args() + +if args.gdb_basic_za_test: + BASIC_ZA_TEST =3D 1 +if args.gdb_tile_slice_test: + TILE_SLICE_TEST =3D 1 + +main(run_test, expected_arch=3D"aarch64") --=20 2.43.0 From nobody Sat Nov 15 00:45:06 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758046415; cv=none; d=zohomail.com; s=zohoarc; b=kuMWD2DhSDe1HrYPMTCEPGOwcMtK1Z9t/RVVDA6VFKPba2E4Du/8u++itNJuErspylhcH6iYDJZuTRdPE5x97D67PbI4fDD5R0y6HIj97+2YUHCNZyVI0lGh+cZMrz7uwOS/bbgPS/VMaTs0zofDhvBcD653+LjyWVHtwtcfdbo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758046415; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=seP0xrEvNCnKjpsBJ955vCqpOKXP9VKXeAgomjXz8Bg=; b=j5X9sClMCg7/9/jFmzu4+hOfNpT93z1isxRxbxVy1BxUqR8FN85x62pij1h6DdM5un1h8rhsutukf+sqSi97EzfaS39Y4l+fSXuhZjhM+NDM7RneyvmryyEZvxclNhEwj3exQHYfQC8d4sIvQLDBQ6WuJ6KP6qcQOIdhjtzp2go= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758046415849849.5531927844239; Tue, 16 Sep 2025 11:13:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uya5i-0004MD-0Y; Tue, 16 Sep 2025 14:07:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uya4w-0003Ac-4X for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:06:59 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uya4k-0001dK-Mh for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:06:51 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-45ed646b656so49695745e9.3 for ; Tue, 16 Sep 2025 11:06:43 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3e760775880sm23033286f8f.2.2025.09.16.11.06.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 11:06:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758046002; x=1758650802; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=seP0xrEvNCnKjpsBJ955vCqpOKXP9VKXeAgomjXz8Bg=; b=p2xpZQ72YqwobVuaWPdSCkH8slU2Pj5g5cmq1Rj1yjCWuYuuwz5ui9LcW3aNuWDogl rj3PTrZZl4nQqJbtzhhQTE6fXPn8HHcXiR75Iz0/fciZCzVadOL3dxBg/n5TR8J21AYa iPYD3YjOS0oz3RIQSB5ZBuJSKPMIndOnHya41mdkb+ilPZ3Iq3zZ1+sGsV0g1M5vtaRz QnRO3Q+rffk5HWknuIo/VVPik0TCrMRqRsu6MQSEJ2N3yrlhMY1eBBja0mLoQnn4DNEj 3tSRq3THOETRXjHo6Z5nfeBhLxSDWQHqOw7m7YjryiAJ6w8M74fU0KsEshcdQLw4J+bU 0T1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758046002; x=1758650802; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=seP0xrEvNCnKjpsBJ955vCqpOKXP9VKXeAgomjXz8Bg=; b=i+k3FG7cMyvEl8BQuY5zJDjoBkqqSW4A8f/jBCxhQqszNfwSAG6w/zzoU23dhIy+Q4 9dLDyiYA8yytSwKyV6loK+DJSlgQ8oJUIMI/WYDSCBbgwp5ejGo0U0uyRn8O0+7o+MRx stlxuzwWlbZgONBsnSEWlNqrs/VFDXoL5ZnP8ZGvtN1dAKWOJKadr8eBE/jg2R+Kc3gL J6AfIZXQWHd/JtnWCWJSwC6GkYt+ZnfZmIAeFdmW+918+MyOOUk+AofBgAxkyeDOrjh7 k+jWackTEa/JNgjNMUrSqubu3k0DVkNeOWeveSKEZ/8xVzOl0iLJbIM0M9jp/4uuPgWL e0Ig== X-Gm-Message-State: AOJu0Yybnto1S4lerDyvohoASbbz1Jnp3mr1Jx8pZ/OOF6PvcMdoABqR q2OoOX6l/6wlxMQbW0SWTysk75dcwsZSEXOKo3AJ64Eri39WMl/fyx8p/LXnBmlUqxYHuimluSh xbDPb X-Gm-Gg: ASbGnctG4ZVzBycXe+XuCYng2pMdHj0Akk13y0EWRhohrZikAB4jwbwZ+scycHOSBQu bsL1XGUcWSGB4cXO46iH4DrJ3ft+vvExUgT1jbGGbt5VePJRyrgpdJ1y6/wML87tAh56nJcey41 Ff50XPkLAwDtd0M+sbLlgm45raU5BtIBS7YRzsXboxSEDatM9kr3TUZ2XpG98QwhWeyYzkxqtwo tzHJyzGIyAJXDX0Y2RNYaxfkGqqM9swXb0bE2Ve3UaE7hPuVJJ5C+0REwGbc2nZ46wSPVOVu5dE WJcXyU75X71K615qNcq5L54WntRI/1KICUlCr4XurWSyNJEtQMa2q8PWNjZ/WbNTAXSMD+DnLE9 r6dIe9PIYnxwWzs2YNoJNVw92UL6S X-Google-Smtp-Source: AGHT+IFdBk1x/+6Goql+jZuEF7SparSqo6EV6b+3ga04pRrN0C0ZqqPkjreu4Wzihf5wTbUvK6tSbw== X-Received: by 2002:adf:ee46:0:b0:3ec:4e41:fd86 with SMTP id ffacd0b85a97d-3ec4e41ff5fmr3147507f8f.50.1758046002136; Tue, 16 Sep 2025 11:06:42 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/36] hw/arm/smmu-common: Check SMMU has PCIe Root Complex association Date: Tue, 16 Sep 2025 19:05:59 +0100 Message-ID: <20250916180611.1481266-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916180611.1481266-1-peter.maydell@linaro.org> References: <20250916180611.1481266-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758046416672116600 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum We only allow default PCIe Root Complex(pcie.0) or pxb-pcie based extra root complexes to be associated with SMMU. Although this change does not affect functionality at present, it is required when we add support for user-creatable SMMUv3 devices in future patches. Note: Added a specific check to identify pxb-pcie to avoid matching pxb-cxl host bridges, which are also of type PCI_HOST_BRIDGE. This restriction can be relaxed once support for CXL devices on arm/virt is added and validated with SMMUv3. Reviewed-by: Jonathan Cameron Reviewed-by: Eric Auger Tested-by: Nathan Chen Tested-by: Eric Auger Reviewed-by: Nicolin Chen Tested-by: Nicolin Chen Signed-off-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Reviewed-by: Donald Dutile Message-id: 20250829082543.7680-2-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- include/hw/pci/pci_bridge.h | 1 + hw/arm/smmu-common.c | 31 ++++++++++++++++++++++++++--- hw/pci-bridge/pci_expander_bridge.c | 1 - 3 files changed, 29 insertions(+), 4 deletions(-) diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h index 8cdacbc4e16..a055fd8d321 100644 --- a/include/hw/pci/pci_bridge.h +++ b/include/hw/pci/pci_bridge.h @@ -104,6 +104,7 @@ typedef struct PXBPCIEDev { PXBDev parent_obj; } PXBPCIEDev; =20 +#define TYPE_PXB_PCIE_BUS "pxb-pcie-bus" #define TYPE_PXB_CXL_BUS "pxb-cxl-bus" #define TYPE_PXB_DEV "pxb" OBJECT_DECLARE_SIMPLE_TYPE(PXBDev, PXB_DEV) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 0dcaf2f5897..7f64ea48d03 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -20,6 +20,7 @@ #include "trace.h" #include "exec/target_page.h" #include "hw/core/cpu.h" +#include "hw/pci/pci_bridge.h" #include "hw/qdev-properties.h" #include "qapi/error.h" #include "qemu/jhash.h" @@ -925,6 +926,7 @@ static void smmu_base_realize(DeviceState *dev, Error *= *errp) { SMMUState *s =3D ARM_SMMU(dev); SMMUBaseClass *sbc =3D ARM_SMMU_GET_CLASS(dev); + PCIBus *pci_bus =3D s->primary_bus; Error *local_err =3D NULL; =20 sbc->parent_realize(dev, &local_err); @@ -937,11 +939,34 @@ static void smmu_base_realize(DeviceState *dev, Error= **errp) g_free, g_free); s->smmu_pcibus_by_busptr =3D g_hash_table_new(NULL, NULL); =20 - if (s->primary_bus) { - pci_setup_iommu(s->primary_bus, &smmu_ops, s); - } else { + if (!pci_bus) { error_setg(errp, "SMMU is not attached to any PCI bus!"); + return; } + + /* + * We only allow default PCIe Root Complex(pcie.0) or pxb-pcie based e= xtra + * root complexes to be associated with SMMU. + */ + if (pci_bus_is_express(pci_bus) && pci_bus_is_root(pci_bus) && + object_dynamic_cast(OBJECT(pci_bus)->parent, TYPE_PCI_HOST_BRIDGE)= ) { + /* + * This condition matches either the default pcie.0, pxb-pcie, or + * pxb-cxl. For both pxb-pcie and pxb-cxl, parent_dev will be set. + * Currently, we don't allow pxb-cxl as it requires further + * verification. Therefore, make sure this is indeed pxb-pcie. + */ + if (pci_bus->parent_dev) { + if (!object_dynamic_cast(OBJECT(pci_bus), TYPE_PXB_PCIE_BUS)) { + goto out_err; + } + } + pci_setup_iommu(pci_bus, &smmu_ops, s); + return; + } +out_err: + error_setg(errp, "SMMU should be attached to a default PCIe root compl= ex" + "(pcie.0) or a pxb-pcie based root complex"); } =20 /* diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expand= er_bridge.c index 3a29dfefc2c..1bcceddbc4d 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -34,7 +34,6 @@ typedef struct PXBBus PXBBus; DECLARE_INSTANCE_CHECKER(PXBBus, PXB_BUS, TYPE_PXB_BUS) =20 -#define TYPE_PXB_PCIE_BUS "pxb-pcie-bus" DECLARE_INSTANCE_CHECKER(PXBBus, PXB_PCIE_BUS, TYPE_PXB_PCIE_BUS) =20 --=20 2.43.0 From nobody Sat Nov 15 00:45:06 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758046473; cv=none; d=zohomail.com; s=zohoarc; b=gX6/Tk4UzPyHJx3oA810Zm38aGOrD89A9VBCfl7WUtjGY6KCrA5dz2GGVaeTneDFwj0ji+bXANgRkmefGnpoa9LYrTMOozLOb40BxTc552LontwvyAQ8P6dxui8xz/ilXoe/fhLc99oo9TYvoq/Lo/xaQDKNNfVt7/Je4tuhDvw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758046473; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=rC+TMiYJKUB8eByBDe713xQWhD5QH0p+dyLech7y7/s=; b=Lk9f6+Tkv6YeqWiXn+5af5W51jrLC7ebPe/jRc+MCrfJMfE6P1j53oX+5nK5HEWX7vW1oT6EW4cZ0eh4CHVxzxr8ACJtJte6VHLpLaja6ef3dvPaVbTKmaMPBEJNM8jpO2KYNfu2eqQv5+ko8+s8wHJ+mzjWCs2TvVHLn6BKToA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758046473752382.22967263235364; Tue, 16 Sep 2025 11:14:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uya5Q-0003ZU-Nc; Tue, 16 Sep 2025 14:07:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uya4w-0003Af-5e for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:06:59 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uya4n-0001da-Vf for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:06:55 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-45f29dd8490so28414005e9.1 for ; Tue, 16 Sep 2025 11:06:44 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3e760775880sm23033286f8f.2.2025.09.16.11.06.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 11:06:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758046003; x=1758650803; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=rC+TMiYJKUB8eByBDe713xQWhD5QH0p+dyLech7y7/s=; b=vS46SeO3D8V8CGJNfd1c1nac3zwnvleI+n6lb9xgZJAU7jpYmCVBfiaMnP03w7yRqp gLy+YwFGJ7dyZmGFCnWpnFYGbGSPnuUkj7vjchGYQQii8mClQPAp7lDnNlDdaU5t0Zv1 /KzvwDt4ADRDGaoB8xHxPCCjE8b/zTpEEBNVi4Nl96viaRqiCqz7Jw1IqMIdxG96op4N dtEyhacEm4ZD0OI2zYquzNTJphbaySM8Eou7bM4QdF+EEjeTnMFGfVxxsnUDPUp8YkNb v3/kbK6xYTy0Tav/+HegejdiMeZegGAADUZtJI9C1QJlerWBla3aE7KmvYH3O2bU3UiJ MmfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758046003; x=1758650803; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rC+TMiYJKUB8eByBDe713xQWhD5QH0p+dyLech7y7/s=; b=LonBfXdb0S0HLfkc7JEUzjqCqIKC6urYKRnwnGcroJBGTWQUWpXtFoL5T16N8nq8Hm jRtTJ3apMtx3ydjuQxFi8a3+QcMazbIyEvLzKWjDjB6ecIFygrHh1CYr24KPz7XQKV0n 6VbCIIZODVZk0CgcTjOnFBQcH64l9KGZXaxQbOoTDp6w1CtO6o0VnFW8duYAKsHdJ0R7 j+/RpdrUa7yZbzuwILnOzOY/LVPsDIjfRZLP6Eq4/FIS5dAa9glTbook6JsPvOtOkBu9 mcHwK9JqaWdAhMWxX8MhctUB+MFUfCtvUxuFA42EcZAUMRPWfHpvXmUB1eNDB0vxq9pn LcvQ== X-Gm-Message-State: AOJu0Yznwzj2JWFHzXHpPpBYA617qdXuBLqxEbQ26iIAAmJVIsWzAqZ5 CI7mQb2LU3Jv/RSeeUL2etqSOlGBTewQLTcg59srcXwyqj98n3KqfEitzDJHMFn16thS3IDBVwU 5vxF2 X-Gm-Gg: ASbGncuLRfuHF7VFOhTFd52zrTsP9suh7u+GaRRdGYH2OyHGGNTHQUQFv/Wqfe4wL24 j8aPvJ9ZXd90V31c3X7OLh4KJU7cTsVPa8QEPwQCFXuTGXr27qo/pWrJ7CRnvIKRuO4f9t9KdOO Tsm554ej7HshPwiVgF3m0eB73gRd1wfQu/g7ZOW8L9yTKU2Q29lxLJjKjNiPi+m0RV1n0OQZDfv q9oHX3je/cGGJyb6qyoPI+t8txjTJVBWbDak4/PJuWEltHYz+GPg7V04WdSj9teGs9aeJLvEiGy 1GUvRi1B7EfE4t8CrWyuoH0tvq3P3+V4yJW4U6rJMqpQiDBD+5flmv6hb0oZC7I1iJeYSB9N12Z kYWK6KP1neKfISWXZOCPP8k8N+xiC X-Google-Smtp-Source: AGHT+IFiHiSHrhJ/LurtnXw9VUVCihYc6dyN2uSUgYqmP1qQ5QtHbhuiYrrttXjQHpQWjYLIBxrZRg== X-Received: by 2002:a7b:cd8f:0:b0:45b:47e1:ef67 with SMTP id 5b1f17b1804b1-45f212081abmr110670735e9.34.1758046003152; Tue, 16 Sep 2025 11:06:43 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/36] hw/arm/virt-acpi-build: Re-arrange SMMUv3 IORT build Date: Tue, 16 Sep 2025 19:06:00 +0100 Message-ID: <20250916180611.1481266-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916180611.1481266-1-peter.maydell@linaro.org> References: <20250916180611.1481266-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758046475621116600 From: Shameer Kolothum Introduce a new struct AcpiIortSMMUv3Dev to hold all the information required for SMMUv3 IORT node and use that for populating the node. The current machine wide SMMUv3 is named as legacy SMMUv3 as we will soon add support for user-creatable SMMUv3 devices. These changes will be useful to have common code paths when we add that support. Tested-by: Nathan Chen Reviewed-by: Nicolin Chen Reviewed-by: Jonathan Cameron Reviewed-by: Eric Auger Tested-by: Eric Auger Tested-by: Nicolin Chen Signed-off-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Reviewed-by: Donald Dutile Message-id: 20250829082543.7680-3-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- include/hw/arm/virt.h | 1 + hw/arm/virt-acpi-build.c | 137 ++++++++++++++++++++++++++------------- hw/arm/virt.c | 1 + 3 files changed, 94 insertions(+), 45 deletions(-) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 365a28b082c..ea2cff05b02 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -179,6 +179,7 @@ struct VirtMachineState { char *oem_table_id; bool ns_el2_virt_timer_irq; CXLState cxl_devices_state; + bool legacy_smmuv3_present; }; =20 #define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index b01fc4f8ef0..bef4fabe56f 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -305,29 +305,65 @@ static int iort_idmap_compare(gconstpointer a, gconst= pointer b) return idmap_a->input_base - idmap_b->input_base; } =20 +typedef struct AcpiIortSMMUv3Dev { + int irq; + hwaddr base; + GArray *rc_smmu_idmaps; + /* Offset of the SMMUv3 IORT Node relative to the start of the IORT */ + size_t offset; +} AcpiIortSMMUv3Dev; + +/* + * Populate the struct AcpiIortSMMUv3Dev for the legacy SMMUv3 and + * return the total number of associated idmaps. + */ +static int populate_smmuv3_legacy_dev(GArray *sdev_blob) +{ + VirtMachineState *vms =3D VIRT_MACHINE(qdev_get_machine()); + AcpiIortSMMUv3Dev sdev; + + sdev.rc_smmu_idmaps =3D g_array_new(false, true, sizeof(AcpiIortIdMapp= ing)); + object_child_foreach_recursive(object_get_root(), iort_host_bridges, + sdev.rc_smmu_idmaps); + /* + * There can be only one legacy SMMUv3("iommu=3Dsmmuv3") as it is a ma= chine + * wide one. Since it may cover multiple PCIe RCs(based on "bypass_iom= mu" + * property), may have multiple SMMUv3 idmaps. Sort it by input_base. + */ + g_array_sort(sdev.rc_smmu_idmaps, iort_idmap_compare); + + sdev.base =3D vms->memmap[VIRT_SMMU].base; + sdev.irq =3D vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; + g_array_append_val(sdev_blob, sdev); + return sdev.rc_smmu_idmaps->len; +} + /* Compute ID ranges (RIDs) from RC that are directed to the ITS Group nod= e */ -static void create_rc_its_idmaps(GArray *its_idmaps, GArray *smmu_idmaps) +static void create_rc_its_idmaps(GArray *its_idmaps, GArray *smmuv3_devs) { AcpiIortIdMapping *idmap; AcpiIortIdMapping next_range =3D {0}; + AcpiIortSMMUv3Dev *sdev; =20 - /* - * Based on the RID ranges that are directed to the SMMU, determine the - * bypassed RID ranges, i.e., the ones that are directed to the ITS Gr= oup - * node and do not pass through the SMMU, by subtracting the SMMU-bound - * ranges from the full RID range (0x0000=E2=80=930xFFFF). - */ - for (int i =3D 0; i < smmu_idmaps->len; i++) { - idmap =3D &g_array_index(smmu_idmaps, AcpiIortIdMapping, i); + for (int i =3D 0; i < smmuv3_devs->len; i++) { + sdev =3D &g_array_index(smmuv3_devs, AcpiIortSMMUv3Dev, i); + /* + * Based on the RID ranges that are directed to the SMMU, determin= e the + * bypassed RID ranges, i.e., the ones that are directed to the ITS + * Group node and do not pass through the SMMU, by subtracting the + * SMMU-bound ranges from the full RID range (0x0000=E2=80=930xFFF= F). + */ + for (int j =3D 0; j < sdev->rc_smmu_idmaps->len; j++) { + idmap =3D &g_array_index(sdev->rc_smmu_idmaps, AcpiIortIdMappi= ng, j); =20 - if (next_range.input_base < idmap->input_base) { - next_range.id_count =3D idmap->input_base - next_range.input_b= ase; - g_array_append_val(its_idmaps, next_range); + if (next_range.input_base < idmap->input_base) { + next_range.id_count =3D idmap->input_base - next_range.inp= ut_base; + g_array_append_val(its_idmaps, next_range); + } + + next_range.input_base =3D idmap->input_base + idmap->id_count; } - - next_range.input_base =3D idmap->input_base + idmap->id_count; } - /* * Append the last RC -> ITS ID mapping. * @@ -341,7 +377,6 @@ static void create_rc_its_idmaps(GArray *its_idmaps, GA= rray *smmu_idmaps) } } =20 - /* * Input Output Remapping Table (IORT) * Conforms to "IO Remapping Table System Software on ARM Platforms", @@ -351,9 +386,12 @@ static void build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) { int i, nb_nodes, rc_mapping_count; - size_t node_size, smmu_offset =3D 0; + AcpiIortSMMUv3Dev *sdev; + size_t node_size; + int num_smmus =3D 0; uint32_t id =3D 0; - GArray *rc_smmu_idmaps =3D g_array_new(false, true, sizeof(AcpiIortIdM= apping)); + int rc_smmu_idmaps_len =3D 0; + GArray *smmuv3_devs =3D g_array_new(false, true, sizeof(AcpiIortSMMUv3= Dev)); GArray *rc_its_idmaps =3D g_array_new(false, true, sizeof(AcpiIortIdMa= pping)); =20 AcpiTable table =3D { .sig =3D "IORT", .rev =3D 3, .oem_id =3D vms->oe= m_id, @@ -361,22 +399,21 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) /* Table 2 The IORT */ acpi_table_begin(&table, table_data); =20 - if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3) { - object_child_foreach_recursive(object_get_root(), - iort_host_bridges, rc_smmu_idmaps); + if (vms->legacy_smmuv3_present) { + rc_smmu_idmaps_len =3D populate_smmuv3_legacy_dev(smmuv3_devs); + } =20 - /* Sort the smmu idmap by input_base */ - g_array_sort(rc_smmu_idmaps, iort_idmap_compare); - - nb_nodes =3D 2; /* RC and SMMUv3 */ - rc_mapping_count =3D rc_smmu_idmaps->len; + num_smmus =3D smmuv3_devs->len; + if (num_smmus) { + nb_nodes =3D num_smmus + 1; /* RC and SMMUv3 */ + rc_mapping_count =3D rc_smmu_idmaps_len; =20 if (vms->its) { /* * Knowing the ID ranges from the RC to the SMMU, it's possibl= e to * determine the ID ranges from RC that go directly to ITS. */ - create_rc_its_idmaps(rc_its_idmaps, rc_smmu_idmaps); + create_rc_its_idmaps(rc_its_idmaps, smmuv3_devs); =20 nb_nodes++; /* ITS */ rc_mapping_count +=3D rc_its_idmaps->len; @@ -411,9 +448,10 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vir= tMachineState *vms) build_append_int_noprefix(table_data, 0 /* MADT translation_id */,= 4); } =20 - if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3) { - int irq =3D vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; + for (i =3D 0; i < num_smmus; i++) { + sdev =3D &g_array_index(smmuv3_devs, AcpiIortSMMUv3Dev, i); int smmu_mapping_count, offset_to_id_array; + int irq =3D sdev->irq; =20 if (vms->its) { smmu_mapping_count =3D 1; /* ITS Group node */ @@ -422,7 +460,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) smmu_mapping_count =3D 0; /* No ID mappings */ offset_to_id_array =3D 0; /* No ID mappings array */ } - smmu_offset =3D table_data->len - table.table_offset; + sdev->offset =3D table_data->len - table.table_offset; /* Table 9 SMMUv3 Format */ build_append_int_noprefix(table_data, 4 /* SMMUv3 */, 1); /* Type = */ node_size =3D SMMU_V3_ENTRY_SIZE + @@ -435,7 +473,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) /* Reference to ID Array */ build_append_int_noprefix(table_data, offset_to_id_array, 4); /* Base address */ - build_append_int_noprefix(table_data, vms->memmap[VIRT_SMMU].base,= 8); + build_append_int_noprefix(table_data, sdev->base, 8); /* Flags */ build_append_int_noprefix(table_data, 1 /* COHACC Override */, 4); build_append_int_noprefix(table_data, 0, 4); /* Reserved */ @@ -486,21 +524,26 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) build_append_int_noprefix(table_data, 0, 3); /* Reserved */ =20 /* Output Reference */ - if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3) { + if (num_smmus) { AcpiIortIdMapping *range; =20 - /* - * Map RIDs (input) from RC to SMMUv3 nodes: RC -> SMMUv3. - * - * N.B.: The mapping from SMMUv3 to ITS Group node (SMMUv3 -> ITS)= is - * defined in the SMMUv3 table, where all SMMUv3 IDs are mapped to= the - * ITS Group node, if ITS is available. - */ - for (i =3D 0; i < rc_smmu_idmaps->len; i++) { - range =3D &g_array_index(rc_smmu_idmaps, AcpiIortIdMapping, i); - /* Output IORT node is the SMMUv3 node. */ - build_iort_id_mapping(table_data, range->input_base, - range->id_count, smmu_offset); + for (i =3D 0; i < num_smmus; i++) { + sdev =3D &g_array_index(smmuv3_devs, AcpiIortSMMUv3Dev, i); + + /* + * Map RIDs (input) from RC to SMMUv3 nodes: RC -> SMMUv3. + * + * N.B.: The mapping from SMMUv3 to ITS Group node (SMMUv3 -> = ITS) + * is defined in the SMMUv3 table, where all SMMUv3 IDs are ma= pped + * to the ITS Group node, if ITS is available. + */ + for (int j =3D 0; j < sdev->rc_smmu_idmaps->len; j++) { + range =3D &g_array_index(sdev->rc_smmu_idmaps, + AcpiIortIdMapping, j); + /* Output IORT node is the SMMUv3 node. */ + build_iort_id_mapping(table_data, range->input_base, + range->id_count, sdev->offset); + } } =20 if (vms->its) { @@ -525,8 +568,12 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vir= tMachineState *vms) } =20 acpi_table_end(linker, &table); - g_array_free(rc_smmu_idmaps, true); g_array_free(rc_its_idmaps, true); + for (i =3D 0; i < num_smmus; i++) { + sdev =3D &g_array_index(smmuv3_devs, AcpiIortSMMUv3Dev, i); + g_array_free(sdev->rc_smmu_idmaps, true); + } + g_array_free(smmuv3_devs, true); } =20 /* diff --git a/hw/arm/virt.c b/hw/arm/virt.c index e5c4142e822..16a1ac3c2d9 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1651,6 +1651,7 @@ static void create_pcie(VirtMachineState *vms) qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map", 0x0, vms->iommu_phandle, 0x0, 0x100= 00); } + vms->legacy_smmuv3_present =3D true; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3e760775880sm23033286f8f.2.2025.09.16.11.06.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 11:06:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758046004; x=1758650804; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=5YcFNgyROtM6LDiO+7+a0MCY/01CFYioeqjwFM/jXlQ=; b=GSvv1hQQnOR2B9/CisNNFnYYz6EGVYfwuSKYOBxeN9EImT2BYbZH8g5Hvat58SBqiU 9I/QQ5IyI2JwH5T1xNTc5AYO176zis9zijWJAWLIywx2+zejaqtjdBK+X02FsSREk8/m KMdFwYonjKN5uLxZWcaCaAQcPvz1yWjBzffZftEZkGz5nPJktJaufXbyp98WTRwm9lBa CMNkI0rWglndcq3Ozgj0RfOhPgXyJpVUDaby6XwYFlSh/uWPd8xPvLdl3AwthKyIwv9u 5iKmVBo4HcyRFvOn66d/wpFA/otpbQXfvVbp6zpvOv5jblCSfPMgT2D14oJzLlOLKhGz whYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758046004; x=1758650804; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5YcFNgyROtM6LDiO+7+a0MCY/01CFYioeqjwFM/jXlQ=; b=uahcZ62rw3P4dxktloOk7V6nTFJvUVDvP1D3pEIfAsA9y+pB3TSytRLdqSn2n71r7x P9+lkWGDt78I+mJaQcCTDLMU0GDkDu5d55d0BtWsUYdoqtrbspZLfARqGV3YiZ2/Zwr/ wbxXwfyXY/LCMQGYsHBuTULvOemwG+mD5OkyZlfSdo/eQ3rmeOzVTJFmOgKbUfAzksxT bDXJOcaNIVUqp10+ZrZL+NYRUHG1f8NkzNj9QVq+t7sWRJfk88o4PZPkeQ5tAY/DixHD NVCIZfqRdl+IVKj2B+p5ZXmmJkAUNTsw5Gx/sNNmNkH09u/Gzxuyef1S3K6MWWRi8HVX 9Miw== X-Gm-Message-State: AOJu0Yz7YEBbxDnmelK1EtFMUa/AZRdGtIxFK7r8yBprrXcdIaKCHBjv LZHqCOkn/UCK8JHwVrHzrQuetZxnQ2GSk9sQ5QmoOJPGaUIjBt3jN+hFS6fJF7m6aOk6aOdVCTY 8Sqyf X-Gm-Gg: ASbGncuHjiUSYKJS1du5902nZXvL/TEJBx3pOyGQBtxKtSHxVIE1P4U05+ODlXQ1bPc NT/RbOaTJn1sCBnlO73A0V+UWrPmaNPxKV8rglV5YqOG30aXp0uKn6Ipb0WFC9igIn1dK0hx1gK Tq6s3b7IVvjTNsVt3SoJDMj2GojgzuSLupJt7IqEfQxUm2D070TFxEs2jFSKNOpQ+i9ivNdpe8H q7Lu8mTHEX3jUSd9e2inISlkLlE86UBNII3KgYrIcf3aZcml8v30jtPhxEiT2HhcjlMAFHUyZUk v+45LYlBFdBpdIqjd7/exrPf2vUUa3EfD0ajPq/KDomcKr32MqJb9SYKrB71LzMKUZ+rGqV4B2V +iblEtGite1/NmZKQHZKUtnQR9IpN X-Google-Smtp-Source: AGHT+IFocP3qVImHygfvnonGl76zqfDSo6eaQxW1Uikh6fABTfgMOgweweinPxXU5aeQSqxcCzhvXg== X-Received: by 2002:a05:6000:2084:b0:3d3:b30:4cf2 with SMTP id ffacd0b85a97d-3ec9ec52f99mr2751336f8f.19.1758046004359; Tue, 16 Sep 2025 11:06:44 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/36] hw/arm/virt-acpi-build: Update IORT for multiple smmuv3 devices Date: Tue, 16 Sep 2025 19:06:01 +0100 Message-ID: <20250916180611.1481266-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916180611.1481266-1-peter.maydell@linaro.org> References: <20250916180611.1481266-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758046307180116600 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum With the soon to be introduced user-creatable SMMUv3 devices for virt, it is possible to have multiple SMMUv3 devices associated with different PCIe root complexes. Update IORT nodes accordingly. An example IORT Id mappings for a Qemu virt machine with two PCIe Root Complexes each assocaited with a SMMUv3 will be something like below, -device arm-smmuv3,primary-bus=3Dpcie.0,id=3Dsmmuv3.0 -device arm-smmuv3,primary-bus=3Dpcie.1,id=3Dsmmuv3.1 ... +--------------------+ +--------------------+ | Root Complex 0 | | Root Complex 1 | | | | | | Requestor IDs | | Requestor IDs | | 0x0000 - 0x00FF | | 0x0100 - 0x01FF | +---------+----------+ +---------+----------+ | | | | | Stream ID Mapping | v v +--------------------+ +--------------------+ | SMMUv3 Node 0 | | SMMUv3 Node 1 | | | | | | Stream IDs 0x0000- | | Stream IDs 0x0100- | | 0x00FF mapped from | | 0x01FF mapped from | | RC0 Requestor IDs | | RC1 Requestor IDs | +--------------------+ +--------------------+ | | | | +----------------+---------------+ | |Device ID Mapping v +----------------------------+ | ITS Node 0 | | | | Device IDs: | | 0x0000 - 0x00FF (from RC0) | | 0x0100 - 0x01FF (from RC1) | | 0x0200 - 0xFFFF (No SMMU) | +----------------------------+ Tested-by: Nathan Chen Reviewed-by: Nicolin Chen Reviewed-by: Jonathan Cameron Reviewed-by: Eric Auger Tested-by: Eric Auger Tested-by: Nicolin Chen Signed-off-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Reviewed-by: Donald Dutile Message-id: 20250829082543.7680-4-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/virt-acpi-build.c | 64 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index bef4fabe56f..96830f7c4ec 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -45,6 +45,7 @@ #include "hw/acpi/generic_event_device.h" #include "hw/acpi/tpm.h" #include "hw/acpi/hmat.h" +#include "hw/arm/smmuv3.h" #include "hw/cxl/cxl.h" #include "hw/pci/pcie_host.h" #include "hw/pci/pci.h" @@ -338,6 +339,67 @@ static int populate_smmuv3_legacy_dev(GArray *sdev_blo= b) return sdev.rc_smmu_idmaps->len; } =20 +static int smmuv3_dev_idmap_compare(gconstpointer a, gconstpointer b) +{ + AcpiIortSMMUv3Dev *sdev_a =3D (AcpiIortSMMUv3Dev *)a; + AcpiIortSMMUv3Dev *sdev_b =3D (AcpiIortSMMUv3Dev *)b; + AcpiIortIdMapping *map_a =3D &g_array_index(sdev_a->rc_smmu_idmaps, + AcpiIortIdMapping, 0); + AcpiIortIdMapping *map_b =3D &g_array_index(sdev_b->rc_smmu_idmaps, + AcpiIortIdMapping, 0); + return map_a->input_base - map_b->input_base; +} + +static int iort_smmuv3_devices(Object *obj, void *opaque) +{ + VirtMachineState *vms =3D VIRT_MACHINE(qdev_get_machine()); + GArray *sdev_blob =3D opaque; + AcpiIortIdMapping idmap; + PlatformBusDevice *pbus; + AcpiIortSMMUv3Dev sdev; + int min_bus, max_bus; + SysBusDevice *sbdev; + PCIBus *bus; + + if (!object_dynamic_cast(obj, TYPE_ARM_SMMUV3)) { + return 0; + } + + bus =3D PCI_BUS(object_property_get_link(obj, "primary-bus", &error_ab= ort)); + pbus =3D PLATFORM_BUS_DEVICE(vms->platform_bus_dev); + sbdev =3D SYS_BUS_DEVICE(obj); + sdev.base =3D platform_bus_get_mmio_addr(pbus, sbdev, 0); + sdev.base +=3D vms->memmap[VIRT_PLATFORM_BUS].base; + sdev.irq =3D platform_bus_get_irqn(pbus, sbdev, 0); + sdev.irq +=3D vms->irqmap[VIRT_PLATFORM_BUS]; + sdev.irq +=3D ARM_SPI_BASE; + + pci_bus_range(bus, &min_bus, &max_bus); + sdev.rc_smmu_idmaps =3D g_array_new(false, true, sizeof(AcpiIortIdMapp= ing)); + idmap.input_base =3D min_bus << 8, + idmap.id_count =3D (max_bus - min_bus + 1) << 8, + g_array_append_val(sdev.rc_smmu_idmaps, idmap); + g_array_append_val(sdev_blob, sdev); + return 0; +} + +/* + * Populate the struct AcpiIortSMMUv3Dev for all SMMUv3 devices and + * return the total number of idmaps. + */ +static int populate_smmuv3_dev(GArray *sdev_blob) +{ + object_child_foreach_recursive(object_get_root(), + iort_smmuv3_devices, sdev_blob); + /* Sort the smmuv3 devices(if any) by smmu idmap input_base */ + g_array_sort(sdev_blob, smmuv3_dev_idmap_compare); + /* + * Since each SMMUv3 dev is assocaited with specific host bridge, + * total number of idmaps equals to total number of smmuv3 devices. + */ + return sdev_blob->len; +} + /* Compute ID ranges (RIDs) from RC that are directed to the ITS Group nod= e */ static void create_rc_its_idmaps(GArray *its_idmaps, GArray *smmuv3_devs) { @@ -401,6 +463,8 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) =20 if (vms->legacy_smmuv3_present) { rc_smmu_idmaps_len =3D populate_smmuv3_legacy_dev(smmuv3_devs); + } else { + rc_smmu_idmaps_len =3D populate_smmuv3_dev(smmuv3_devs); } =20 num_smmus =3D smmuv3_devs->len; --=20 2.43.0 From nobody Sat Nov 15 00:45:06 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758046345; cv=none; d=zohomail.com; s=zohoarc; b=J4k3qxAifdC4ritUfTcD02fX1lxHW3j+OSI+AYrERJ01L8nTA+mEv35uC9XOAKaChHnfTTa1ibBMBt+b3XFf96bo4OR+snqo0rB5EtJhJpHaB+12sbG5lClIgVQWds5cteIVOqhd69GOkih6luPlAViHYO7e8FIG3Qdb91GXU8o= ARC-Message-Signature: i=1; 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This will be useful when we add support for user-creatable smmuv3 device. Reviewed-by: Nicolin Chen Reviewed-by: Eric Auger Tested-by: Nathan Chen Reviewed-by: Jonathan Cameron Tested-by: Eric Auger Tested-by: Nicolin Chen Signed-off-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Reviewed-by: Donald Dutile Message-id: 20250829082543.7680-5-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/virt.c | 54 +++++++++++++++++++++++++++------------------------ 1 file changed, 29 insertions(+), 25 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 16a1ac3c2d9..bebe2d8cea9 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1444,19 +1444,43 @@ static void create_pcie_irq_map(const MachineState = *ms, 0x7 /* PCI irq */); } =20 +static void create_smmuv3_dt_bindings(const VirtMachineState *vms, hwaddr = base, + hwaddr size, int irq) +{ + char *node; + const char compat[] =3D "arm,smmu-v3"; + const char irq_names[] =3D "eventq\0priq\0cmdq-sync\0gerror"; + MachineState *ms =3D MACHINE(vms); + + node =3D g_strdup_printf("/smmuv3@%" PRIx64, base); + qemu_fdt_add_subnode(ms->fdt, node); + qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); + qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size); + + qemu_fdt_setprop_cells(ms->fdt, node, "interrupts", + GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, + GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, + GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, + GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); + + qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names, + sizeof(irq_names)); + + qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0); + qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); + qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); + g_free(node); +} + static void create_smmu(const VirtMachineState *vms, PCIBus *bus) { VirtMachineClass *vmc =3D VIRT_MACHINE_GET_CLASS(vms); - char *node; - const char compat[] =3D "arm,smmu-v3"; int irq =3D vms->irqmap[VIRT_SMMU]; int i; hwaddr base =3D vms->memmap[VIRT_SMMU].base; hwaddr size =3D vms->memmap[VIRT_SMMU].size; - const char irq_names[] =3D "eventq\0priq\0cmdq-sync\0gerror"; DeviceState *dev; - MachineState *ms =3D MACHINE(vms); =20 if (vms->iommu !=3D VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { return; @@ -1475,27 +1499,7 @@ static void create_smmu(const VirtMachineState *vms, sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, qdev_get_gpio_in(vms->gic, irq + i)); } - - node =3D g_strdup_printf("/smmuv3@%" PRIx64, base); - qemu_fdt_add_subnode(ms->fdt, node); - qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); - qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size); - - qemu_fdt_setprop_cells(ms->fdt, node, "interrupts", - GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, - GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, - GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, - GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); - - qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names, - sizeof(irq_names)); - - qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0); - - qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); - - qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); - g_free(node); + create_smmuv3_dt_bindings(vms, base, size, irq); } =20 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms) --=20 2.43.0 From nobody Sat Nov 15 00:45:06 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758046441; cv=none; d=zohomail.com; s=zohoarc; b=j3nO/KOo/hCxikG55Y76YA8e/D1Xb/TafsJ8un0JihBzev3GD6KTXSctwnse+dTfpARN3ke/F00VrhuTQbx0L5G+iXR5A9T55oWQEF+qCbYMHhUx2pyE6RwrfmUsm6lndVoDUkwsKJLi2POxkCmu3T90jentyA7c3URR+tT09ME= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3e760775880sm23033286f8f.2.2025.09.16.11.06.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 11:06:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758046007; x=1758650807; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=QJC90Z9Jna1Frj0HcvsOKEe9UH6moSfHJHHkk9hg+yo=; b=TA+ZtSf4tRL9WJ+3+raMkgpvqfV6Bu+UXUU525USzSZjb/xNAF3/wlvk4JPtdpoEqS T8VkT6hhHp9aIyc0T17wtNMv8lEvcgFhd2Zn1SRtpUmJKVXtOnv78pTZpMNjxjCYqJKz KcN6O95SUyas3b6vrgj/mszZovGljRoPMPEYQJcU4VCMhZjYknnttTyYGfRGAKPmbEwX tL4xoYZvypQlVlh2Aw6WKL2nQFRQ0OrXZgddNaQcawtDKaMdlxA60IbIFzsB7vExgKBY QwYjzAPz860LvTQF2QlEKpMfGGDxwGV4uUL8xZTMAR+pdPYQgVYgvLWFAsJSH8u7YjIR oJcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758046007; x=1758650807; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QJC90Z9Jna1Frj0HcvsOKEe9UH6moSfHJHHkk9hg+yo=; b=osY+1YNj5Z7um7ZTB0Onir4m9A2bZrpKmOyYOOGT4q47XruhHc2boeXW2pqU0zKrp8 X6dECBzPDekZC1c79McKynoHCIcPtXMx6SnKCqdp9fHCJQTwmqikWjUElGjixhuUMb3h 3277hu+dr7Pkhoq0iCSB+Je25zLk/w6O6zvTviPDi0qUecsWSkO6tnfOl8YrTO2/GOsE Qhpsd+WM2AeJG0gIM/jj7xO1jspbsmp8lIHSJBSopHMttW39+35Lm6bqLackApz9Kxzm W72NrX440ooJHbbwFNIPeHgEveMEh1j+SXJ4joju+8RXU+pTiEgC0FcaQ88z89nIOoWu AleA== X-Gm-Message-State: AOJu0Yy8vLb3BPuPxp35QGkYVj+btyagiy1Df791XGIrkB0pCSJK3c+7 g4s4uSMh7u2vc5KAsznb0MurRjyqTFyjaKtjBwh4LTNPxD1JfM/JO/sYaVuYn1Zu6esOk5+0ifh /OEL+ X-Gm-Gg: ASbGncsjIF2S19kxBcwc6ysyllZR8Zq4sUG/9jyljordYdjYoR/wQqM2w8ZOdSSwC3M lKJZkDpw7Nf/iq46s3NJE5fudZohyKWvjE2JA3Q/Vk2A6gvahEqGiDZyaebplToDILpUu7Xx2dH +c3WAQzjQJ0TIP7eahAKsKWVs3SMlIna89jDx8SGPk/jOj/zW9JDVD1/Pg9+W1+ffCtwr6U9mME COg75gZr1cowAKXWOQiR6U/hNSuDYAnclJHoqVRGMZ2CFxPbPI69dIDIr/JcSqLMYI06j38cR/U LS/K3pUwwOEHevKe01QyjVbA/bfd062qbJ1xZyeKxJTPJgwXYKN2zY1rUrV7BNPBnpYlopfT5HN GW0lrQXQA/83MyKKegEYzAt+su9mO X-Google-Smtp-Source: AGHT+IE7P2el+6TznladCGhlkoQyGMn+tDwscEdohPVr2RPJdGnqAogxRZGcxelBDTNh3ZuUA0qp8g== X-Received: by 2002:a05:600c:4685:b0:45c:b607:ea95 with SMTP id 5b1f17b1804b1-45f211e6054mr184892085e9.18.1758046006924; Tue, 16 Sep 2025 11:06:46 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/36] hw/arm/virt: Add an SMMU_IO_LEN macro Date: Tue, 16 Sep 2025 19:06:03 +0100 Message-ID: <20250916180611.1481266-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916180611.1481266-1-peter.maydell@linaro.org> References: <20250916180611.1481266-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758046442890116600 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen This is useful as the subsequent support for new SMMUv3 dev will also use the same. Signed-off-by: Nicolin Chen Reviewed-by: Donald Dutile Reviewed-by: Eric Auger Tested-by: Nathan Chen Reviewed-by: Jonathan Cameron Tested-by: Eric Auger Tested-by: Nicolin Chen Signed-off-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Reviewed-by: Nicolin Chen Message-id: 20250829082543.7680-6-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/virt.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index bebe2d8cea9..64b4dcf6071 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -151,6 +151,9 @@ static void arm_virt_compat_set(MachineClass *mc) #define LEGACY_RAMLIMIT_GB 255 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB) =20 +/* MMIO region size for SMMUv3 */ +#define SMMU_IO_LEN 0x20000 + /* Addresses and sizes of our components. * 0..128MB is space for a flash device so we can run bootrom code such as= UEFI. * 128MB..256MB is used for miscellaneous device I/O. @@ -182,7 +185,7 @@ static const MemMapEntry base_memmap[] =3D { [VIRT_FW_CFG] =3D { 0x09020000, 0x00000018 }, [VIRT_GPIO] =3D { 0x09030000, 0x00001000 }, [VIRT_UART1] =3D { 0x09040000, 0x00001000 }, - [VIRT_SMMU] =3D { 0x09050000, 0x00020000 }, + [VIRT_SMMU] =3D { 0x09050000, SMMU_IO_LEN }, [VIRT_PCDIMM_ACPI] =3D { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, [VIRT_ACPI_GED] =3D { 0x09080000, ACPI_GED_EVT_SEL_LEN }, [VIRT_NVDIMM_ACPI] =3D { 0x09090000, NVDIMM_ACPI_IO_LEN}, --=20 2.43.0 From nobody Sat Nov 15 00:45:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758046415; cv=none; d=zohomail.com; s=zohoarc; b=Ytm03fW+PYIuuoJSF8P7poHX0ovYASYcF/WqNWCi/ooXiVbHX83aa6+M+49icvHn3Sk73ZPh9RSHi2L7eNZ5JkQvDNap035qZowS12AhZTcVETcHNen/mgSSKopW5yD0ORjJa3PKLoOupJcoR2C87+qWiAA/pySmnhRbtHGXUWg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758046415; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=ubfc2PZj+oS1m5/ITApUfm2bX3aVbus3n9rVpILRrWE=; b=c/eg2KHYLc8qo0kdIOtiVk9dW2pKKBT+yC2ekMuBUU7cK0if7on1o0g0sZckGzssIqLQ0r0NEuujxy1iOufwMORUep58Laz7fN+gS7dCPZPGJLeSZvrkhH2gwGyrOeUwQvCatnIm5mcjxEQXQOmfs8HjbF37i7T0sgTt58Sk7+A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758046414994899.0571510045695; Tue, 16 Sep 2025 11:13:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uya7J-0006aY-GV; Tue, 16 Sep 2025 14:09:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uya58-0003Tx-TY for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:07:18 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uya4v-0001e4-Tx for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:07:04 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-45dfb8e986aso57691195e9.0 for ; Tue, 16 Sep 2025 11:06:49 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3e760775880sm23033286f8f.2.2025.09.16.11.06.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 11:06:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758046008; x=1758650808; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ubfc2PZj+oS1m5/ITApUfm2bX3aVbus3n9rVpILRrWE=; b=jvB/OlytC3Cd0Ypu3HNq+FQ7FvQjfIvSeBDqPl9tgfMxoxlKlCJhYzbK7kjCqZKNRz 5Ndq+ZjFwYQWchjswDlKkefv/nU3gnF6k0HI0TrAl36lLVkM49Q6tTs5PrqjScD4TPK4 i7QVA7/Pb8+JiENZFs6Bi/scgAnqYlyItIaYxys/2DMu6bbwYWaJs/wRydQxbrLrthSS +PVdaoiCyCCHcl6S+Ek+y6QNLmUqdmY0hC7Cg8n4IEvPRs8ccS57wM8n1QBdY2Sl/oYj 0aTLPdxEssaj5pZZ2mRgGzDPhAQpeYB31rt9Wz0LoZO79mYMIJJjfm79X4DJfo9aRnH3 nUjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758046008; x=1758650808; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ubfc2PZj+oS1m5/ITApUfm2bX3aVbus3n9rVpILRrWE=; b=Q0hn5IYU7qrYZJlzZHVFKzf1NgLtWHgt1DQKgZQ3bGJ2QLAXpomLYmoXIMVXBxKoFj Mjs8YKaqHP1Xhc962g/+ajpj/cUCOYavMYInGEqrQWZrZy3n8xo6VUFP2GrnvMY66w9j lL9SqZ568h8X3/OFN5xMwkoIaDjSrnfzZbfSfaHy9NHZptTP0KsOh1SuQbc+Gapv9qDL A0si5sEtYK8zruhiJD7Q//hADBbfsWj0EnzNUTZNOZX5Ha7whrH9Fapi9Z3V9CxAlmPw rOKHJi4hz1WMQwb8AGLDT8+cq7t26c4dwaEyTW/KTFTD4nqRX5vl0FanoCwQSpMr/bpf CZqw== X-Gm-Message-State: AOJu0YyHsW11nHbCgOpeWZYADi/ytZjP45KhVMlH1Ua9CbNPylFmoFI/ YHpnSeJURFNqYg9GfzHxsrX3KRPYPEvsHkCS4tO+aPQfGOAv16tUtZ0T+6JFu3/4csaGTZhId0g TQVDJ X-Gm-Gg: ASbGncvNIrEOOjFoTIUL9qAzl7BrZSpP72qcrgyHpAvjCkBkwEMxWAUlY2CQun/CQoV JIXcB9PEiyYyqJfO/W84D7PhBiaxHylfnXIpwo6SnERHhQ8LOkeBu5CeRMu+sBedXs0tLUsvey6 nDrxJMqBmh7k4q7pMe1HxXBmH4G3XI7Mt7rj0l5+zoI8JL6bO4uyXcs0R47PsKpYsLSobQxpqqN sOTGC5F3DfzO/8K7CkLK7cVGUULQpOPrUghqQPSulNg9hjlMg8sK9QfC2f7DnJgbwl5DDCBKnzJ YvW16M+CQk7nbUKAb3j0qiYhJZd4X6NAZWroI8Pvphcx4C1sPUNoLil6IC8uoZ7m72vFzstIy2U u9HawrS7owjf9Itz9YwtbB7tKv+6IZLGsKuf+ACY= X-Google-Smtp-Source: AGHT+IFApf8ohbI8uwk+/MEsz8A+1IubEnMXSZzTRs4tUjzWR4e0k0InydV3hI/MH4a9X+zVisgRuQ== X-Received: by 2002:a05:600c:1909:b0:45f:2c89:a873 with SMTP id 5b1f17b1804b1-45f2cbafa55mr63564115e9.35.1758046007948; Tue, 16 Sep 2025 11:06:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/36] hw/pci: Introduce pci_setup_iommu_per_bus() for per-bus IOMMU ops retrieval Date: Tue, 16 Sep 2025 19:06:04 +0100 Message-ID: <20250916180611.1481266-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916180611.1481266-1-peter.maydell@linaro.org> References: <20250916180611.1481266-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758046416740116600 From: Shameer Kolothum Currently, pci_setup_iommu() registers IOMMU ops for a given PCIBus. However, when retrieving IOMMU ops for a device using pci_device_get_iommu_bus_devfn(), the function checks the parent_dev and fetches IOMMU ops from the parent device, even if the current bus does not have any associated IOMMU ops. This behavior works for now because QEMU's IOMMU implementations are globally scoped, and host bridges rely on the bypass_iommu property to skip IOMMU translation when needed. However, this model will break with the soon to be introduced arm-smmuv3 device, which allows users to associate the IOMMU with a specific PCIe root complex (e.g., the default pcie.0 or a pxb-pcie root complex). For example, consider the following setup with multiple root complexes: -device arm-smmuv3,primary-bus=3Dpcie.0,id=3Dsmmuv3.0 \ ... -device pxb-pcie,id=3Dpcie.1,bus_nr=3D8,bus=3Dpcie.0 \ -device pcie-root-port,id=3Dpcie.port1,bus=3Dpcie.1 \ -device virtio-net-pci,bus=3Dpcie.port1 In Qemu, pxb-pcie acts as a special root complex whose parent is effectively the default root complex(pcie.0). Hence, though pcie.1 has no associated SMMUv3 as per above, pci_device_get_iommu_bus_devfn() will incorrectly return the IOMMU ops from pcie.0 due to the fallback via parent_dev. To fix this, introduce a new helper pci_setup_iommu_per_bus() that explicitly sets the new iommu_per_bus field in the PCIBus structure. This helper will be used in a subsequent patch that adds support for the new arm-smmuv3 device. Update pci_device_get_iommu_bus_devfn() to use iommu_per_bus when determining the correct IOMMU ops, ensuring accurate behavior for per-bus IOMMUs. Reviewed-by: Jonathan Cameron Reviewed-by: Eric Auger Tested-by: Nathan Chen Tested-by: Eric Auger Reviewed-by: Nicolin Chen Tested-by: Nicolin Chen Signed-off-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Reviewed-by: Donald Dutile Message-id: 20250829082543.7680-7-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- include/hw/pci/pci.h | 2 ++ include/hw/pci/pci_bus.h | 1 + hw/pci/pci.c | 31 +++++++++++++++++++++++++++++++ 3 files changed, 34 insertions(+) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 6b7d3ac8a36..6bccb25ac2f 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -773,6 +773,8 @@ int pci_iommu_unregister_iotlb_notifier(PCIDevice *dev,= uint32_t pasid, */ void pci_setup_iommu(PCIBus *bus, const PCIIOMMUOps *ops, void *opaque); =20 +void pci_setup_iommu_per_bus(PCIBus *bus, const PCIIOMMUOps *ops, void *op= aque); + pcibus_t pci_bar_address(PCIDevice *d, int reg, uint8_t type, pcibus_t size); =20 diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bus.h index 22613125462..c7384467888 100644 --- a/include/hw/pci/pci_bus.h +++ b/include/hw/pci/pci_bus.h @@ -35,6 +35,7 @@ struct PCIBus { enum PCIBusFlags flags; const PCIIOMMUOps *iommu_ops; void *iommu_opaque; + bool iommu_per_bus; uint8_t devfn_min; uint32_t slot_reserved_mask; pci_set_irq_fn set_irq; diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 297196b2421..c3df9d6656b 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2912,6 +2912,19 @@ static void pci_device_get_iommu_bus_devfn(PCIDevice= *dev, } } =20 + /* + * When multiple PCI Express Root Buses are defined using pxb-pcie, + * the IOMMU configuration may be specific to each root bus. Howev= er, + * pxb-pcie acts as a special root complex whose parent is effecti= vely + * the default root complex(pcie.0). Ensure that we retrieve the + * correct IOMMU ops(if any) in such cases. + */ + if (pci_bus_is_express(iommu_bus) && pci_bus_is_root(iommu_bus)) { + if (parent_bus->iommu_per_bus) { + break; + } + } + iommu_bus =3D parent_bus; } =20 @@ -3172,6 +3185,24 @@ void pci_setup_iommu(PCIBus *bus, const PCIIOMMUOps = *ops, void *opaque) bus->iommu_opaque =3D opaque; } =20 +/* + * Similar to pci_setup_iommu(), but sets iommu_per_bus to true, + * indicating that the IOMMU is specific to this bus. This is used by + * IOMMU implementations that are tied to a specific PCIe root complex. + * + * In QEMU, pxb-pcie behaves as a special root complex whose parent is + * effectively the default root complex (pcie.0). The iommu_per_bus + * is checked in pci_device_get_iommu_bus_devfn() to ensure the correct + * IOMMU ops are returned, avoiding the use of the parent=E2=80=99s IOMMU = when + * it's not appropriate. + */ +void pci_setup_iommu_per_bus(PCIBus *bus, const PCIIOMMUOps *ops, + void *opaque) +{ + pci_setup_iommu(bus, ops, opaque); + bus->iommu_per_bus =3D true; +} + static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque) { Range *range =3D opaque; --=20 2.43.0 From nobody Sat Nov 15 00:45:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758046445; cv=none; d=zohomail.com; s=zohoarc; b=WLOkrAFlgDEmrdvpAkmfiu8J9e3AfEZABsASwZqL6xCyP02Yb6j6o+id9pIgZWzsRMRnjI7OyzTT7SKhLI9eYHg4L/XzdJW+uyxNGFxS5D+NaK60zTxRY7rlFTY+IbYvZTqNyUdwrpv0yw9Jx1r7I1gk4ZpGwNeNsRqtamY3Lik= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758046445; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Jie2b8L6LtBeITM9fRPk+VpBByVf977W976JKBwZNHE=; b=dq/HGDrJlkhHer3i+mQOzOFmfufoYitmrkPq4bc/o3zMw6aKnByBakjbh+qwVlEPjQ6eB2TvAMdxTeX7iPJhGdqp7S6OQ1jaeN9/I6dx0n5XKEvZkMLhKZs5Ga+dWW2wSnIP7Kwepj7RsjcMvNNiAGkit7Y0137jfmyenXaX96M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758046445006373.22000603793356; Tue, 16 Sep 2025 11:14:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uya5p-0004lS-SG; Tue, 16 Sep 2025 14:07:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uya4z-0003DH-B4 for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:07:03 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uya4s-0001eC-19 for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:07:00 -0400 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-3d118d8fa91so46717f8f.1 for ; Tue, 16 Sep 2025 11:06:50 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3e760775880sm23033286f8f.2.2025.09.16.11.06.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 11:06:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758046009; x=1758650809; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Jie2b8L6LtBeITM9fRPk+VpBByVf977W976JKBwZNHE=; b=VC3TIjWwYYwOM+Qx3yKpBWlG3z7UdOYQuQzGFBwVmdQMj03PeQGSIqlwTe9hlK1vz/ uGHYaeLcrycS8Is6qOdfTgNcwTXV2YTxlCFONDgSUrBtmOyPTrhqltcisrKQ1hG058uC Rxu3sgWzc1jJ6EeXAHEwVjz5JCNlwla1ncwNyKEyUdwYf6K8PAlpDrtPPGBq1zKL5RT9 xYkGHeY6el+E06iX0VvNOHsKzhXFknl0fcOxvYhjMLDykwh7gGVTNC4BLMbTjn/RwTzg ZUL1sH/kEEPRPV8UYPfrfDGGrRFrAvgwOO0k+uDEHylJ6Ku78AtRY2ZKgIi6QprNDYSp aoQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758046009; x=1758650809; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Jie2b8L6LtBeITM9fRPk+VpBByVf977W976JKBwZNHE=; b=xH9BoYIzRHHeK8MFqI0wA455a2AfvUHzXPVH/tIbt9oJnv1KsIL6dSzgP6WM2ODwvu sEeXxLwuJ8OwtbahvEFTgYrfBX4Mi1U44l9nop0qqF09qL58mhe03N5QIKsvg66upqRx 7C6jJ/+h820sFWBhDlGTZ6e0j98Sy8AhpTuAa3jowHj3GIQMCENXeSNfp2rHVmI1E1u2 LWy9H+qa363CWS/xO7dKOe7OU7wC5MhBlUAJLDTm1o1Yu07bA957HCVZr7OeprmXRp8C 0eVovdV6QBq5GCmBvAsT1diHumhYdzbvnScPWdbQghkxXBa1tH82Llodw4e33Q/QRlR9 Fgww== X-Gm-Message-State: AOJu0YyXWsbLUgGZN0Xw4p29RIvZB0fcWduFcOFbPxMRy+afDxfX2haM /btOVudn55N6CgQ1szPQxiJCeLknbWcWRgYXFtaJjyWtlz/H4CRLN7YVtbDVmFEgSgFnka4JDMC KDzHl X-Gm-Gg: ASbGncvl8DIx+CFY8fU1Aq6UlALyzNGaBWiaLzGJR79BDWQugE0gx5nra9viBY7ZxI1 +Zne5NkEgW131gs/kfMbhxz2D8Rupfpq3bQYMgX0O/vFkp3HEde0WOiYRZX1zefYRFLWW0Xam83 +GiUoW7Yglxdv4o+5GAaKA39H0Aui7US+QEL6ow2acaV+2U2irBszPMBVzr6q5rT/mUw6Onf0KB 2ZyzAoLyVgqAgBCsEv9pjWOfeZosJ9oy+WaaGeAtEsCGAsYMY7w5AheWRyxWTiq2dpKOBk3XB3Q VRoErKqGwmYyMh6uFYNc/lu8u+lgd73KQxo0Wfe0EwOeYFQEEV1iOR59Ucy3tieDtt+pKip1n0D rYd3ZaRYffpSZaQ9+S+KWB/D2dEt6 X-Google-Smtp-Source: AGHT+IErl2U4bI2jZlINn7pTP/daHLtMOtZIgJRfnqTbc9SPvPYrjuOK6BpKx5V83fV8+Uupt9Snig== X-Received: by 2002:a5d:5d0e:0:b0:3ea:71c4:8e3a with SMTP id ffacd0b85a97d-3ec9e1af7camr3028978f8f.13.1758046008967; Tue, 16 Sep 2025 11:06:48 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/36] hw/arm/virt: Allow user-creatable SMMUv3 dev instantiation Date: Tue, 16 Sep 2025 19:06:05 +0100 Message-ID: <20250916180611.1481266-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916180611.1481266-1-peter.maydell@linaro.org> References: <20250916180611.1481266-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758046447116116600 From: Shameer Kolothum Allow cold-plugging of an SMMUv3 device on the virt machine when no global (legacy) SMMUv3 is present or when a virtio-iommu is specified. This user-created SMMUv3 device is tied to a specific PCI bus provided by the user, so ensure the IOMMU ops are configured accordingly. Due to current limitations in QEMU=E2=80=99s device tree support, specifica= lly its inability to properly present pxb-pcie based root complexes and their devices, the device tree support for the new SMMUv3 device is limited to cases where it is attached to the default pcie.0 root complex. Reviewed-by: Jonathan Cameron Reviewed-by: Eric Auger Tested-by: Nathan Chen Tested-by: Eric Auger Tested-by: Nicolin Chen Signed-off-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Reviewed-by: Donald Dutile Reviewed-by: Nicolin Chen Message-id: 20250829082543.7680-8-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- include/hw/arm/smmu-common.h | 1 + hw/arm/smmu-common.c | 8 +++++- hw/arm/smmuv3.c | 2 ++ hw/arm/virt.c | 51 ++++++++++++++++++++++++++++++++++++ hw/core/sysbus-fdt.c | 3 +++ 5 files changed, 64 insertions(+), 1 deletion(-) diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index e5e2d09294d..80d0fecfde8 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -161,6 +161,7 @@ struct SMMUState { QLIST_HEAD(, SMMUDevice) devices_with_notifiers; uint8_t bus_num; PCIBus *primary_bus; + bool smmu_per_bus; /* SMMU is specific to the primary_bus */ }; =20 struct SMMUBaseClass { diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 7f64ea48d03..62a76121841 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -961,7 +961,12 @@ static void smmu_base_realize(DeviceState *dev, Error = **errp) goto out_err; } } - pci_setup_iommu(pci_bus, &smmu_ops, s); + + if (s->smmu_per_bus) { + pci_setup_iommu_per_bus(pci_bus, &smmu_ops, s); + } else { + pci_setup_iommu(pci_bus, &smmu_ops, s); + } return; } out_err: @@ -986,6 +991,7 @@ static void smmu_base_reset_exit(Object *obj, ResetType= type) =20 static const Property smmu_dev_properties[] =3D { DEFINE_PROP_UINT8("bus_num", SMMUState, bus_num, 0), + DEFINE_PROP_BOOL("smmu_per_bus", SMMUState, smmu_per_bus, false), DEFINE_PROP_LINK("primary-bus", SMMUState, primary_bus, TYPE_PCI_BUS, PCIBus *), }; diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index ab679723533..bcf8af8dc73 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1996,6 +1996,8 @@ static void smmuv3_class_init(ObjectClass *klass, con= st void *data) device_class_set_parent_realize(dc, smmu_realize, &c->parent_realize); device_class_set_props(dc, smmuv3_properties); + dc->hotpluggable =3D false; + dc->user_creatable =3D true; } =20 static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 64b4dcf6071..7b3f9b1cdfe 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -57,6 +57,7 @@ #include "qemu/cutils.h" #include "qemu/error-report.h" #include "qemu/module.h" +#include "hw/pci/pci_bus.h" #include "hw/pci-host/gpex.h" #include "hw/pci-bridge/pci_expander_bridge.h" #include "hw/virtio/virtio-pci.h" @@ -1475,6 +1476,29 @@ static void create_smmuv3_dt_bindings(const VirtMach= ineState *vms, hwaddr base, g_free(node); } =20 +static void create_smmuv3_dev_dtb(VirtMachineState *vms, + DeviceState *dev, PCIBus *bus) +{ + PlatformBusDevice *pbus =3D PLATFORM_BUS_DEVICE(vms->platform_bus_dev); + SysBusDevice *sbdev =3D SYS_BUS_DEVICE(dev); + int irq =3D platform_bus_get_irqn(pbus, sbdev, 0); + hwaddr base =3D platform_bus_get_mmio_addr(pbus, sbdev, 0); + MachineState *ms =3D MACHINE(vms); + + if (!(vms->bootinfo.firmware_loaded && virt_is_acpi_enabled(vms)) && + strcmp("pcie.0", bus->qbus.name)) { + warn_report("SMMUv3 device only supported with pcie.0 for DT"); + return; + } + base +=3D vms->memmap[VIRT_PLATFORM_BUS].base; + irq +=3D vms->irqmap[VIRT_PLATFORM_BUS]; + + vms->iommu_phandle =3D qemu_fdt_alloc_phandle(ms->fdt); + create_smmuv3_dt_bindings(vms, base, SMMU_IO_LEN, irq); + qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map", + 0x0, vms->iommu_phandle, 0x0, 0x10000); +} + static void create_smmu(const VirtMachineState *vms, PCIBus *bus) { @@ -3006,6 +3030,16 @@ static void virt_machine_device_pre_plug_cb(HotplugH= andler *hotplug_dev, qlist_append_str(reserved_regions, resv_prop_str); qdev_prop_set_array(dev, "reserved-regions", reserved_regions); g_free(resv_prop_str); + } else if (object_dynamic_cast(OBJECT(dev), TYPE_ARM_SMMUV3)) { + if (vms->legacy_smmuv3_present || vms->iommu =3D=3D VIRT_IOMMU_VIR= TIO) { + error_setg(errp, "virt machine already has %s set. " + "Doesn't support incompatible iommus", + (vms->legacy_smmuv3_present) ? + "iommu=3Dsmmuv3" : "virtio-iommu"); + } else if (vms->iommu =3D=3D VIRT_IOMMU_NONE) { + /* The new SMMUv3 device is specific to the PCI bus */ + object_property_set_bool(OBJECT(dev), "smmu_per_bus", true, NU= LL); + } } } =20 @@ -3029,6 +3063,22 @@ static void virt_machine_device_plug_cb(HotplugHandl= er *hotplug_dev, virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); } =20 + if (object_dynamic_cast(OBJECT(dev), TYPE_ARM_SMMUV3)) { + if (!vms->legacy_smmuv3_present && vms->platform_bus_dev) { + PCIBus *bus; + + bus =3D PCI_BUS(object_property_get_link(OBJECT(dev), "primary= -bus", + &error_abort)); + if (pci_bus_bypass_iommu(bus)) { + error_setg(errp, "Bypass option cannot be set for SMMUv3 " + "associated PCIe RC"); + return; + } + + create_smmuv3_dev_dtb(vms, dev, bus); + } + } + if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { PCIDevice *pdev =3D PCI_DEVICE(dev); =20 @@ -3231,6 +3281,7 @@ static void virt_machine_class_init(ObjectClass *oc, = const void *data) machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); machine_class_allow_dynamic_sysbus_dev(mc, TYPE_UEFI_VARS_SYSBUS); + machine_class_allow_dynamic_sysbus_dev(mc, TYPE_ARM_SMMUV3); #ifdef CONFIG_TPM machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); #endif diff --git a/hw/core/sysbus-fdt.c b/hw/core/sysbus-fdt.c index c339a27875c..e80776080be 100644 --- a/hw/core/sysbus-fdt.c +++ b/hw/core/sysbus-fdt.c @@ -31,6 +31,7 @@ #include "qemu/error-report.h" #include "system/device_tree.h" #include "system/tpm.h" +#include "hw/arm/smmuv3.h" #include "hw/platform-bus.h" #include "hw/vfio/vfio-platform.h" #include "hw/vfio/vfio-calxeda-xgmac.h" @@ -518,6 +519,8 @@ static const BindingEntry bindings[] =3D { #ifdef CONFIG_TPM TYPE_BINDING(TYPE_TPM_TIS_SYSBUS, add_tpm_tis_fdt_node), #endif + /* No generic DT support for smmuv3 dev. Support added for arm virt on= ly */ + TYPE_BINDING(TYPE_ARM_SMMUV3, no_fdt_node), TYPE_BINDING(TYPE_RAMFB_DEVICE, no_fdt_node), TYPE_BINDING(TYPE_UEFI_VARS_SYSBUS, add_uefi_vars_node), TYPE_BINDING("", NULL), /* last element */ --=20 2.43.0 From nobody Sat Nov 15 00:45:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758046088; cv=none; d=zohomail.com; s=zohoarc; b=Qv2dObA5OYIiK1z5OLBGUpi7lHY3VHrACtHpfGMHT+WaTCot0DG44U/n0S8F1mFd591tg0jZ0/pvKVXpT1PEt8uctMwCXevB7iLYwMJ8MzsToSreH/DC1EJ3gwm23J+Int5K6Va7m++rS0vwIBzm6HrEFqDugwtIyYwcE507DW0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758046088; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=lxKnBCOImWIkwJQbGUGHvGVkNj52S0Z0jeayxRUvfM8=; b=M5eiVmelu81aYKy0ZUzKHv19JFP9D0JmL1cZy7vCt52LCYF/awY60szYOMWFStXRonHpvvZBrXJojok9wpJCEJmGh0GSOyT7B6f65/DiTUBWkb5PmM2qdvPaV2x9y6AFsAO3BRVI8uCSTTYIsz+t3/sZBVskBC3bNljR9TBD47U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758046088135670.0972961143593; Tue, 16 Sep 2025 11:08:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uya5k-0004VJ-NG; Tue, 16 Sep 2025 14:07:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uya4x-0003Aq-Ba for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:06:59 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uya4s-0001eG-3a for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:06:59 -0400 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-3e8ea11a325so4025786f8f.1 for ; Tue, 16 Sep 2025 11:06:51 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3e760775880sm23033286f8f.2.2025.09.16.11.06.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 11:06:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758046010; x=1758650810; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=lxKnBCOImWIkwJQbGUGHvGVkNj52S0Z0jeayxRUvfM8=; b=GW1/WWSJqjBZoIPea/2DmYHO55vlBVtCnwcg+bA/8zXCAlGRQjnfhs9ZSt/2DjNOis ICdtBhXN1C7arU/t3m+FMhr250C3GIFIKerO/HJi4lsL5L8f//yvtdGjLlgR7x1e8vGo QHnM8bjmCBBInxy/mxk92vHZroLd+dIzSA5oJsxO0EIZibfviJ9EFo9RkZJJpEjy3l7e +2CF805iJKyBhiPtHOvdd13knVQZ0fKK0O9ImtC5JWRw1zQYUpi4aRRKPJEER+vr21aa S8oPpfZBmwMmMhhe2182Q/CrW8Z53FgkvFAuYoyLGp568/0Y6M0OV+9HbcD+QhRtP7pA sYEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758046010; x=1758650810; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lxKnBCOImWIkwJQbGUGHvGVkNj52S0Z0jeayxRUvfM8=; b=BhNR99R6f8QtdC5cG0Ks0ps9TrTIg0699VFm6tYl05eCOBH+lTZzctTkUCePNXHVda vMNHKLcrhj0y+SUcim4QchKOwhpiCqRmw0009CgXo/GOe6lNpchOsEsOKlNMjO2wUjmY P4srW3Rg/8DiE2yFOYqvwz+/XpBUWgJNA0QD71OKSmu9RxyPy7F0Amj1sE9Fq2cy9qPB JHcoSJwxcvGPliW/amc2/iJbxOTMA8vwcnwb5QkKMqchejNstqsuJff9YkzN3tpXzzWP FFeArDfyYbrXBn7YH+Hfm1VAvhq6cJQAGptTvAms/I4XWanxZF4iotIQyplgdLm5rPhS nfeg== X-Gm-Message-State: AOJu0YwTH5gxqF27P4Y82qt8WcQQutoITGHPqhKI9slHo5iZBV7e1kCM h0WY5Dp1tpJQmiKEgT6AqYh6Y5FWR9qh7/byo1XYDGzCw1eW7zv/C1/TGW4bBDB6qVfQ8agbRnN a1lcT X-Gm-Gg: ASbGncvhlKbbkZ24LgvrpmkQ/WZw4N9U0r/M4AmK7BE7lWruc78OqKkS/Pgwjqi1CVE 0QKFFft3Vr176J4BuCTjWJzBHaoeLcZlqBjzTiu0zVxyS8Rbv3tTf/CGXzkiunHidkXS65aApJz k6RW47Zvec/bOQhkalOym9kFYP44ogzawlvqCNkN2oyNM4Ye/OyKJ2reR/+G7Tq1AlZOU03Nlv2 4gY7W5XwWWSIBOcVhtVltuhTLISME4xYHk9VqVhy+WklDugCyg0QxRxG/IQ0nyUUBRklgXfT8IE rVgL1HoKaavNqsBLf7SDfa0ut5fvVK57OBMHOR0xhurDn7OESVDrnDcIIDcXKgrdZlTU75oE1ul HTe8iCZGlUeYqiexHNRTxXcI9+RdU X-Google-Smtp-Source: AGHT+IHHs5iKR/6eQ4r5PhZvRxl/MonntUZZ4/DBZ1pdfnj8W/qAZAv0qR3SNv0TGnQAFqkTl6Z7Og== X-Received: by 2002:a5d:5d05:0:b0:3e2:c41c:bfe3 with SMTP id ffacd0b85a97d-3e7659d3a79mr16790645f8f.38.1758046009888; Tue, 16 Sep 2025 11:06:49 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 32/36] qemu-options.hx: Document the arm-smmuv3 device Date: Tue, 16 Sep 2025 19:06:06 +0100 Message-ID: <20250916180611.1481266-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916180611.1481266-1-peter.maydell@linaro.org> References: <20250916180611.1481266-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758046090463116600 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum Now that arm,virt can have user-creatable smmuv3 devices, document it. Reviewed-by: Jonathan Cameron Reviewed-by: Eric Auger Tested-by: Eric Auger Tested-by: Nicolin Chen Signed-off-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Reviewed-by: Donald Dutile Reviewed-by: Nicolin Chen Message-id: 20250829082543.7680-9-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- qemu-options.hx | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qemu-options.hx b/qemu-options.hx index aa44b0e34ae..075f4be2e3e 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -1231,6 +1231,13 @@ SRST ``aw-bits=3Dval`` (val between 32 and 64, default depends on machine) This decides the address width of the IOVA address space. =20 +``-device arm-smmuv3,primary-bus=3Did`` + This is only supported by ``-machine virt`` (ARM). + + ``primary-bus=3Did`` + Accepts either the default root complex (pcie.0) or a + pxb-pcie based root complex. + ERST =20 DEF("name", HAS_ARG, QEMU_OPTION_name, --=20 2.43.0 From nobody Sat Nov 15 00:45:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758046109; cv=none; d=zohomail.com; s=zohoarc; b=dScvaquwHwM5MDuUaPmSKp1fLNsaObj5CAau00okWY6q5PjO6Wj82CJdDZjTfJttXfpTLD6H7hYFYeJC7n+ReG1HMN+eJwFyKQlNpDB5qhDvMI/exAhnpN7rE796/NXvJLgPjwramsZY0FFEGJIrPovrh720DnueDXCDIYdb+KQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758046109; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=g04gXkzqDwaTf/HMFL3z5yBF259ksFa2ePPUMCg8ocI=; b=YM9YAggRJ9o22VmwFM5/6PbOLwiK0PjEkpPxgvFa5tFzwDKRlxHuKBkBN/RLTOHtRKOMrnHwCvbnrkqPf7CdYiMjZM/yAh+P0+9PcoTyhj0/9RBxUYmAL8P/fwlaJLTupFXopni3jkalTu/JCkU7GRUuDYzgQciN+SdD45IUqM4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758046109676548.1669347788018; Tue, 16 Sep 2025 11:08:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uya5n-0004k8-CF; Tue, 16 Sep 2025 14:07:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uya51-0003ET-ER for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:07:06 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uya4w-0001eN-0u for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:07:02 -0400 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-45f29d2357aso22259015e9.2 for ; Tue, 16 Sep 2025 11:06:52 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3e760775880sm23033286f8f.2.2025.09.16.11.06.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 11:06:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758046011; x=1758650811; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=g04gXkzqDwaTf/HMFL3z5yBF259ksFa2ePPUMCg8ocI=; b=LFv7UTbKt6+1geUJ2E2opgb84nAHpBuKYT+a8+eX3Ua+/sewJuNjWcpZJVSwlA2FW8 7vMekg/7CSL033cvI66TQAyJHYCJPVezfeW/IurwjzlJuIP4Z0ZpsJDyWjdAoqKPULxe VNUjFtfPiC+AUaYm2vSE1s6pqs6yiL93x8cn6gouj19bH0Qk/Wwcgt27D9Fk/iBEoh2N xdZlaUPGhITC72cugoK4/l9FoIv1dnda7imvjTulsJ0npcXuhTxmuIPZf6rrcaocvjf5 XofNTWuP7DKQ0kxJ+UVyAPKcQprpRchSJMr/JaKFCimpt391HTbdc7KElEcMFlbtUL19 gMcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758046011; x=1758650811; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=g04gXkzqDwaTf/HMFL3z5yBF259ksFa2ePPUMCg8ocI=; b=nNobDsm6/sk+iaMtD+cJOwjIMzua0aW2h74jrYk2I4o5R3ophjZTtU4dIJMw6vo/sM /CeLXEGdr4jbFRuMUkY3ri3yXz8v16z3A2WmmBjcxvewCj8e22w5MoHt/o9Kc34SP0eY IRmgpiNIORoaAskTAYoNZNHI/3fQzuLunPocvsgKN2q/yyy0P2JgED2NCpB/MlxjNKsF //u3/h0rcMwGL0Z21tYlpU93fNREte8m4y17JjHCm22Tr/L3obF0R3PxkoD1ci5PsoV+ B1u69hw0a9Vy7annSon/Fcrxgf2iilvvS6nRifv0xQopfvaarUIUDxigrwwTgd4JQb8J GK/A== X-Gm-Message-State: AOJu0Yy1E708vf9fRy37ELcUPce9dc46OOzk8spwrWKekSX0cbwytLNp xCfvjRzvAuxqVxQ69GgX1kYg/XFwhAviFRdu1TYpCDuxeezHHET6lpu/wmVQGAJywvGy1Nk7Nq1 Yj1we X-Gm-Gg: ASbGncuX5cVmYDcdIJSbTplvf2IPvjk8kSVqIpxzX3eIGZBgQ9Boby0tqcmfqr7ABz+ Aj9Jrt/jC9xH8Ljt2HSzz1w9+a6Ah1eZnIIvhG5SQAZSIUazxswwL7ZL2Vy9+CtpfjHl1mjsatw 27PgSXClAnoDPAZNXJpEDSQvUhhbeRiai0cw9Xapc3MIChvxniCtaOERAmKEWkxxyGbmgyr5v2A zGtdzqeY6wZhqbbLl75aetFfaEz+VM8iMx1W0fS5X/Ft2X9OpbTyUAKngnWDXEMZ8qrX+R7165r o9Exe0bf4Njy3N5vPdnTM9O2GyfNAZoJCE4I8OxNT2Qg8W+K+wBbG4h/5Zdwp1YHjoM4DN5a6+1 aj9wuKtRzsGMU62s7oDDg6xIyAd3N X-Google-Smtp-Source: AGHT+IFfqxlrCXqOuWFAW5+8yS0nIQ3nrosZhM7H/7dTtDigUVzdaaNYcmjBjEvf3zahSrtOMyVXIg== X-Received: by 2002:a05:600c:c1c8:10b0:45b:43cc:e557 with SMTP id 5b1f17b1804b1-45f212067efmr125240225e9.34.1758046010864; Tue, 16 Sep 2025 11:06:50 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 33/36] bios-tables-test: Allow for smmuv3 test data. Date: Tue, 16 Sep 2025 19:06:07 +0100 Message-ID: <20250916180611.1481266-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916180611.1481266-1-peter.maydell@linaro.org> References: <20250916180611.1481266-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758046110627116600 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum The tests to be added exercise both legacy(iommu=3Dsmmuv3) and new -device arm-smmuv3,.. cases. Reviewed-by: Jonathan Cameron Reviewed-by: Eric Auger Tested-by: Eric Auger Tested-by: Nicolin Chen Signed-off-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Reviewed-by: Donald Dutile Reviewed-by: Nicolin Chen Message-id: 20250829082543.7680-10-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- tests/qtest/bios-tables-test-allowed-diff.h | 4 ++++ tests/data/acpi/aarch64/virt/DSDT.smmuv3-dev | 0 tests/data/acpi/aarch64/virt/DSDT.smmuv3-legacy | 0 tests/data/acpi/aarch64/virt/IORT.smmuv3-dev | 0 tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy | 0 5 files changed, 4 insertions(+) create mode 100644 tests/data/acpi/aarch64/virt/DSDT.smmuv3-dev create mode 100644 tests/data/acpi/aarch64/virt/DSDT.smmuv3-legacy create mode 100644 tests/data/acpi/aarch64/virt/IORT.smmuv3-dev create mode 100644 tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index dfb8523c8bf..2e3e3ccdcec 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,5 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/aarch64/virt/DSDT.smmuv3-legacy", +"tests/data/acpi/aarch64/virt/DSDT.smmuv3-dev", +"tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy", +"tests/data/acpi/aarch64/virt/IORT.smmuv3-dev", diff --git a/tests/data/acpi/aarch64/virt/DSDT.smmuv3-dev b/tests/data/acpi= /aarch64/virt/DSDT.smmuv3-dev new file mode 100644 index 00000000000..e69de29bb2d diff --git a/tests/data/acpi/aarch64/virt/DSDT.smmuv3-legacy b/tests/data/a= cpi/aarch64/virt/DSDT.smmuv3-legacy new file mode 100644 index 00000000000..e69de29bb2d diff --git a/tests/data/acpi/aarch64/virt/IORT.smmuv3-dev b/tests/data/acpi= /aarch64/virt/IORT.smmuv3-dev new file mode 100644 index 00000000000..e69de29bb2d diff --git a/tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy b/tests/data/a= cpi/aarch64/virt/IORT.smmuv3-legacy new file mode 100644 index 00000000000..e69de29bb2d --=20 2.43.0 From nobody Sat Nov 15 00:45:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758046312; cv=none; d=zohomail.com; s=zohoarc; b=bBitOE9F2o/nYRvccvuC7ifysEq+j70wm5guvc+XjZFp8Sc910KZFNn/w1eDcuU+XLsJ39Crb5MoM2jLw/vbg92REq8mbvzAJteclQrvVRfdGR3+e5y8WN1zdZIwrctkU4/I1Id8S8NCB6/7i/5UnSuZkaftL5JJXiGNoyfm0ac= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758046312; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=4dqb0NZE3YDP33SsalYcTuCfe7e9JX4x4Z6Cv8SAzRA=; b=UlWiKfY+b6vSCrpkdEeJxIV3OTMDHFn0bhK7nW8oWb42xrhexopifaAaEp5ivjhGUrD1OCzs/b1lBlkSXkhDPvzL6J5VKYgfvKPJJ4bnvYBVbrTg8syPMse14QyBCR8ZWhlRoYrhqrGjOIDGQhffizbgiUrWfudPLk/JVAahPPY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758046312056554.3975832664188; Tue, 16 Sep 2025 11:11:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uya6E-0005ni-Q3; Tue, 16 Sep 2025 14:08:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uya59-0003VZ-EO for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:07:18 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uya4w-0001eR-0s for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:07:04 -0400 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-3e98c5adbbeso1450881f8f.0 for ; Tue, 16 Sep 2025 11:06:53 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3e760775880sm23033286f8f.2.2025.09.16.11.06.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 11:06:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758046012; x=1758650812; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=4dqb0NZE3YDP33SsalYcTuCfe7e9JX4x4Z6Cv8SAzRA=; b=bqNe3VtHi9VSduTy3DOeRfn6EasrzU/e3+KIhX2T4X0rRE3FWnyL1/JScsB1Cv9Y/s EcIyBVJfO15jggkYvlc26goX+QOgzvZ9OnUY5lnCn7XvCRlQuDShwsZ1A5Q4zLVJo/Qj RcgdP/853S71cWaDb5xBH/X4w2CUZSEtinut+wMvi+Ci8/KeCracBkQL4WvtSBBj0Svz lyJDIT6sVTu1aEqrnmaCIL64FpJBd/gyQqY0sECgD7hBZnCuR3YCW/xCxJczZKQMjVWh Kuap8odWmzDwgyOwP7YpluI5Y6upUUnlDh4ib55eAbjwLbMHiB3zG6oonxUhvIHnW5tE QFPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758046012; x=1758650812; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4dqb0NZE3YDP33SsalYcTuCfe7e9JX4x4Z6Cv8SAzRA=; b=c/kGNAchC3CUBJrq917l77Ma0zO+RZcmsI5VFLLjQ9yILILeom2/RbOvGv2W3VEDSS dhUdDkjJSGvYKtB+656xxUU3+u5d+Cgursw8LLZT2Kjl+3WbpVzNicdu2NHh+Je58rhN m+LPu1hI4S9LaXydcf9+Jfp0bRca8vwcDft5FUYQuJKI41/Oe7gx4jQD00BBDaUeEX3F M4NoJx/unqmrPhaGgo6ANOih4AH+elkOYMel29M/78/abhA8lXMSvV4f9pd6Jl9DlmU3 1M1DhjQyHRLVvok+mPxo9rQ1ORJZ1AWqPbHR4b5ft1RPIMHFfudvA63VnueFrTVLbNhC GKyA== X-Gm-Message-State: AOJu0Yy0ojzbZAsituyMdgAby3OHzaG8q+hqEEhmszbJcoTtdYcfKTtp IoPy64j26AmulhQ3mhZmmfFOQPvuLQnrKbBx8Nfj8jUOF1/05pRHBk0/xzQE84Ecd9llO1wKm94 GmVPI X-Gm-Gg: ASbGncsQ6A+sXVbUKlKsS9gJHgcUy273ZkoV+Ng1DM34DmPhNYXD5M/Alrx3vO5jJ10 gWLwDxAMncH1Y2XWXs6umpMjO+TiFrBmgSVDHzYSoLzSPl75nK5YWZ1e3JAkl+9nMtmKUssy/ZQ yqA40XUsti3w89BOmTAe0Nq9OrjxYAewjwurtYgJaipb1T8YkKGw6B+0DD5PbDlnufehfg+X4bc IP6j5ViB0mQGcI6y7ARwsegZa2jE2vGWwLmxZWRmGqUEuHg+EYfhEHDWkK2CR6FsHqqryKbMkfE hqlfpskHv0NvlbKJL/bRj0CiM+GEfEIH3W/58ozEp5nA/he9rJdqDwnP+8EQxMb3ktoGRjcI2Jn +/K/vCSHtaDL9bj5lptV8yVS6ECAu X-Google-Smtp-Source: AGHT+IFcrl5LWaDdwAFuWOLHgURIe6d03ve/2+fXA+BdXn406aClxbHvbzKUnSbU9wsQAJnd2SFRhA== X-Received: by 2002:a05:6000:2dc2:b0:3eb:4681:acbc with SMTP id ffacd0b85a97d-3eb4681b0c9mr7037204f8f.23.1758046012120; Tue, 16 Sep 2025 11:06:52 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 34/36] qtest/bios-tables-test: Add tests for legacy smmuv3 and smmuv3 device Date: Tue, 16 Sep 2025 19:06:08 +0100 Message-ID: <20250916180611.1481266-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916180611.1481266-1-peter.maydell@linaro.org> References: <20250916180611.1481266-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758046313359116600 From: Shameer Kolothum For the legacy SMMUv3 test, the setup includes three PCIe Root Complexes, one of which has bypass_iommu enabled. The generated IORT table contains a single SMMUv3 node, a Root Complex(RC) node and 1 ITS node. RC node features 4 ID mappings, of which 2 points to SMMU node and the remaining ones points to ITS. pcie.0 -> {SMMU0} -> {ITS} {RC} pcie.1 -> {SMMU0} -> {ITS} pcie.2 -> {ITS} [all other ids] -> {ITS} For the -device arm-smmuv3,... test, the configuration also includes three Root Complexes, with two connected to separate SMMUv3 devices. The resulting IORT table contains 1 RC node, 2 SMMU nodes and 1 ITS node. RC node features 4 ID mappings. 2 of them target the 2 SMMU nodes while the others targets the ITS. pcie.0 -> {SMMU0} -> {ITS} {RC} pcie.1 -> {SMMU1} -> {ITS} pcie.2 -> {ITS} [all other ids] -> {ITS} Reviewed-by: Jonathan Cameron Reviewed-by: Eric Auger Tested-by: Eric Auger Tested-by: Nicolin Chen Signed-off-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Reviewed-by: Donald Dutile Reviewed-by: Nicolin Chen Message-id: 20250829082543.7680-11-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- tests/qtest/bios-tables-test.c | 86 ++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index e7e6926c816..4fa8ac5096a 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -2337,6 +2337,86 @@ static void test_acpi_aarch64_virt_viot(void) free_test_data(&data); } =20 +static void test_acpi_aarch64_virt_smmuv3_legacy(void) +{ + test_data data =3D { + .machine =3D "virt", + .arch =3D "aarch64", + .tcg_only =3D true, + .uefi_fl1 =3D "pc-bios/edk2-aarch64-code.fd", + .uefi_fl2 =3D "pc-bios/edk2-arm-vars.fd", + .ram_start =3D 0x40000000ULL, + .scan_len =3D 128ULL * MiB, + }; + + /* + * cdrom is plugged into scsi controller to avoid conflict + * with pxb-pcie. See comments in test_acpi_aarch64_virt_tcg_pxb() for + * details. + * + * The setup includes three PCIe root complexes, one of which has + * bypass_iommu enabled. The generated IORT table contains a single + * SMMUv3 node and a Root Complex node with three ID mappings. Two + * of the ID mappings have output references pointing to the SMMUv3 + * node and the remaining one points to ITS. + */ + data.variant =3D ".smmuv3-legacy"; + test_acpi_one(" -device pcie-root-port,chassis=3D1,id=3Dpci.1" + " -device virtio-scsi-pci,id=3Dscsi0,bus=3Dpci.1" + " -drive file=3D" + "tests/data/uefi-boot-images/bios-tables-test.aarch64.is= o.qcow2," + "if=3Dnone,media=3Dcdrom,id=3Ddrive-scsi0-0-0-1,readonly= =3Don" + " -device scsi-cd,bus=3Dscsi0.0,scsi-id=3D0," + "drive=3Ddrive-scsi0-0-0-1,id=3Dscsi0-0-0-1,bootindex=3D= 1" + " -cpu cortex-a57" + " -M iommu=3Dsmmuv3" + " -device pxb-pcie,id=3Dpcie.1,bus=3Dpcie.0,bus_nr=3D0x1= 0" + " -device pxb-pcie,id=3Dpcie.2,bus=3Dpcie.0,bus_nr=3D0x2= 0,bypass_iommu=3Don", + &data); + free_test_data(&data); +} + +static void test_acpi_aarch64_virt_smmuv3_dev(void) +{ + test_data data =3D { + .machine =3D "virt", + .arch =3D "aarch64", + .tcg_only =3D true, + .uefi_fl1 =3D "pc-bios/edk2-aarch64-code.fd", + .uefi_fl2 =3D "pc-bios/edk2-arm-vars.fd", + .ram_start =3D 0x40000000ULL, + .scan_len =3D 128ULL * MiB, + }; + + /* + * cdrom is plugged into scsi controller to avoid conflict + * with pxb-pcie. See comments in test_acpi_aarch64_virt_tcg_pxb() + * for details. + * + * The setup includes three PCie root complexes, two of which are + * connected to separate SMMUv3 devices. The resulting IORT table + * contains two SMMUv3 nodes and a Root Complex node with ID mappings + * of which two of the=C2=A0ID mappings have output references pointing + * to two different SMMUv3 nodes and the remaining ones pointing to + * ITS. + */ + data.variant =3D ".smmuv3-dev"; + test_acpi_one(" -device pcie-root-port,chassis=3D1,id=3Dpci.1" + " -device virtio-scsi-pci,id=3Dscsi0,bus=3Dpci.1" + " -drive file=3D" + "tests/data/uefi-boot-images/bios-tables-test.aarch64.is= o.qcow2," + "if=3Dnone,media=3Dcdrom,id=3Ddrive-scsi0-0-0-1,readonly= =3Don" + " -device scsi-cd,bus=3Dscsi0.0,scsi-id=3D0," + "drive=3Ddrive-scsi0-0-0-1,id=3Dscsi0-0-0-1,bootindex=3D= 1" + " -cpu cortex-a57" + " -device arm-smmuv3,primary-bus=3Dpcie.0,id=3Dsmmuv3.0" + " -device pxb-pcie,id=3Dpcie.1,bus=3Dpcie.0,bus_nr=3D0x1= 0" + " -device arm-smmuv3,primary-bus=3Dpcie.1,id=3Dsmmuv3.1" + " -device pxb-pcie,id=3Dpcie.2,bus=3Dpcie.0,bus_nr=3D0x2= 0", + &data); + free_test_data(&data); +} + #ifndef _WIN32 # define DEV_NULL "/dev/null" #else @@ -2768,6 +2848,12 @@ int main(int argc, char *argv[]) if (qtest_has_device("virtio-iommu-pci")) { qtest_add_func("acpi/virt/viot", test_acpi_aarch64_virt_vi= ot); } + qtest_add_func("acpi/virt/smmuv3-legacy", + test_acpi_aarch64_virt_smmuv3_legacy); + if (qtest_has_device("arm-smmuv3")) { + qtest_add_func("acpi/virt/smmuv3-dev", + test_acpi_aarch64_virt_smmuv3_dev); + } } } else if (strcmp(arch, "riscv64") =3D=3D 0) { if (has_tcg && qtest_has_device("virtio-blk-pci")) { --=20 2.43.0 From nobody Sat Nov 15 00:45:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758046232; cv=none; d=zohomail.com; s=zohoarc; b=jlegNWI/FQ2jAnfnIe+CHvPjKLQ5xNYWfj+r2ytt/NKZxDG2k/oqqL2rl97/JdZ3f0fD062O8alYALqYnvVZxAIIAXUIZbY28vPst+5twgYM8n8WPTkxYT8Xne+gR+EdlIVus1Kj0KE7DFdcV4Kq9yjinu1rdQe1qQoQbM0fCrM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758046232; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=UkARRwZyoo7H6bF6Vk8t98197iZiJFfH3aRXFYrYnPo=; b=AmT4L+jtOV51rO6oWZvofBtrEJjcorIfZlaO1jQG9d7I5r9ofgebN62j9BIHjJNDve6JvxOD3hcUS+9B7Ppm+pdD2JZk6WeLOLdv6K6TJ/LBT9FQ/sboVbqLqb6WKL4whlpLWOKe4KGihzsh6pNn4Xm2BxfXC5e9M8HLJWSfuG4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17580462327691022.5154331800316; Tue, 16 Sep 2025 11:10:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uya60-0005YB-8l; Tue, 16 Sep 2025 14:08:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uya51-0003EO-EN for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:07:06 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uya4v-0001ee-ST for qemu-devel@nongnu.org; Tue, 16 Sep 2025 14:07:02 -0400 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-3c46686d1e6so4003983f8f.3 for ; Tue, 16 Sep 2025 11:06:54 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3e760775880sm23033286f8f.2.2025.09.16.11.06.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 11:06:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758046014; x=1758650814; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=UkARRwZyoo7H6bF6Vk8t98197iZiJFfH3aRXFYrYnPo=; b=FQ/qzUoUUQHZW1+8vPZXEfvm3LF4Ykydm1KXOIJituaWmzT8Rwksb++kSVstkM7ZAs DZIX3pyHBpNpINUfMG0Myc8wljMZ/RAVdShrM99CiQjFdj2OiUsQW/uzvrqyj4aMYjvq yQz8XIsITKafMqEEd+hrkl5QFrE2n7hpxO85YeRcE4sd++pZYSSrnjpf1x+L3CnspobX GRGmivHb2gVGdC1zhA/rAB0BH2FPsftB+4YZymyERMUkEM/DUuyRWqlHmdCJnEPDLsCO NbYb1z0D3b2UwpS22QxlawpzybPvPDLzPHDMYA3aZ6+brGyVDd0bCHVaYuFyG9dzgvgx vchw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758046014; x=1758650814; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UkARRwZyoo7H6bF6Vk8t98197iZiJFfH3aRXFYrYnPo=; b=uvFN8Mk9zf51eRtlrxtKc9HaNUV4xIAAdNBKaAmGjtoxmplYeDDLBfhbU88IYDit8k g5gppWVxUx2BWD+ItsP4mEDWgBjMyjvpPdV0X3RSwLfRL+HcXx7oqMtow05AS8Aq5wzu eOXDTzK8JJO8uizz889d5tPlkS4IT6jWjvXBugfmK2o201Ird2uGT+U/jHNltFz/lTf/ gxXf6lwOdnAnCiirNJWamE444SYQRijdpMG0Bohu3EGkZTDeIrF4BoUulKnHk5Xta8iK MzarPaAcmpB3ugjkM9eW06ebAWv4argCaxu5zz2mw5gBKeGkhuTx4QNxHjqa0BKy6yo2 O4dQ== X-Gm-Message-State: AOJu0Yz0HugLrmyTmNKZ4FvOxLZX/z2ieTI7TLGBKI+XqDyr2pqZN7NM gcjQkaRj4AZ7ktKORq3A32PYya/mExKCPgdhfo+/1e0gyIRWRUjPzR8xBGCDXrxmUKb8uzSw7dB S+j+b X-Gm-Gg: ASbGncv2PcV7qXfA41BXEJ7ZNCkBGG3fus388k5FMp07maL1gaPt9TwwtRnTCQpIUr2 DiQauAdosyMD4HmhB+ils2VTCjB+cXxV/rY8nTUsmk41N+iSeomRAzmTm+qCmr7usr425rbw/Hu mB0Ua24kf2ANtJQRP4n7oNhn/0WvcXQB7Xc9ASFcCV+3KR2lHm5/rzVnCudYQp7/yZ7ZtBvbO2D 0QHVNCVL1+oZH6vKmmm5Uw56nqRhUMNLJ6obm+XhIGyTgH7ZPvfCzUxUDBevYcy3XFQLuc2j1m3 LVcXyy2gizMM9LZtK/cH1lNGyouS/GX1cvW2avRil1MzE93aK0EeMNN+O/+aMjlCspBp3N02ej2 kZzEwXIYT2yliq9F8oaexgVH6NG2/ X-Google-Smtp-Source: AGHT+IGP7Qj2eoo+9LCmzCnFsCuaS2bg0DG8h2q/nqKydQZd77DrkYsX3UCGf2dYljKBCS40uV1tng== X-Received: by 2002:a05:6000:2586:b0:3e4:1e29:47db with SMTP id ffacd0b85a97d-3e765a25836mr16860951f8f.43.1758046013534; Tue, 16 Sep 2025 11:06:53 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 35/36] qtest/bios-tables-test: Update tables for smmuv3 tests Date: Tue, 16 Sep 2025 19:06:09 +0100 Message-ID: <20250916180611.1481266-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916180611.1481266-1-peter.maydell@linaro.org> References: <20250916180611.1481266-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758046234367116600 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum For the legacy smmuv3 test case, generated IORT has a single SMMUv3 node, a Root Complex(RC) node and 1 ITS node. RC node features 4 ID mappings, of which 2 points to SMMU node and the remaining ones points to ITS. pcie.0 -> {SMMU0} -> {ITS} {RC} pcie.1 -> {SMMU0} -> {ITS} pcie.2 -> {ITS} [all other ids] -> {ITS} ... [030h 0048 1] Type : 00 [031h 0049 2] Length : 0018 [033h 0051 1] Revision : 01 [034h 0052 4] Identifier : 00000000 [038h 0056 4] Mapping Count : 00000000 [03Ch 0060 4] Mapping Offset : 00000000 [040h 0064 4] ItsCount : 00000001 [044h 0068 4] Identifiers : 00000000 [048h 0072 1] Type : 04 [049h 0073 2] Length : 0058 [04Bh 0075 1] Revision : 04 [04Ch 0076 4] Identifier : 00000001 [050h 0080 4] Mapping Count : 00000001 [054h 0084 4] Mapping Offset : 00000044 [058h 0088 8] Base Address : 0000000009050000 [060h 0096 4] Flags (decoded below) : 00000001 COHACC Override : 1 HTTU Override : 0 Proximity Domain Valid : 0 [064h 0100 4] Reserved : 00000000 [068h 0104 8] VATOS Address : 0000000000000000 [070h 0112 4] Model : 00000000 [074h 0116 4] Event GSIV : 0000006A [078h 0120 4] PRI GSIV : 0000006B [07Ch 0124 4] GERR GSIV : 0000006D [080h 0128 4] Sync GSIV : 0000006C [084h 0132 4] Proximity Domain : 00000000 [088h 0136 4] Device ID Mapping Index : 00000000 [08Ch 0140 4] Input base : 00000000 [090h 0144 4] ID Count : 0000FFFF [094h 0148 4] Output Base : 00000000 [098h 0152 4] Output Reference : 00000030 [09Ch 0156 4] Flags (decoded below) : 00000000 Single Mapping : 0 [0A0h 0160 1] Type : 02 [0A1h 0161 2] Length : 0074 [0A3h 0163 1] Revision : 03 [0A4h 0164 4] Identifier : 00000002 [0A8h 0168 4] Mapping Count : 00000004 [0ACh 0172 4] Mapping Offset : 00000024 [0B0h 0176 8] Memory Properties : [IORT Memory Access Properti= es] [0B0h 0176 4] Cache Coherency : 00000001 [0B4h 0180 1] Hints (decoded below) : 00 Transient : 0 Write Allocate : 0 Read Allocate : 0 Override : 0 [0B5h 0181 2] Reserved : 0000 [0B7h 0183 1] Memory Flags (decoded below) : 03 Coherency : 1 Device Attribute : 1 [0B8h 0184 4] ATS Attribute : 00000000 [0BCh 0188 4] PCI Segment Number : 00000000 [0C0h 0192 1] Memory Size Limit : 40 [0C1h 0193 2] PASID Capabilities : 0000 [0C3h 0195 1] Reserved : 00 [0C4h 0196 4] Input base : 00000000 [0C8h 0200 4] ID Count : 000001FF [0CCh 0204 4] Output Base : 00000000 [0D0h 0208 4] Output Reference : 00000048 [0D4h 0212 4] Flags (decoded below) : 00000000 Single Mapping : 0 [0D8h 0216 4] Input base : 00001000 [0DCh 0220 4] ID Count : 000000FF [0E0h 0224 4] Output Base : 00001000 [0E4h 0228 4] Output Reference : 00000048 [0E8h 0232 4] Flags (decoded below) : 00000000 Single Mapping : 0 [0ECh 0236 4] Input base : 00000200 [0F0h 0240 4] ID Count : 00000DFF [0F4h 0244 4] Output Base : 00000200 [0F8h 0248 4] Output Reference : 00000030 [0FCh 0252 4] Flags (decoded below) : 00000000 Single Mapping : 0 [100h 0256 4] Input base : 00001100 [104h 0260 4] ID Count : 0000EEFF [108h 0264 4] Output Base : 00001100 [10Ch 0268 4] Output Reference : 00000030 [110h 0272 4] Flags (decoded below) : 00000000 Single Mapping : 0 For the smmuv3-dev test case, IORT has 2 SMMUV3 nodes, 1 RC node and 1 ITS node. RC node features 4 ID mappings. 2 of them target the 2 SMMU nodes while the others targets the ITS. pcie.0 -> {SMMU0} -> {ITS} {RC} pcie.1 -> {SMMU1} -> {ITS} pcie.2 -> {ITS} [all other ids] -> {ITS} ... [030h 0048 1] Type : 00 [031h 0049 2] Length : 0018 [033h 0051 1] Revision : 01 [034h 0052 4] Identifier : 00000000 [038h 0056 4] Mapping Count : 00000000 [03Ch 0060 4] Mapping Offset : 00000000 [040h 0064 4] ItsCount : 00000001 [044h 0068 4] Identifiers : 00000000 [048h 0072 1] Type : 04 [049h 0073 2] Length : 0058 [04Bh 0075 1] Revision : 04 [04Ch 0076 4] Identifier : 00000001 [050h 0080 4] Mapping Count : 00000001 [054h 0084 4] Mapping Offset : 00000044 [058h 0088 8] Base Address : 000000000C000000 [060h 0096 4] Flags (decoded below) : 00000001 COHACC Override : 1 HTTU Override : 0 Proximity Domain Valid : 0 [064h 0100 4] Reserved : 00000000 [068h 0104 8] VATOS Address : 0000000000000000 [070h 0112 4] Model : 00000000 [074h 0116 4] Event GSIV : 00000090 [078h 0120 4] PRI GSIV : 00000091 [07Ch 0124 4] GERR GSIV : 00000093 [080h 0128 4] Sync GSIV : 00000092 [084h 0132 4] Proximity Domain : 00000000 [088h 0136 4] Device ID Mapping Index : 00000000 [08Ch 0140 4] Input base : 00000000 [090h 0144 4] ID Count : 0000FFFF [094h 0148 4] Output Base : 00000000 [098h 0152 4] Output Reference : 00000030 [09Ch 0156 4] Flags (decoded below) : 00000000 Single Mapping : 0 [0A0h 0160 1] Type : 04 [0A1h 0161 2] Length : 0058 [0A3h 0163 1] Revision : 04 [0A4h 0164 4] Identifier : 00000002 [0A8h 0168 4] Mapping Count : 00000001 [0ACh 0172 4] Mapping Offset : 00000044 [0B0h 0176 8] Base Address : 000000000C020000 [0B8h 0184 4] Flags (decoded below) : 00000001 COHACC Override : 1 HTTU Override : 0 Proximity Domain Valid : 0 [0BCh 0188 4] Reserved : 00000000 [0C0h 0192 8] VATOS Address : 0000000000000000 [0C8h 0200 4] Model : 00000000 [0CCh 0204 4] Event GSIV : 00000094 [0D0h 0208 4] PRI GSIV : 00000095 [0D4h 0212 4] GERR GSIV : 00000097 [0D8h 0216 4] Sync GSIV : 00000096 [0DCh 0220 4] Proximity Domain : 00000000 [0E0h 0224 4] Device ID Mapping Index : 00000000 [0E4h 0228 4] Input base : 00000000 [0E8h 0232 4] ID Count : 0000FFFF [0ECh 0236 4] Output Base : 00000000 [0F0h 0240 4] Output Reference : 00000030 [0F4h 0244 4] Flags (decoded below) : 00000000 Single Mapping : 0 [0F8h 0248 1] Type : 02 [0F9h 0249 2] Length : 0074 [0FBh 0251 1] Revision : 03 [0FCh 0252 4] Identifier : 00000003 [100h 0256 4] Mapping Count : 00000004 [104h 0260 4] Mapping Offset : 00000024 [108h 0264 8] Memory Properties : [IORT Memory Access Properti= es] [108h 0264 4] Cache Coherency : 00000001 [10Ch 0268 1] Hints (decoded below) : 00 Transient : 0 Write Allocate : 0 Read Allocate : 0 Override : 0 [10Dh 0269 2] Reserved : 0000 [10Fh 0271 1] Memory Flags (decoded below) : 03 Coherency : 1 Device Attribute : 1 [110h 0272 4] ATS Attribute : 00000000 [114h 0276 4] PCI Segment Number : 00000000 [118h 0280 1] Memory Size Limit : 40 [119h 0281 2] PASID Capabilities : 0000 [11Bh 0283 1] Reserved : 00 [11Ch 0284 4] Input base : 00000000 [120h 0288 4] ID Count : 000001FF [124h 0292 4] Output Base : 00000000 [128h 0296 4] Output Reference : 00000048 [12Ch 0300 4] Flags (decoded below) : 00000000 Single Mapping : 0 [130h 0304 4] Input base : 00001000 [134h 0308 4] ID Count : 000000FF [138h 0312 4] Output Base : 00001000 [13Ch 0316 4] Output Reference : 000000A0 [140h 0320 4] Flags (decoded below) : 00000000 Single Mapping : 0 [144h 0324 4] Input base : 00000200 [148h 0328 4] ID Count : 00000DFF [14Ch 0332 4] Output Base : 00000200 [150h 0336 4] Output Reference : 00000030 [154h 0340 4] Flags (decoded below) : 00000000 Single Mapping : 0 [158h 0344 4] Input base : 00001100 [15Ch 0348 4] ID Count : 0000EEFF [160h 0352 4] Output Base : 00001100 [164h 0356 4] Output Reference : 00000030 [168h 0360 4] Flags (decoded below) : 00000000 Single Mapping : 0 Note: DSDT changes are not described here as it is not impacted by the way the SMMUv3 is instantiated. Reviewed-by: Jonathan Cameron Reviewed-by: Eric Auger Tested-by: Eric Auger Tested-by: Nicolin Chen Signed-off-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Reviewed-by: Donald Dutile Reviewed-by: Nicolin Chen Message-id: 20250829082543.7680-12-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- tests/qtest/bios-tables-test-allowed-diff.h | 4 ---- tests/data/acpi/aarch64/virt/DSDT.smmuv3-dev | Bin 0 -> 10230 bytes tests/data/acpi/aarch64/virt/DSDT.smmuv3-legacy | Bin 0 -> 10230 bytes tests/data/acpi/aarch64/virt/IORT.smmuv3-dev | Bin 0 -> 364 bytes tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy | Bin 0 -> 276 bytes 5 files changed, 4 deletions(-) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index 2e3e3ccdcec..dfb8523c8bf 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,5 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/aarch64/virt/DSDT.smmuv3-legacy", -"tests/data/acpi/aarch64/virt/DSDT.smmuv3-dev", -"tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy", -"tests/data/acpi/aarch64/virt/IORT.smmuv3-dev", diff --git a/tests/data/acpi/aarch64/virt/DSDT.smmuv3-dev b/tests/data/acpi= /aarch64/virt/DSDT.smmuv3-dev index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..53d4c07f423886d8c4b57f1da64= 98eef5a08b556 100644 GIT binary patch literal 10230 zcmdU#&2OAn8O866$FcqTBjb<6vE#%pl=3D2+@XYf~qK+TFQ8yd7pcpb7rpN z-`w#=3DcjNBAz8pgJ@9TH+o86`L?{4Qy_EiZX;6A?BfB%!}JH76DZ|Bi`-e@$2dp9>X z#@F)gO)IX1;oe)D8)4_s)%;Goyw+*oY&4q9{M!)v7X>8X^)*PKSnYozz- z>6FGdoW^ypk>01XDUAzG=3D{3^(bS|Z_>@+sLMtYylr!+1)jayzL zy-&}kG%h=3DhH@!xBpDv^{R-ML{*GTWvb199hPNVHKR?_?Qd`jarr*YeBr1$A!O5+Wu zai_1bS=3D(AJ>0|r$b|Y_GKZcKOW1fj@l$`TL_M7T6kIkIubvxb4&Lc|o?L<-rAztd` zgjDg^vD7WN>i_gaQh*V!^`(SX@mQ?Y|0#;K3`)G#D+#UQv16_FZ?^ODe-~)2HCFA} z$_*xqYQ?Jc_1oDJkrLm!cRQ1F+3CIT^YFc}6gI*S!q39}@O}Fpu#|AN-MKrx_0#O( z)M#z=3D=3DqTV73B~=3D2-EW4eF+84C@uZZ+fE6oYYP>dfbYw_c^z|#Ovc`$x8rNBCSz@K> zv)4$n=3DoVW`h(rO!DO2r=3Dn zIme=3D$hQ&Uol|JWqlyf}FIUeV<(&wCra!y1!4WoTdD}BzBQO=3DW5&XaLYD}7FT%UA4i z?&5ls)3Dp;w9@CCjB-v!IVaC-r(wF!X{FCO9p#*ka!$uNt@Jr(qMS2P zPQ!Yi(@LN7RFv~nl=3DD=3Da(@LN7bd>XSl+)e@_?%YyoU>8R*(m31oYP95)82r)*Yix2 z)801toL2grb5YK@DCb<9(@LLnKFT>C<+QgMKBtvF=3Dh-Od*(m4PIH#39=3DR%ZoA@H&T~=3DDb8${9ea`by&ht@DdmH0(TIq8xMmZOwoQrWzD~p^3mYm9_9*>8r z{dZ))XqW7^Vka{*TSL7&-MseXLC81mH4knN?*C|VI;-!r|F-h)#f57h-+O=3DU&#!;_ z!zT~2nl&uj_hI|KvWJ`94|cP~-Glnm{ri<)VL7ig52l~)^K$W69ar{t@yMUXiiaT8 zJbW6h(4%>J`I_m{kVFtYz%IGh})RB&U5NJdc27YAd_ z#tVb7<_m6GLf6UHXjA;sBOb!5JY9)-xJYh^z0Aq3h7*i`@Oy&t=3D zngSS;1HhPC31c!(7}FHMm>dAc)JhnWdBT{c0LJ71Fs4?*n9LK#GzBmw2Y@lP62@en zFs3PhF*yK?sg*D$^Mo-?0gTB3U`(xqF_|ZfX$oLW4gh0nC5*{DVN6p1V{!l(Q!8Oi z<_Tk(0vMA6z?fPIV=3D_+|(-gp%9011DN*I%Q!kDH2#^eAnrdGn3%oD~m1u!NDfHAca z#$=3Du_hAGd$SREgheJ)|__@lz;+{hC8W24V@GG-qp79YSwQqOfVW*;pkq@M3&tns2? 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3e760775880sm23033286f8f.2.2025.09.16.11.06.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 11:06:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758046015; x=1758650815; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=YhTnH9wNwgFi/SzqMsXE+M8cpU3Hir6pM6j4YcAhL7s=; b=LO8uo1GvGtYnkFV9K+FNRmnDdYszL7NfgoMtYT0baM1x2KkCXSUs0iR9aA/8VV1FZ5 +byx+N2U5ZA5AZKHvg5bo98f5ryLRFsZ2kBw385pSYjkinYwHwMuZxfLr3aY5BFH8hq7 9qiSZusGmJKqCFdJuO4tVAIsiKqhcd/Q85hC5rtJqziWj+mUJwds/uyMy7a3/8fbJRFJ 1cKjSmehNEj5DXDAXfNsVhR0NByTwUVnj1R4SbNyFK6f/7E/8A8z43ZjhVf2pDoWq+Mk fyh2YHa7owGo9rRDjLcDxBZHrFcS0Ideaz+ENBJZ/L/I68W/rC6hL5dBXcs4E39ZuvLh bHhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758046015; x=1758650815; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YhTnH9wNwgFi/SzqMsXE+M8cpU3Hir6pM6j4YcAhL7s=; b=dpGdUva/aAqlqtmBz1vXC6Tlksx5po6T1T10DisPDtqzGGRH4wTgw0+oY8ZXtmSbYG ZBmaVehpABYNh7MK/3rtSOM/a1RdsSco0cIRivkFnhLmaXMgYfFfEmedTtl3YhtNFsb0 uZe+5TEIp7cM0ljL8PeFPYZ7k4GvGRKLftDJRfiuj4DZBnuRnIgtbLqMVE23l8LH7l+R 1Mq75ZC2E9tbpXEQSNPK5Yjg9rddvZQX6cZvSvbCiMB37OWl+oM7uK4iWuD9bVksgVwL UigrRISiqqnT5PZ5YpZqslO+XwPvCSutmljkyqgxjaQ8KDMWIt+CxLHN8huOStoXijMz oXsA== X-Gm-Message-State: AOJu0YzJQ4rXcPYwxxSSHEPHeVqVwNJh4+vPcgQxMzDUbVBQnBSSG8ay KQ33joRW/GPqyVfN5nXCnqJpfNUYLiIln4FXcrEFzWVLNBSISDFLeOD7c3bTnOuMRNKaM9Ik+bU Eh/EX X-Gm-Gg: ASbGncuqKWevo8zclL8vpkwFRvWguZM00KAJzN128MRGmd+g1Vb3HWhWpIKHrxCyaiJ q/sQTqXv1X3qfJSrMsGAndm3JUJgKR4xuNPI/btj2msex8XZNRH6xgKgVddU+ztgDcH4g8zs6pX 98xlA8oEf21QAsll/tLih0j1lplqGn3hBi1O0X8Ah4F86/zhDsY1H3n8lbviSlCcbAJ25yVNT9k LCx0k+SNc/C3do9LtrF2o3QWbkRJ9gXPSOdbwnkGmnxulk/p9zTVZMrr+oHpywA6FVmbSoUAS62 eMtalagXCyIDmmW0gG7p1Ww0m02cl8UqfgbISOrpXfKAheyRVbmcJpbSnThmlN7xHQYvX1ZNs7k s5JQ9NVcAISBSv6zd0hDbrxEbhv6c X-Google-Smtp-Source: AGHT+IHLVxow+Qy6wIDHyeTHFJswQ1vPcLVHUqyMk46fDzv83hzqs7q8c1x4epDpIi3oMABGZAUToA== X-Received: by 2002:a05:6000:2289:b0:3e5:47a9:1c7a with SMTP id ffacd0b85a97d-3e765a157b7mr16345160f8f.62.1758046014766; Tue, 16 Sep 2025 11:06:54 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 36/36] hw/usb/network: Remove hardcoded 0x40 prefix in STRING_ETHADDR response Date: Tue, 16 Sep 2025 19:06:10 +0100 Message-ID: <20250916180611.1481266-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916180611.1481266-1-peter.maydell@linaro.org> References: <20250916180611.1481266-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758046175529116601 From: St=C3=A9phane Graber USB NICs have a "40:" prefix hardcoded for all MAC addresses when we return the guest the MAC address if it queries the STRING_ETHADDR USB string property. This doesn't match what we use for the OID_802_3_PERMANENT_ADDRESS or OID_802_3_CURRENT_ADDRESS OIDs for NDIS, or the MAC address we actually use in the QEMU networking code to send/receive packets for this device, or the NIC info string we print for users. In all those other places we directly use s->conf.macaddr.a, which is the full thing the user asks for. This overrides user-provided configuration and leads to an inconsistent experience. I couldn't find any documented reason (comment or git commits) for this behavior. It seems like everyone is just expecting the MAC address to be fully passed through to the guest, but it isn't. This may have been a debugging hack that accidentally made it through to the accepted patch: it has been in the code since it was originally added back in 2008. This is also particularly problematic as the "40:" prefix isn't a reserved prefix for MAC addresses (IEEE OUI). There are a number of valid allocations out there which use this prefix, meaning that QEMU may be causing MAC address conflicts. Cc: qemu-stable@nongnu.org Fixes: 6c9f886ceae5b ("Add CDC-Ethernet usb NIC (original patch from Thomas= Sailer)" Signed-off-by: St=C3=A9phane Graber Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2951 Reviewed-by: Daniel P. Berrang=C3=A9 [PMM: beef up commit message based on mailing list discussion] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/usb/dev-network.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/usb/dev-network.c b/hw/usb/dev-network.c index 81cc09dcac9..1df24541814 100644 --- a/hw/usb/dev-network.c +++ b/hw/usb/dev-network.c @@ -1383,7 +1383,7 @@ static void usb_net_realize(USBDevice *dev, Error **e= rrp) qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); snprintf(s->usbstring_mac, sizeof(s->usbstring_mac), "%02x%02x%02x%02x%02x%02x", - 0x40, + s->conf.macaddr.a[0], s->conf.macaddr.a[1], s->conf.macaddr.a[2], s->conf.macaddr.a[3], --=20 2.43.0