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([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2651d2df15esm73459905ad.45.2025.09.16.07.23.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 07:23:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758032588; x=1758637388; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ssqw9JSyA9Os3mkiUL2PAFRSciY/JuSbUEvZwlSWe9U=; b=dldX1MLe2ufOcP8WXKfuVaAfcQRRwvOpGfmFEwLokCWRpOqPg1yWJTaVB9Z1s35/Ok XuERLnYln41psek6rZDLfjUApM5ceJyKC0oP024gyrhEFlRDxDBUh08AgUuL+brabU1h 0oAZCWjFgKLRRi341cEEIPqLBaHEiREpVjXy3cM1FGGpQ9yQ6EdXYD/V8yY93PBwvuRI hM78N2xiQCDsb429HjFxFZuJ8wurREiTis4fGfA6CigvBs7HXy0hMTUdh+uV6YNmFqxn QKMZeW8nexqOf0GSnTuujCJ1HdHQj3vt+LoV8X/+egSrL2p2SfVFUje+YlOPqmsReD7G MR6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758032588; x=1758637388; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ssqw9JSyA9Os3mkiUL2PAFRSciY/JuSbUEvZwlSWe9U=; b=B5NSzpEtAHrp9uFAa5Pr8ARZ3Jincd1DaUY+uezV5uPlxe84aRChb4JhJHuLP3kWd+ NJucBRrONmjaawyKTVrMuY02kyXuySKFPSh7RXizIJKf9vZjdETbio9/POTBqMRNloIm O3QfGfOPCzJti1ZuD37TDQJitFPawOjchXCsFqQpqBb6VsXUq8RCVfLsfQRpFI+noWQ5 vsf7fPJ5gnaYSlXoeOlinq+BQOecP9wkWVkrCzQjlmLHbTUu6S8RG6DKBC6l1brCfhrs 8ywKJ4bkLcGK2OT5COnQeXSBOP5Hz/fTj+DLhpxhgl7lGZhnGiogxNu0ukHJduBOy7c9 LNpw== X-Gm-Message-State: AOJu0Yzxv5eDrbAujzqycrweMf9ALVL/LiSEfNC6X50TCBOQoBby34V/ e3O634vkdfmCb3zBg296Tt/Bk285zBWO2oAMA/bl4edBMcuyH0jdsVydtQ76BYUZzVlCmNKfk85 QEZcE X-Gm-Gg: ASbGncs8unttQt3wYlU31BB2lzPFbT7tw2MzGcazVFu70abRYAxMjMzRdJlRjiRDmzY hKjAn/z4IHK6c79ZEbEB8ASWpbTAaFW8XLEPM6HLihJjKKkGHCvrBSzCtd+2jreNiX2DWufy709 GY9LDyjTq2pkWkIUsr9r9DLf2qnW2A5EGWnwBqmVP2LsMtnXyDXmWSMv9d8hKQqZWjjWiCMTHY7 2YIBfGZflXQEvNiRVmieSQCVH2HdG2+VB1ELJNH6Y5c9d2l1+qe9EufkIgXHmwanXwmtuDTDAnk LiCuQe0kMvbZubqfkGyxyOzNmUoRnIn3NS/ICLDstzjRa+cN0oG1tSq7Wz3rSgqV9W+ybV66u8Q 7iOM5Z75wnw4pPVjEsG/mkhy37mjd3yUrPLgY9RU= X-Google-Smtp-Source: AGHT+IFUh08MekGrGxfGO14Tb+bgO7mr2vx2eeT/+cc4MliUhQJVTfYpcMysvkAtOT9+ypVxw2DPyw== X-Received: by 2002:a17:902:e54e:b0:261:1521:17a8 with SMTP id d9443c01a7336-26115211986mr160460175ad.16.1758032587841; Tue, 16 Sep 2025 07:23:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, Manos Pitsidianakis Subject: [PATCH v2 35/36] target/arm: Rename some cpreg to their aarch64 names Date: Tue, 16 Sep 2025 07:22:36 -0700 Message-ID: <20250916142238.664316-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916142238.664316-1-richard.henderson@linaro.org> References: <20250916142238.664316-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758032757234116600 Content-Type: text/plain; charset="utf-8" Rename those registers which will have FOO_EL12 aliases. Reviewed-by: Manos Pitsidianakis Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/helper.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8074c50241..4172fcaa21 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -671,7 +671,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { */ { .name =3D "WFAR", .cp =3D 15, .crn =3D 6, .crm =3D 0, .opc1 =3D 0, .= opc2 =3D 1, .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0, }, - { .name =3D "CPACR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, + { .name =3D "CPACR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 1, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, .accessfn =3D cpac= r_access, .fgt =3D FGT_CPACR_EL1, .nv2_redirect_offset =3D 0x100 | NV2_REDIR_NV1, @@ -2018,7 +2018,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { .resetfn =3D arm_gt_cntfrq_reset, }, /* overall control: mostly access permissions */ - { .name =3D "CNTKCTL", .state =3D ARM_CP_STATE_BOTH, + { .name =3D "CNTKCTL_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 14, .crm =3D 1, .opc2 =3D 0, .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_cntkctl), @@ -3077,8 +3077,8 @@ static uint64_t mpidr_read(CPUARMState *env, const AR= MCPRegInfo *ri) } =20 static const ARMCPRegInfo lpae_cp_reginfo[] =3D { - /* NOP AMAIR0/1 */ - { .name =3D "AMAIR0", .state =3D ARM_CP_STATE_BOTH, + /* AMAIR0 is mapped to AMAIR_EL1[31:0] */ + { .name =3D "AMAIR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 10, .crm =3D 3, .opc1 =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_AMAIR_EL1, @@ -4469,11 +4469,11 @@ static void define_arm_vh_e2h_redirects_aliases(ARM= CPU *cpu) =20 static const struct E2HAlias aliases[] =3D { { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0), - "SCTLR", "SCTLR_EL2", "SCTLR_EL12" }, + "SCTLR_EL1", "SCTLR_EL2", "SCTLR_EL12" }, { K(3, 0, 1, 0, 3), K(3, 4, 1, 0, 3), K(3, 5, 1, 0, 3), "SCTLR2_EL1", "SCTLR2_EL2", "SCTLR2_EL12", isar_feature_aa64_sct= lr2 }, { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2), - "CPACR", "CPTR_EL2", "CPACR_EL12" }, + "CPACR_EL1", "CPTR_EL2", "CPACR_EL12" }, { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0), "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" }, { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1), @@ -4497,13 +4497,13 @@ static void define_arm_vh_e2h_redirects_aliases(ARM= CPU *cpu) { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0), "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" }, { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0), - "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" }, + "AMAIR_EL1", "AMAIR_EL2", "AMAIR_EL12" }, { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0), - "VBAR", "VBAR_EL2", "VBAR_EL12" }, + "VBAR_EL1", "VBAR_EL2", "VBAR_EL12" }, { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1), "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" }, { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0), - "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" }, + "CNTKCTL_EL1", "CNTHCTL_EL2", "CNTKCTL_EL12" }, =20 /* * Note that redirection of ZCR is mentioned in the description @@ -7145,7 +7145,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) =20 if (arm_feature(env, ARM_FEATURE_VBAR)) { static const ARMCPRegInfo vbar_cp_reginfo[] =3D { - { .name =3D "VBAR", .state =3D ARM_CP_STATE_BOTH, + { .name =3D "VBAR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 12, .crm =3D 0, .opc1 =3D 0, .opc2 =3D= 0, .access =3D PL1_RW, .writefn =3D vbar_write, .accessfn =3D access_nv1, @@ -7161,7 +7161,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) /* Generic registers whose values depend on the implementation */ { ARMCPRegInfo sctlr =3D { - .name =3D "SCTLR", .state =3D ARM_CP_STATE_BOTH, + .name =3D "SCTLR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_SCTLR_EL1, --=20 2.43.0