From nobody Sun Sep 28 17:07:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758033065; cv=none; d=zohomail.com; s=zohoarc; b=KsP1ibNo1uLfWiqZN0r+0VrxVcr5YSac0BVVpFL0Ofo33mqx33tDsH0iCkFCuLvnXwxrK/D4rFuByKo/QONvTmj5zkGf6V59GH08xET4wuhUmoWNPhHjqONxFfBQpnnSzlaLoqHCpIwv28X1PumfWtCrSou6YCWBD5lpbxiPuEU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758033065; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=izULxd/xPJJeJxDcsNdLsFI/0M1j8/7oFIq6UaqJp58=; b=ByYEmbXqSi2XvC+EYy8PtD3ys2/RYZHZ4QSLzZF4kznk5Zsp5Muk14DKz1GeY44kbEN61a7HklzgoBttNAn8aShoXxZ1nuDCFwBXVj0D40WzNU6rTnXoDNfWwwDmAV8sieLSlOAVCzacRa4DBgrVEO8eGJGpMF7g5YQq2bWK6T4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758033065606199.30353853933445; Tue, 16 Sep 2025 07:31:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uyWbW-0006l2-7z; Tue, 16 Sep 2025 10:24:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uyWaZ-0005wx-LF for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:23:23 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uyWaT-0008M5-O2 for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:23:23 -0400 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-267f0fe72a1so2622805ad.2 for ; Tue, 16 Sep 2025 07:22:58 -0700 (PDT) Received: from stoup.. ([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2651d2df15esm73459905ad.45.2025.09.16.07.22.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 07:22:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758032577; x=1758637377; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=izULxd/xPJJeJxDcsNdLsFI/0M1j8/7oFIq6UaqJp58=; b=xE3c/8hVc0znAzW5TNDIZmEE5udrBoMeXcoLsOyeR0ksqoXe3FV4ET/46MLYJO2VX3 pKbkYhRxHx07MBQjmtWFALQl+mgMn6CX5pz1LCkQPMxvFaeFaG0MgIzbak5y/f3hmLpf 4dmlJ8xl3vO3QtJKy4dgFWd82qyopvNxH/e6k8045KFmNVy5IrcEP/I4cOqyfvIft1ja +N4krz7g4MYTdWwBFCe1b36VbiKFpScD1YtijIHS8lC2ykTqcqyN68y6rcZDJd5W2k7p b8JZ81ZZ7RE+f6SV5eoN+7MxyHddrsHiB/VoRIgwByIHVoBi1OeW8N/1e/Cge/vjj8TB 3Puw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758032577; x=1758637377; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=izULxd/xPJJeJxDcsNdLsFI/0M1j8/7oFIq6UaqJp58=; b=sUOaYac34QzA/sZeAFg+nTiAQBuyTGWY9xKzOKZKXMmBEvkxmfSlEUAV2wlj9EgxSp w59lK3bFBH79B49SiDKLK9y7F7TPRtKBPrjkeJZuCfvxNIQ2/EkRYrD49iA1KyxBeWws abY/GsH/iHcd5Mg1ucCnGhor56hu3ngL4RwUv4h/908/xmIBzGHisNF9XdCcXxWBwnw0 We2oasOzhA6IjiSeQ3PMB6CmND1PG/ii8KA2BMgLtIdl76xhDW7vugEhtPqXBuD1OvIg 1pNJrJon/wgqjBEWQZHTwfdBbui15ZP6kwzA5sNaQ+adbzomZhGZ3EYP2hKCmzmWmL8v MC3g== X-Gm-Message-State: AOJu0Yyk+oPIetQ+dtNwSWuRKniW0mJqqKc+IduKHObg8UUz5va6f/4l tyTeiBNVR0Lh1x58UzvyvMeF1V2YwQfGN6DL4JREa2zmbPA1Kj/WZSDrUuCvW4UgN9dsQ9u/Y+L ANHi2 X-Gm-Gg: ASbGncs6fkPYnUjz9oBZd+AHY0jJMEgp3QqJDQPEFP+PjjhpBUsQajx22E6zUCDGsYb V3afZoPiykvbIouskVav4084v9I6l33u0QmM80iYHiVhu1FY9D6tjfbTDsQcdXHQOaeRm5YFPSi eWk8ghzXJ4bWL5rlFYxW6I0hzcpdC/FBOymP8LbHR2JM5ZsgyJANeAJUG6T2ZCxxji9IjPwEKGA LahIVCb4/jmL01ad5BNe88VJYgbpW0h8D6ncT9NXomZ0bSL+nTMVhh8SniDVebui2wgRZTnmmXu EAW9/FXKy2DXvmIl2EbchPhmjFgrFw+kr8ioXXu7CNxgWnalBXNzrERncsjNAD8hHSlSD8qmR2r mR4auI+NLlluH3uVXNm279GkP1LgK X-Google-Smtp-Source: AGHT+IFiZ0et+wGkypTtaLHsvfFfy4cXl0yQB4YrPuEz2PqUthSF2q8whtiF+RGsrr+SYyCw9PN5Qg== X-Received: by 2002:a17:903:32ca:b0:267:f4e4:e4df with SMTP id d9443c01a7336-267f4e4e671mr10240255ad.57.1758032577380; Tue, 16 Sep 2025 07:22:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v2 23/36] target/arm: Move cpreg elimination to define_one_arm_cp_reg Date: Tue, 16 Sep 2025 07:22:24 -0700 Message-ID: <20250916142238.664316-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916142238.664316-1-richard.henderson@linaro.org> References: <20250916142238.664316-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758033067677116600 Content-Type: text/plain; charset="utf-8" Eliminate unused registers earlier, so that by the time we arrive in add_cpreg_to_hashtable we never skip. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/helper.c | 123 +++++++++++++++++++++++--------------------- 1 file changed, 64 insertions(+), 59 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0eedbacc2b..4a109a113d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7432,7 +7432,6 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, bool is64 =3D r->type & ARM_CP_64BIT; bool ns =3D secstate & ARM_CP_SECSTATE_NS; size_t name_len; - bool make_const; =20 switch (state) { case ARM_CP_STATE_AA32: @@ -7453,32 +7452,6 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons= t ARMCPRegInfo *r, } } =20 - /* - * Eliminate registers that are not present because the EL is missing. - * Doing this here makes it easier to put all registers for a given - * feature into the same ARMCPRegInfo array and define them all at onc= e. - */ - make_const =3D false; - if (arm_feature(env, ARM_FEATURE_EL3)) { - /* - * An EL2 register without EL2 but with EL3 is (usually) RES0. - * See rule RJFFP in section D1.1.3 of DDI0487H.a. - */ - int min_el =3D ctz32(r->access) / 2; - if (min_el =3D=3D 2 && !arm_feature(env, ARM_FEATURE_EL2)) { - if (r->type & ARM_CP_EL3_NO_EL2_UNDEF) { - return; - } - make_const =3D !(r->type & ARM_CP_EL3_NO_EL2_KEEP); - } - } else { - CPAccessRights max_el =3D (arm_feature(env, ARM_FEATURE_EL2) - ? PL2_RW : PL1_RW); - if ((r->access & max_el) =3D=3D 0) { - return; - } - } - /* Combine cpreg and name into one allocation. */ name_len =3D strlen(name) + 1; r2 =3D g_malloc(sizeof(*r2) + name_len); @@ -7496,38 +7469,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons= t ARMCPRegInfo *r, r2->state =3D state; r2->secure =3D secstate; =20 - if (make_const) { - /* This should not have been a very special register to begin. */ - int old_special =3D r2->type & ARM_CP_SPECIAL_MASK; - assert(old_special =3D=3D 0 || old_special =3D=3D ARM_CP_NOP); - /* - * Set the special function to CONST, retaining the other flags. - * This is important for e.g. ARM_CP_SVE so that we still - * take the SVE trap if CPTR_EL3.EZ =3D=3D 0. - */ - r2->type =3D (r2->type & ~ARM_CP_SPECIAL_MASK) | ARM_CP_CONST; - /* - * Usually, these registers become RES0, but there are a few - * special cases like VPIDR_EL2 which have a constant non-zero - * value with writes ignored. - */ - if (!(r->type & ARM_CP_EL3_NO_EL2_C_NZ)) { - r2->resetvalue =3D 0; - } - /* - * ARM_CP_CONST has precedence, so removing the callbacks and - * offsets are not strictly necessary, but it is potentially - * less confusing to debug later. - */ - r2->readfn =3D NULL; - r2->writefn =3D NULL; - r2->raw_readfn =3D NULL; - r2->raw_writefn =3D NULL; - r2->resetfn =3D NULL; - r2->fieldoffset =3D 0; - r2->bank_fieldoffsets[0] =3D 0; - r2->bank_fieldoffsets[1] =3D 0; - } else { + { bool isbanked =3D r->bank_fieldoffsets[0] && r->bank_fieldoffsets[= 1]; =20 if (isbanked) { @@ -7692,6 +7634,8 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRe= gInfo *r) int opc2min =3D (r->opc2 =3D=3D CP_ANY) ? 0 : r->opc2; int opc2max =3D (r->opc2 =3D=3D CP_ANY) ? 7 : r->opc2; int cp =3D r->cp; + ARMCPRegInfo r_const; + CPUARMState *env =3D &cpu->env; =20 /* * AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless. @@ -7797,6 +7741,67 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPR= egInfo *r) } } =20 + /* + * Eliminate registers that are not present because the EL is missing. + * Doing this here makes it easier to put all registers for a given + * feature into the same ARMCPRegInfo array and define them all at onc= e. + */ + if (arm_feature(env, ARM_FEATURE_EL3)) { + /* + * An EL2 register without EL2 but with EL3 is (usually) RES0. + * See rule RJFFP in section D1.1.3 of DDI0487H.a. + */ + int min_el =3D ctz32(r->access) / 2; + if (min_el =3D=3D 2 && !arm_feature(env, ARM_FEATURE_EL2)) { + if (r->type & ARM_CP_EL3_NO_EL2_UNDEF) { + return; + } + if (!(r->type & ARM_CP_EL3_NO_EL2_KEEP)) { + /* This should not have been a very special register. */ + int old_special =3D r->type & ARM_CP_SPECIAL_MASK; + assert(old_special =3D=3D 0 || old_special =3D=3D ARM_CP_N= OP); + + r_const =3D *r; + + /* + * Set the special function to CONST, retaining the other = flags. + * This is important for e.g. ARM_CP_SVE so that we still + * take the SVE trap if CPTR_EL3.EZ =3D=3D 0. + */ + r_const.type =3D (r->type & ~ARM_CP_SPECIAL_MASK) | ARM_CP= _CONST; + /* + * Usually, these registers become RES0, but there are a f= ew + * special cases like VPIDR_EL2 which have a constant non-= zero + * value with writes ignored. + */ + if (!(r->type & ARM_CP_EL3_NO_EL2_C_NZ)) { + r_const.resetvalue =3D 0; + } + /* + * ARM_CP_CONST has precedence, so removing the callbacks = and + * offsets are not strictly necessary, but it is potential= ly + * less confusing to debug later. + */ + r_const.readfn =3D NULL; + r_const.writefn =3D NULL; + r_const.raw_readfn =3D NULL; + r_const.raw_writefn =3D NULL; + r_const.resetfn =3D NULL; + r_const.fieldoffset =3D 0; + r_const.bank_fieldoffsets[0] =3D 0; + r_const.bank_fieldoffsets[1] =3D 0; + + r =3D &r_const; + } + } + } else { + CPAccessRights max_el =3D (arm_feature(env, ARM_FEATURE_EL2) + ? PL2_RW : PL1_RW); + if ((r->access & max_el) =3D=3D 0) { + return; + } + } + for (int crm =3D crmmin; crm <=3D crmmax; crm++) { for (int opc1 =3D opc1min; opc1 <=3D opc1max; opc1++) { for (int opc2 =3D opc2min; opc2 <=3D opc2max; opc2++) { --=20 2.43.0