From nobody Sun Sep 28 17:07:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758032858650243.3488295999698; Tue, 16 Sep 2025 07:27:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uyWau-0006PJ-BE; Tue, 16 Sep 2025 10:23:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uyWab-0005yr-Nh for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:23:25 -0400 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uyWaT-0008LZ-Pz for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:23:25 -0400 Received: by mail-pg1-x529.google.com with SMTP id 41be03b00d2f7-b49b56a3f27so3256633a12.1 for ; Tue, 16 Sep 2025 07:22:56 -0700 (PDT) Received: from stoup.. ([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2651d2df15esm73459905ad.45.2025.09.16.07.22.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 07:22:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758032575; x=1758637375; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=O3ZI3DSvuSnKVozoGKOUzCAQ9C1UttOP4zYBt0a8luk=; b=Hfkk6nz7AEi+6meQ1pCJcKsOZhfM203qM1V9Z9M3IIzXYcRzP6St6j1swXBTWvpIhb wDo7/+5Qfrss+LHNJJzXk2U+6dE9/wArYY/4+JANu0K693z4HGwxzJUF9gk2qJeHHV/g rhYXoEko9sEAkTMO/UlS3uUmdADtyerogt0b9qfmFsFF60vPu4qoAiEwe+MaKoWrsnfk x8uql2P9oKRoak0DMgCAhvR1P7fUsI8iAb8CD3W8RNGUYtO4/oQcikqUzMh9afOkU+jX wky76JI865nbFvPvlwvfrfkZSW+VkyU0Occ4ZPFt3Ys4IRdjWxdiAuESpYhiwV0QYVUq ejsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758032575; x=1758637375; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=O3ZI3DSvuSnKVozoGKOUzCAQ9C1UttOP4zYBt0a8luk=; b=lZDMLIik+/5mLdi2IH2rJqEBNqxBJkmAHMdx9cn/IJCAvoSbCvjC8HVRroZpftGw8f CQACtK81V6jIwnRdwIvcMKBzKtm3penMpdHwijM4zUV45ROqoxT4ptwyr25ELYF3VaoX feqWbB0ks+OhGX+BRxE3n0rXHX+l7mVuGAQl6mEzeMXgdSCJQgaA9NxJdOfjBcw8nZlU OwhCxYK42jLXX+UUC2OppLdHJA/zQ0BzDTlfPN7bj4M+iyKKJsGqdxgU0CESCA2rKHcE YulU/MmOPg5olLrR88yqQYyoDCpuBzaJANnbkAKVY45rMnkU6UPElrWYDMImwV63drzN m1mQ== X-Gm-Message-State: AOJu0Yy87LuW0nqTWAQL17zhVLj/s3mdl71r6IFeSbS2ws5hmf6MJGas E8YkHxiFm2KJYHM8t6g9WUhCdKrJHLeOuPGelLV7bNCHsdjGyyqSQuSD69Gg1UeUbj+pwc8q9WK beha9 X-Gm-Gg: ASbGncuNeZVSNPHUplBAop6CH51/cXxT/NmwuEpUmsqskcAXTLy3no1EPSBDSjMTBTK 4O3WEZzOiDO7X0epittHq+I1JmT73A3gd8YRiEe827ZHbLFRCbqsCJ02vdJNm8IyY0e4xk00IaR +v0LdB6DHVpJOSVasfDfdQadxtU8i/DaIrmyrr3xcP2QaRi8Q9QIZm3XUBNoGSziGu/9SLeuUhp vMt99sK0juQg6xQTn6QAR7AYaJz7nk8zCyVQAgEGB2kb/aOWeUCVzM5dH9CiVjaZbnmyZ4z7dU/ l7DSC5gwx5Ir5rlbgN58j489bhrmuxjAwXB7/AUVdYuxyb5ZHnNzKXlT3UOWogEu2m05WIS7qTV b0NZDXpooiFIexLTd3rrgfxUUiWmsrUi2HafzfDE= X-Google-Smtp-Source: AGHT+IEliu+Ux8ncYvtfLYROnFdzKeiFM8UHKSBUqvd3juzX+RrflFEdZz1RIIhhHxfDG7KCpF0jzA== X-Received: by 2002:a17:903:230d:b0:263:671e:397b with SMTP id d9443c01a7336-263671e3beemr122575215ad.7.1758032575412; Tue, 16 Sep 2025 07:22:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v2 20/36] target/arm: Split out add_cpreg_to_hashtable_aa{32, 64} Date: Tue, 16 Sep 2025 07:22:21 -0700 Message-ID: <20250916142238.664316-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916142238.664316-1-richard.henderson@linaro.org> References: <20250916142238.664316-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1758032860549116600 Content-Type: text/plain; charset="utf-8" The nesting level for the inner loop of define_one_arm_cp_reg was overly deep. Split out that code into two functions, for the AArch32 and AArch64 paths separately. Simplify the innermost loop to a switch statement over r->state. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/helper.c | 147 +++++++++++++++++++++++--------------------- 1 file changed, 76 insertions(+), 71 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8b63eacb91..ec78c8f08f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7612,6 +7612,66 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons= t ARMCPRegInfo *r, g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2); } =20 +static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, const ARMCPRegInfo *r, + int crm, int opc1, int opc2) +{ + /* + * Under AArch32 CP registers can be common + * (same for secure and non-secure world) or banked. + */ + char *name; + + assert(!(r->type & ARM_CP_ADD_TLBI_NXS)); /* aa64 only */ + + switch (r->secure) { + case ARM_CP_SECSTATE_S: + case ARM_CP_SECSTATE_NS: + add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, + r->secure, crm, opc1, opc2, r->name); + break; + case ARM_CP_SECSTATE_BOTH: + name =3D g_strdup_printf("%s_S", r->name); + add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, + ARM_CP_SECSTATE_S, crm, opc1, opc2, name); + g_free(name); + add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, + ARM_CP_SECSTATE_NS, crm, opc1, opc2, r->nam= e); + break; + default: + g_assert_not_reached(); + } +} + +static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu, const ARMCPRegInfo *r, + int crm, int opc1, int opc2) +{ + if ((r->type & ARM_CP_ADD_TLBI_NXS) && + cpu_isar_feature(aa64_xs, cpu)) { + /* + * This is a TLBI insn which has an NXS variant. The + * NXS variant is at the same encoding except that + * crn is +1, and has the same behaviour except for + * fine-grained trapping. Add the NXS insn here and + * then fall through to add the normal register. + * add_cpreg_to_hashtable() copies the cpreg struct + * and name that it is passed, so it's OK to use + * a local struct here. + */ + ARMCPRegInfo nxs_ri =3D *r; + g_autofree char *name =3D g_strdup_printf("%sNXS", r->name); + + assert(nxs_ri.crn < 0xf); + nxs_ri.crn++; + if (nxs_ri.fgt) { + nxs_ri.fgt |=3D R_FGT_NXS_MASK; + } + add_cpreg_to_hashtable(cpu, &nxs_ri, ARM_CP_STATE_AA64, + ARM_CP_SECSTATE_NS, crm, opc1, opc2, name); + } + + add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA64, ARM_CP_SECSTATE_NS, + crm, opc1, opc2, r->name); +} =20 void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r) { @@ -7639,14 +7699,12 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCP= RegInfo *r) * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of * the register, if any. */ - int crm, opc1, opc2; int crmmin =3D (r->crm =3D=3D CP_ANY) ? 0 : r->crm; int crmmax =3D (r->crm =3D=3D CP_ANY) ? 15 : r->crm; int opc1min =3D (r->opc1 =3D=3D CP_ANY) ? 0 : r->opc1; int opc1max =3D (r->opc1 =3D=3D CP_ANY) ? 7 : r->opc1; int opc2min =3D (r->opc2 =3D=3D CP_ANY) ? 0 : r->opc2; int opc2max =3D (r->opc2 =3D=3D CP_ANY) ? 7 : r->opc2; - CPState state; =20 /* 64 bit registers have only CRm and Opc1 fields */ assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); @@ -7743,75 +7801,22 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCP= RegInfo *r) } } =20 - for (crm =3D crmmin; crm <=3D crmmax; crm++) { - for (opc1 =3D opc1min; opc1 <=3D opc1max; opc1++) { - for (opc2 =3D opc2min; opc2 <=3D opc2max; opc2++) { - for (state =3D ARM_CP_STATE_AA32; - state <=3D ARM_CP_STATE_AA64; state++) { - if (r->state !=3D state && r->state !=3D ARM_CP_STATE_= BOTH) { - continue; - } - if ((r->type & ARM_CP_ADD_TLBI_NXS) && - cpu_isar_feature(aa64_xs, cpu)) { - /* - * This is a TLBI insn which has an NXS variant. T= he - * NXS variant is at the same encoding except that - * crn is +1, and has the same behaviour except for - * fine-grained trapping. Add the NXS insn here and - * then fall through to add the normal register. - * add_cpreg_to_hashtable() copies the cpreg struct - * and name that it is passed, so it's OK to use - * a local struct here. - */ - ARMCPRegInfo nxs_ri =3D *r; - g_autofree char *name =3D g_strdup_printf("%sNXS",= r->name); - - assert(state =3D=3D ARM_CP_STATE_AA64); - assert(nxs_ri.crn < 0xf); - nxs_ri.crn++; - if (nxs_ri.fgt) { - nxs_ri.fgt |=3D R_FGT_NXS_MASK; - } - add_cpreg_to_hashtable(cpu, &nxs_ri, state, - ARM_CP_SECSTATE_NS, - crm, opc1, opc2, name); - } - if (state =3D=3D ARM_CP_STATE_AA32) { - /* - * Under AArch32 CP registers can be common - * (same for secure and non-secure world) or banke= d. - */ - char *name; - - switch (r->secure) { - case ARM_CP_SECSTATE_S: - case ARM_CP_SECSTATE_NS: - add_cpreg_to_hashtable(cpu, r, state, - r->secure, crm, opc1, o= pc2, - r->name); - break; - case ARM_CP_SECSTATE_BOTH: - name =3D g_strdup_printf("%s_S", r->name); - add_cpreg_to_hashtable(cpu, r, state, - ARM_CP_SECSTATE_S, - crm, opc1, opc2, name); - g_free(name); - add_cpreg_to_hashtable(cpu, r, state, - ARM_CP_SECSTATE_NS, - crm, opc1, opc2, r->nam= e); - break; - default: - g_assert_not_reached(); - } - } else { - /* - * AArch64 registers get mapped to non-secure inst= ance - * of AArch32 - */ - add_cpreg_to_hashtable(cpu, r, state, - ARM_CP_SECSTATE_NS, - crm, opc1, opc2, r->name); - } + for (int crm =3D crmmin; crm <=3D crmmax; crm++) { + for (int opc1 =3D opc1min; opc1 <=3D opc1max; opc1++) { + for (int opc2 =3D opc2min; opc2 <=3D opc2max; opc2++) { + switch (r->state) { + case ARM_CP_STATE_AA32: + add_cpreg_to_hashtable_aa32(cpu, r, crm, opc1, opc2); + break; + case ARM_CP_STATE_AA64: + add_cpreg_to_hashtable_aa64(cpu, r, crm, opc1, opc2); + break; + case ARM_CP_STATE_BOTH: + add_cpreg_to_hashtable_aa32(cpu, r, crm, opc1, opc2); + add_cpreg_to_hashtable_aa64(cpu, r, crm, opc1, opc2); + break; + default: + g_assert_not_reached(); } } } --=20 2.43.0