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Bake that in to the result directly. Remove CP_REG_ARM64_SYSREG_CP as unused. Reviewed-by: Manos Pitsidianakis Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpregs.h | 5 ++--- target/arm/kvm-consts.h | 3 --- target/arm/helper.c | 11 +++++------ target/arm/hvf/hvf.c | 3 +-- target/arm/tcg/translate-a64.c | 6 ++---- 5 files changed, 10 insertions(+), 18 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 7ebe404163..95b0b9c78e 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -187,9 +187,8 @@ enum { ((is64) << CP_REG_AA32_64BIT_SHIFT) | \ ((cp) << 16) | ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) =20 -#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ - (CP_REG_AA64_MASK | \ - ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ +#define ENCODE_AA64_CP_REG(crn, crm, op0, op1, op2) \ + (CP_REG_AA64_MASK | CP_REG_ARM64_SYSREG | \ ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h index fdb305eea1..54ae5da7ce 100644 --- a/target/arm/kvm-consts.h +++ b/target/arm/kvm-consts.h @@ -160,9 +160,6 @@ MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A53, KVM_ARM_= TARGET_CORTEX_A53); #define CP_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007 #define CP_REG_ARM64_SYSREG_OP2_SHIFT 0 =20 -/* No kernel define but it's useful to QEMU */ -#define CP_REG_ARM64_SYSREG_CP (CP_REG_ARM64_SYSREG >> CP_REG_ARM_COPROC_S= HIFT) - MISMATCH_CHECK(CP_REG_ARM64, KVM_REG_ARM64); MISMATCH_CHECK(CP_REG_ARM_COPROC_MASK, KVM_REG_ARM_COPROC_MASK); MISMATCH_CHECK(CP_REG_ARM_COPROC_SHIFT, KVM_REG_ARM_COPROC_SHIFT); diff --git a/target/arm/helper.c b/target/arm/helper.c index cc924adbc7..7094b63f82 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4542,7 +4542,7 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCP= U *cpu) }; =20 #define K(op0, op1, crn, crm, op2) \ - ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2) + ENCODE_AA64_CP_REG(crn, crm, op0, op1, op2) =20 static const struct E2HAlias aliases[] =3D { { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0), @@ -7451,10 +7451,9 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons= t ARMCPRegInfo *r, * in their AArch64 view (the .cp value may be non-zero for the * benefit of the AArch32 view). */ - if (cp =3D=3D 0 || r->state =3D=3D ARM_CP_STATE_BOTH) { - cp =3D CP_REG_ARM64_SYSREG_CP; - } - key =3D ENCODE_AA64_CP_REG(cp, r->crn, crm, r->opc0, opc1, opc2); + assert(cp =3D=3D 0 || r->state =3D=3D ARM_CP_STATE_BOTH); + cp =3D 0; + key =3D ENCODE_AA64_CP_REG(r->crn, crm, r->opc0, opc1, opc2); break; default: g_assert_not_reached(); @@ -7679,7 +7678,7 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRe= gInfo *r) } break; case ARM_CP_STATE_AA64: - assert(r->cp =3D=3D 0 || r->cp =3D=3D CP_REG_ARM64_SYSREG_CP); + assert(r->cp =3D=3D 0); break; default: g_assert_not_reached(); diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 694584cc13..6e67d89163 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1124,8 +1124,7 @@ static bool is_id_sysreg(uint32_t reg) =20 static uint32_t hvf_reg2cp_reg(uint32_t reg) { - return ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, - (reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK, + return ENCODE_AA64_CP_REG((reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK, (reg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK, (reg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK, (reg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK, diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 37bedc3780..a560ef0f42 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2466,8 +2466,7 @@ static void handle_sys(DisasContext *s, bool isread, unsigned int op0, unsigned int op1, unsigned int op= 2, unsigned int crn, unsigned int crm, unsigned int rt) { - uint32_t key =3D ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, - crn, crm, op0, op1, op2); + uint32_t key =3D ENCODE_AA64_CP_REG(crn, crm, op0, op1, op2); const ARMCPRegInfo *ri =3D get_arm_cp_reginfo(s->cp_regs, key); bool need_exit_tb =3D false; bool nv_trap_to_el2 =3D false; @@ -2603,8 +2602,7 @@ static void handle_sys(DisasContext *s, bool isread, * We don't use the EL1 register's access function, and * fine-grained-traps on EL1 also do not apply here. */ - key =3D ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, - crn, crm, op0, 0, op2); + key =3D ENCODE_AA64_CP_REG(crn, crm, op0, 0, op2); ri =3D get_arm_cp_reginfo(s->cp_regs, key); assert(ri); assert(cp_access_ok(s->current_el, ri, isread)); --=20 2.43.0