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([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2651d2df15esm73459905ad.45.2025.09.16.07.22.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 07:22:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758032570; x=1758637370; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=E7wtwSeAyVxAyxj0iVv+zvWRTdY6KuYaJg6kG2AFAzk=; b=NMH3JlZpOMFCDSsdTOVQg8mrKJ10xaCPwptCa/oEVWyxKCpfJTyNy0Ad20edfl4czr URy1aX2RLBQPuP0S2+Olh/ba2woqhfdDw7KZdv9j6KC3nvzitXNV+xKxg4U3qzqw7eVo eObjjjq0Jl2QW5QrlxAhuAuhLLQXQpF2OsmR6kIL0gZsuq1HBGBQLHCery0oqt8N2rFo 00fuQAxXTnF/JObfVivSyFnHNsQY2u6I9LCMc0nyhJ/hkH5jHpGj7BR6SRIojHHq0CrY dwNMs11JpVGT4rQ5kRh2IoLSub3poSuGIlheSbMPc7YUCBXTIqrIenlzkNpLVRH96Nrh f4fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758032570; x=1758637370; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=E7wtwSeAyVxAyxj0iVv+zvWRTdY6KuYaJg6kG2AFAzk=; b=LDvuVZK04nUzdDrpBhm72pPKZmYjrHwpBxa5JRBjzNiKafQecG6xRWE1x0ZBb4Lxy+ G6TL91M2nBXK847u/g0cpVaBl/KT1TCUTiFRUcf/Tmh0PY6Lf3zQ6O7lXiYTNtluX7DS 9QZRJEilxvoCUJqve/pbhV1KMV9qV0350Z9Q8dNaycVxrOKNo2YN6f2v8qRFrpKeu04h ELOdxgSRTyJSJiw+uUYWWB2nfx7o3fblAteWPtOhfG85XYVVRx4vXHcqg9anzkuF2LDG tK+NgxPtCEaRsijYFP5YW5m083uldvLvq2vWpB3C5sds2FuwTlg+tAiQxMeq9Lq+rvZK ezTw== X-Gm-Message-State: AOJu0YzuktMbzXB5Udxwh+AGreQQaAv4Zk0zIH/PW+e2qsG1Atjau9hH eMix+sfKPumgbOIcj2xtc/pgMqlCX5O0gCUoG0EDHpr2Sm3y1S9TiOy66onl0OqVcnpxuCih4be aPWyv X-Gm-Gg: ASbGncsBpTr1VZ+3sM0o0WCBnUXOGpdme2tUOwx2gTz6rjcxHZrai0BZh0bmWzytzGv rl4/9j918HNb5I5CRocXJb1ggjuV9IX6lgfInS1/1mVhtXqRTxm3YERRTX5G9mxIURA7hleFMOU ckagWlfU2c8coDJBHrqNu2ouEPzrxlYqyHV3Z8bwoG2+f0q7Nd92eaSMWhQwBJN+Feg/VkHjD5b bDHNy9wcKv6SCrSjxt7ycCi6c8xAJcjSMp7slXLxaor6dz9A8fV4f8DZo1QVH3alX+SlfO18pHQ TriHamJW9Kzs2ib20q1bpZnnay90ccuXP+z/sttBpma8O/phJ6aYNonQ0b6JIXcl/rgKqk52tn9 V8ohqhYYvymuChQAwr2zx+sdFtCRWnNqzfM7n/Jo= X-Google-Smtp-Source: AGHT+IHlUQdVirHYnlXUBJTD6+fcQ4MnjOs0iMqeNKU+4UIsiEzUhUmfnCxvbsiawthsc7RzdNupvw== X-Received: by 2002:a17:902:f68b:b0:264:ede2:683d with SMTP id d9443c01a7336-264ede26b0bmr117365955ad.56.1758032569582; Tue, 16 Sep 2025 07:22:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, Manos Pitsidianakis Subject: [PATCH v2 12/36] target/arm: Drop define_one_arm_cp_reg_with_opaque Date: Tue, 16 Sep 2025 07:22:13 -0700 Message-ID: <20250916142238.664316-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916142238.664316-1-richard.henderson@linaro.org> References: <20250916142238.664316-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758032751308116600 Content-Type: text/plain; charset="utf-8" The last use of this interface was removed in 603bc048a27f ("hw/arm: Remove pxa2xx_pic"). As the comment in gicv3 stated, keeping pointer references to cpregs has SMP issues, so avoid future temptation by removing the interface. Reviewed-by: Manos Pitsidianakis Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpregs.h | 32 ++++++++------------------------ hw/intc/arm_gicv3_cpuif.c | 10 +--------- target/arm/helper.c | 29 +++++++++++------------------ 3 files changed, 20 insertions(+), 51 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 3344a02bd3..b610716c24 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -906,11 +906,7 @@ struct ARMCPRegInfo { */ uint32_t nv2_redirect_offset; =20 - /* - * The opaque pointer passed to define_arm_cp_regs_with_opaque() when - * this register was defined: can be used to hand data through to the - * register read/write functions, since they are passed the ARMCPRegIn= fo*. - */ + /* This is used only by VHE. */ void *opaque; /* * Value of this register, if it is ARM_CP_CONST. Otherwise, if @@ -1004,27 +1000,15 @@ struct ARMCPRegInfo { #define CPREG_FIELD64(env, ri) \ (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) =20 -void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, const ARMCPRegInfo *re= g, - void *opaque); +void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs); +void define_arm_cp_regs_len(ARMCPU *cpu, const ARMCPRegInfo *regs, size_t = len); =20 -static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *= regs) -{ - define_one_arm_cp_reg_with_opaque(cpu, regs, NULL); -} - -void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *r= egs, - void *opaque, size_t len); - -#define define_arm_cp_regs_with_opaque(CPU, REGS, OPAQUE) \ - do { \ - QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) =3D=3D 0); = \ - define_arm_cp_regs_with_opaque_len(CPU, REGS, OPAQUE, \ - ARRAY_SIZE(REGS)); \ +#define define_arm_cp_regs(CPU, REGS) \ + do { \ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) =3D=3D 0); \ + define_arm_cp_regs_len(CPU, REGS, ARRAY_SIZE(REGS)); \ } while (0) =20 -#define define_arm_cp_regs(CPU, REGS) \ - define_arm_cp_regs_with_opaque(CPU, REGS, NULL) - const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encode= d_cp); =20 /* @@ -1143,7 +1127,7 @@ static inline bool arm_cpreg_traps_in_nv(const ARMCPR= egInfo *ri) * means that the right set of registers is exactly those where * the opc1 field is 4 or 5. (You can see this also in the assert * we do that the opc1 field and the permissions mask line up in - * define_one_arm_cp_reg_with_opaque().) + * define_one_arm_cp_reg().) * Checking the opc1 field is easier for us and avoids the problem * that we do not consistently use the right architectural names * for all sysregs, since we treat the name field as largely for debug. diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 4b4cf09157..72e91f971a 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -3037,15 +3037,7 @@ void gicv3_init_cpuif(GICv3State *s) * cpu->gic_pribits */ =20 - /* Note that we can't just use the GICv3CPUState as an opaque poin= ter - * in define_arm_cp_regs_with_opaque(), because when we're called = back - * it might be with code translated by CPU 0 but run by CPU 1, in - * which case we'd get the wrong value. - * So instead we define the regs with no ri->opaque info, and - * get back to the GICv3CPUState from the CPUARMState. - * - * These CP regs callbacks can be called from either TCG or HVF co= de. - */ + /* These CP regs callbacks can be called from either TCG or HVF. */ define_arm_cp_regs(cpu, gicv3_cpuif_reginfo); =20 /* diff --git a/target/arm/helper.c b/target/arm/helper.c index 4ba76c80b1..5bc8fb23cc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7410,12 +7410,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) } =20 /* - * Private utility function for define_one_arm_cp_reg_with_opaque(): + * Private utility function for define_one_arm_cp_reg(): * add a single reginfo struct to the hash table. */ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, - void *opaque, CPState state, - CPSecureState secstate, + CPState state, CPSecureState secstate, int crm, int opc1, int opc2, const char *name) { @@ -7503,9 +7502,6 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, r2->opc2 =3D opc2; r2->state =3D state; r2->secure =3D secstate; - if (opaque) { - r2->opaque =3D opaque; - } =20 if (make_const) { /* This should not have been a very special register to begin. */ @@ -7610,8 +7606,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, } =20 =20 -void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, - const ARMCPRegInfo *r, void *opaque) +void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r) { /* * Define implementations of coprocessor registers. @@ -7770,7 +7765,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, if (nxs_ri.fgt) { nxs_ri.fgt |=3D R_FGT_NXS_MASK; } - add_cpreg_to_hashtable(cpu, &nxs_ri, opaque, state, + add_cpreg_to_hashtable(cpu, &nxs_ri, state, ARM_CP_SECSTATE_NS, crm, opc1, opc2, name); } @@ -7784,17 +7779,17 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, switch (r->secure) { case ARM_CP_SECSTATE_S: case ARM_CP_SECSTATE_NS: - add_cpreg_to_hashtable(cpu, r, opaque, state, + add_cpreg_to_hashtable(cpu, r, state, r->secure, crm, opc1, o= pc2, r->name); break; case ARM_CP_SECSTATE_BOTH: name =3D g_strdup_printf("%s_S", r->name); - add_cpreg_to_hashtable(cpu, r, opaque, state, + add_cpreg_to_hashtable(cpu, r, state, ARM_CP_SECSTATE_S, crm, opc1, opc2, name); g_free(name); - add_cpreg_to_hashtable(cpu, r, opaque, state, + add_cpreg_to_hashtable(cpu, r, state, ARM_CP_SECSTATE_NS, crm, opc1, opc2, r->nam= e); break; @@ -7806,7 +7801,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, * AArch64 registers get mapped to non-secure inst= ance * of AArch32 */ - add_cpreg_to_hashtable(cpu, r, opaque, state, + add_cpreg_to_hashtable(cpu, r, state, ARM_CP_SECSTATE_NS, crm, opc1, opc2, r->name); } @@ -7817,12 +7812,10 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, } =20 /* Define a whole list of registers */ -void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *r= egs, - void *opaque, size_t len) +void define_arm_cp_regs_len(ARMCPU *cpu, const ARMCPRegInfo *regs, size_t = len) { - size_t i; - for (i =3D 0; i < len; ++i) { - define_one_arm_cp_reg_with_opaque(cpu, regs + i, opaque); + for (size_t i =3D 0; i < len; ++i) { + define_one_arm_cp_reg(cpu, regs + i); } } =20 --=20 2.43.0