From nobody Sun Sep 28 16:37:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758032960; cv=none; d=zohomail.com; s=zohoarc; b=STZx3/KE4/OBO6PNikIbPfYdL3nEZzVEvD/VP4vAgjvwTutZ7YVhp2hILxf0ZM73IvlKYmZEagWD+NYs+lcLVoSnVEp3HRmdnge7OVF5VyAAM//DZrhyDahj3LX0A1v4lJrg+CJxSngkKYdv/zyDWXPx5GHlQsqvzbWSwpoUqOQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758032960; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Ggwb1PQpRrrkLOGCaS9ng6BrXdIGDe+gz4mi5GKaHg4=; b=Zgt0sW/wVjbDDNRro55exjX2gIvHOPpZ/DaAx0glr1jpnDs8VpzWaCbdTMDNhbsHmgUa2w0HRdKN9v9AL4GksY/gUCMt/9iIIEpzhVSO48s4/UrAzGN2Q+IwrW30gYfvAFdAo6fe5NXnf5I9BBGaetxlseIo1DLIjCd7UvZw5BM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175803296031752.67464738088404; Tue, 16 Sep 2025 07:29:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uyWaZ-0005wS-FZ; Tue, 16 Sep 2025 10:23:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uyWa0-0005i6-6W for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:22:48 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uyWZu-0008HP-Dq for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:22:45 -0400 Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-25669596921so57024535ad.1 for ; Tue, 16 Sep 2025 07:22:41 -0700 (PDT) Received: from stoup.. ([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2651d2df15esm73459905ad.45.2025.09.16.07.22.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 07:22:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758032560; x=1758637360; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ggwb1PQpRrrkLOGCaS9ng6BrXdIGDe+gz4mi5GKaHg4=; b=Qz5dtjqmycIzu1IkGeg7iLsNqD+MbZgs9cK5MzNp/+YbxQmXDwWC75vyfBcOHLa0Rj iLphL0UqWMzbfm3o9XKFAFB90u7D3jm9IC2I+jpmGhZA1OLGZtC81aSdJh8rxBgqwBnY 8VvtuMOVhqnmZmM+6ig8Ljx8j0bYFzuQ08XN8YujTBmY3qkG3CLmLnOYeBqoZ77rriBZ L41DLHIb7Y9hmvXkiz+E+qdq2Dzq116Nv7qqF9v/0ilESyXbvkZOCR63ffEmNn+rJQ0J uQ0Wgv44hAOhkKlK120bH1Q+ZEF2n9QmfBcQU7ATYjED8kPsx1El644SRjwzYeFK2nOm 2K7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758032560; x=1758637360; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ggwb1PQpRrrkLOGCaS9ng6BrXdIGDe+gz4mi5GKaHg4=; b=AdREueHiqbYH0e3k+9XYkV9Avnabaqid1ZOSfAXcQ9rL2rL4NOBF3PWT0op+pscttx 1a06Ij51GjrusKAXPlQz8/PJwVkVFwPzQLzvw7Snny9EqHauVqmDHkavK8BNLlitB7O2 aNDgfP4ivGy1wKFXO3JxbdYCLkpA8jq3qXqCJrPiA2boiB7mIjqoteMIrj+UoofKz6EK E+WaW+J80NJ57HB8vlFHaB3oZ7hbODoYMoumz/PDy4Ks2mgwrDs+Lb2BU3741E7vjuM2 E1cJBmkH0DgQKXVW8BUDhfg3lvp3i6n8KAD8Q3N41W2J11KFEDGyYOqoWvFSPoB8XZeR /HEA== X-Gm-Message-State: AOJu0Yya4BHxX76++w0oCogCzgJTZO0RlPtDG0pRxeVvNWygu2tViXts NHGOmYXK3f5CBNlIWjLm3TjQLuUF/E81sCf9jRUHJp/L9UPM38IC0M9ci9sPqNqYORgmFWyqhY8 KmWEv X-Gm-Gg: ASbGncttZ3fMQq9dVcKYy0NK32IxdXgaJ6BDQPr2pa1RLBdC7BOJzCtT8ezjeFzEJEd kX20Ja+IRwo+VItnhMBEwlFG+sz7/oJMbQDncLxXoTTqRlqnzrkC9WM/wYiaoseHK1eGeVFS1RN y80Di58767yHdWv7lKThMtjdJizAM43xjhnvnvYwt+jevrK3AG5+CTaFXlQdaKL7vd/g7/Ca1Bj Qjj+o+hhEgsO9VZ6dI5cA0QS/OPPisIVrlLuxqa4P3RaS82NZ2+AAFl4syVFx8KjTJwwpjae4af Q23FRXbFCW1jNVaskXA9UHkNlg3KiOItr00D11HWJhXE2qpopczQ/stGjATzeOtGrpe3+RLXS7i Nf1Xic80dQx1wftDPoVgPYC0PDr29 X-Google-Smtp-Source: AGHT+IE3CN+8SXPUqhiTrptq+LUoQb03jckSSvZOGZe49jHkgbp5Mfw/0e7ESoBQA2ho9ljZ3tPuCg== X-Received: by 2002:a17:903:37c4:b0:248:811e:f86c with SMTP id d9443c01a7336-25d26663209mr182399855ad.34.1758032560232; Tue, 16 Sep 2025 07:22:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v2 01/36] target/arm: Introduce KVMID_AA64_SYS_REG64 Date: Tue, 16 Sep 2025 07:22:02 -0700 Message-ID: <20250916142238.664316-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916142238.664316-1-richard.henderson@linaro.org> References: <20250916142238.664316-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758032962032116600 Content-Type: text/plain; charset="utf-8" Allow us to create kvm ids directly, rather than going through ENCODE_AA64_CP_REG + cpreg_to_kvm_id. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/kvm-consts.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h index c44d23dbe7..fdb305eea1 100644 --- a/target/arm/kvm-consts.h +++ b/target/arm/kvm-consts.h @@ -180,4 +180,15 @@ MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP2_SHIFT, KVM_REG_= ARM64_SYSREG_OP2_SHIFT); =20 #undef MISMATCH_CHECK =20 +#define KVMID_AA64_SYS_REG_(op0, op1, crn, crm, op2) \ + (CP_REG_AA64_MASK | CP_REG_ARM64_SYSREG | \ + ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ + ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ + ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ + ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ + ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) + +#define KVMID_AA64_SYS_REG64(op0, op1, crn, crm, op2) \ + (KVMID_AA64_SYS_REG_(op0, op1, crn, crm, op2) | CP_REG_SIZE_U64) + #endif --=20 2.43.0 From nobody Sun Sep 28 16:37:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758033133; cv=none; d=zohomail.com; s=zohoarc; b=UbrA/awb5KwrtCZhK2mVPYIgQIdGUxwxbO5rSS7XRx/MJnWGexGluI7Hxgx4+DUvad4He9kCW/gymQiEqkBSIS7oCiE/QsJuUP5tfh/mq2SvHWuO79grbJweeZBHVGWcH42x+vKEtornG/3gUXti0jM0VGRUbxK2xMqf/oywnkk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758033133; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=+3xm1kMJVy9epiTvDaZGGXppX5/JPVL6xwbTCzPX0xU=; b=UuaY9kz5pb16XzwvNYV4pzcMhOJk66N6i0pP58sRx2uW5oq7++YmRUboIS06jPskHspcJ05z3c0Dy0c6SHLq0qjvPyaMaZ71dWmuyAIibnOez6lViiLY5vVlNX12pKmkedAnV0RBaH5+dhPbAGlVaIQhuVrEHo5/293TR6SMuUQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758033133955430.5282722978926; Tue, 16 Sep 2025 07:32:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uyWaW-0005tV-FX; Tue, 16 Sep 2025 10:23:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uyWa0-0005i7-6B for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:22:48 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uyWZu-0008HY-TR for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:22:45 -0400 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-2445826fd9dso65598555ad.3 for ; Tue, 16 Sep 2025 07:22:42 -0700 (PDT) Received: from stoup.. ([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2651d2df15esm73459905ad.45.2025.09.16.07.22.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 07:22:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758032561; x=1758637361; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+3xm1kMJVy9epiTvDaZGGXppX5/JPVL6xwbTCzPX0xU=; b=y3QarTMOHAL0Kk3Zr/nlcd3dYEIeFwTh37+pA7FHXdodzWf//kDKeJnKvQ74697JXx sHNdAzDKIT4m/xRDGCatPRzrcnGEmkd83QSWfPWcBpwLmZ5xlNVzXxQPMiZbDD/1CjSy kSH5l11sakNmqM7cKWb4TXujsMTqOyelRx336kpXZtlTGk0/9tVrsE9KAh8emE6GxiBo kwYeJ3I8QM+SqHJ84j8wPBuf+SeZ2wlkF6J3LppwveidYoKLqcK6A2D6NzetRXJNEAXH aSvOLa9nbuhqzfqZBTqPRDPCnHucCNEpv7aiF166fMFBujW8A0rhFsy4smI998BrFz2e +FOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758032561; x=1758637361; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+3xm1kMJVy9epiTvDaZGGXppX5/JPVL6xwbTCzPX0xU=; b=WjEoYua50931+TPA1LeFB9fr/+ijAhJOLgTKI9VpB/f6kZlC41KXP+4jceZE5mwrGv uqjVj8E9zjnu5/39w73283QT8nVzV6XNYuvAvKqbNyEiXD4Wlj47yhETR5XacjiC6A5M Sr6SVDdbr1vvHeRoMUGku+BpnryhkGX4VmbtDx+GIRNmu+7bC5JUsgwIiRegvpFPvkGH OdtuoFF46fPwCMXNCB3NrUECPNjGjhx8il8ho9KN9mKyrhuc++TGJ7QAVUyjSgCxq6rt y6Nz3cdo4kyd2jd+A4HoVJtYGtcli4h0gkTRLUSJ7zhYJ/fxKdgxS66iC0ccUjQE0t4M 4tFw== X-Gm-Message-State: AOJu0Yx2tlXeZfFeSqUB/CVKCoN084LU2K2ng8yU6bITcGTXP/ABn3A2 FkV1oeBTT8KCO4VYCrAoYnttSlLjttYlUWr+m/uTkwDLdNDOSyaxg+StXYa6119buJ8mzHRILwK LVq6N X-Gm-Gg: ASbGncuThKnHqTXRhSisNp1DZyNAInPxfaUUG9znMSrfyzRpPkUm2XA7NgJERlNLDto 2Hl1nM1v0+YJA/6umOcBKj3+msmyuvTsueQo0T7t0DwU9IumEoIr7h+KyZr0waPql19sVonWDb6 DnBjEqWzOc3I5gNAZME9QI2q7QtR9sv10SM7cNVHT0p747aTMknVBgCIj4+GMVd/4rY/LC7L3Z3 NCh1t4qn42q6ajC5S1c93x9WJgDDehkMHwoHY1VLNyj0jPpdRLWC40+6PHNPUIFB01zyRGEsjrr T3Jp63Jh+kNnVj6diHEDgoP5jE1AIpbHCJS3ARpD7HGFavqCoep/12Pksde57uE1korBFpp3lYL HLk/99A6L/XS7QdeNPVbqT2jU95/Y X-Google-Smtp-Source: AGHT+IEKYFr5mHf6j9pPZf1kw+lkToeLk+paj3zDSHydNPbS1vfxBAr8FDnRmwXS0QuIe2iW0HXWBQ== X-Received: by 2002:a17:903:287:b0:25c:d4b6:f117 with SMTP id d9443c01a7336-25d276242femr211550615ad.35.1758032560961; Tue, 16 Sep 2025 07:22:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, Manos Pitsidianakis Subject: [PATCH v2 02/36] target/arm: Move compare_u64 to helper.c Date: Tue, 16 Sep 2025 07:22:03 -0700 Message-ID: <20250916142238.664316-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916142238.664316-1-richard.henderson@linaro.org> References: <20250916142238.664316-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758033134427116600 Content-Type: text/plain; charset="utf-8" We will use this function beyond kvm.c. Reviewed-by: Manos Pitsidianakis Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/internals.h | 3 +++ target/arm/helper.c | 11 +++++++++++ target/arm/kvm.c | 11 ----------- 3 files changed, 14 insertions(+), 11 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index f5a1e75db3..41133df778 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1999,4 +1999,7 @@ void vfp_clear_float_status_exc_flags(CPUARMState *en= v); void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask); bool arm_pan_enabled(CPUARMState *env); =20 +/* Compare uint64_t for qsort and bsearch. */ +int compare_u64(const void *a, const void *b); + #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index 19637e7301..df9e0c7bca 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -40,6 +40,17 @@ =20 static void switch_mode(CPUARMState *env, int mode); =20 +int compare_u64(const void *a, const void *b) +{ + if (*(uint64_t *)a > *(uint64_t *)b) { + return 1; + } + if (*(uint64_t *)a < *(uint64_t *)b) { + return -1; + } + return 0; +} + uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) { assert(ri->fieldoffset); diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 6672344855..9e569eff65 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -718,17 +718,6 @@ void kvm_arm_register_device(MemoryRegion *mr, uint64_= t devid, uint64_t group, memory_region_ref(kd->mr); } =20 -static int compare_u64(const void *a, const void *b) -{ - if (*(uint64_t *)a > *(uint64_t *)b) { - return 1; - } - if (*(uint64_t *)a < *(uint64_t *)b) { - return -1; - } - return 0; -} - /* * cpreg_values are sorted in ascending order by KVM register ID * (see kvm_arm_init_cpreg_list). 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([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2651d2df15esm73459905ad.45.2025.09.16.07.22.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 07:22:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758032563; x=1758637363; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7CLvOjXal/wRoc/wLSYOsvhQgX3fvH+M30NDHTCz0Cg=; b=kJEgu6l1/wDnAiy/CR/hN4bYeEh7eOmRcuafuzeRa4SU440ssf0PSJdqOL9fbAK0b1 GeAB9ES7bG2801Fkto17/xXLHuOfX+jhh+tYVWIj5Lj0Wu5HPEYle1v+qzN21qFCh9Zn Uuk3daBc+ajRNPbZSegfpEzsSwN3A8tlD4ONkXPh6j554UjyPVKYFgOs4vZk7FPiWjmG tPOp5senSOLS606cju+ASdh0GYtsUcdx+5n9dMT5PB9SBGo2mdWZGenJ4rlEoKdJbRA3 S5ta70pAHumIq26EwcmTMlh2uZvlV2Baj9WyTwTQoBvpJxWGBZmZW5pQkzZdPrzCii5d VSSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758032563; x=1758637363; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7CLvOjXal/wRoc/wLSYOsvhQgX3fvH+M30NDHTCz0Cg=; b=NcRsYTUZirhtZNIYH7PniKtUUOZA11jHD1X4i2r4n6h9c/wjBMQjH+r7x9j3vUfAP/ x3/mlgC5hc17YrW3Suvhr7kIXn4LkQYkR2hozBe7/Q3TOeWj3cdvTIWc3SaheRfeJ4SW 7Jl9cTqd5/BF+6c9t0nDep1iLVWAa5tp7hxeSSL+ix9q8VzZU5Gx/E/n8VnsuBIkvIyX 8hJk6VyfOsmVDb7BUA9vHjg9tIkur7TpDXVVWpLaNB+P8gjhrTjzAe0Oh+VlsGZ6RkWC /y3pUzgEhZNuQL/FR2neNpsq1z1/DQF/KibTAzmhHHF53TMYSCjeXGiazRK/wuWgcG45 VMlg== X-Gm-Message-State: AOJu0Yx+Sgam2q6J3vmzW4Cfpa1V8WrJRKObcHte3Qvp/j3f5sObW0sm U0HRZtmA2WziwWtdEdNn51Q75LU/rMPcNa9EF+xgfX59mfi5gpRTSnjRwwCJJE/buZgux7Ay93p FmvBn X-Gm-Gg: ASbGncsP2I1Oay0Sd9ImCijSp2RINCMLrxbuB9sN4DiLlkR3HsvwUWg7RzOiQySLdya dJjPfwnfUwqgUNehBjE77sZpXFWNyimOYfkLV4xl1X9kDHbL17mhorRxPmR9foYL9b5UdJ6zzyJ kykURM5/gmm4MDPbMCVK0CGDsEGQzqZvxDk76cx3QjMuKFGg4KQ1W7I5hBOqgqsKugOJ8ECnPQM ODl5EYLwV2xNXsSGHobmptk2XlSnUSJoyApXl044JZDszTAz/MyApQBbpwiNMx04UL+1fGcTWOF 6SZhAnkQw7H5KxUWaIdmssRwMm+T7QnFIMDSgbzBzi5XjZLcryJpfBKLFDhSkc7mBDedB5jZoq0 64JOWxuP7Q9e+LHUVAA9T4Bsfdf3V X-Google-Smtp-Source: AGHT+IEgFYRalaSvs5S3aALfeRi2yL5MiMSg+po6K/v7tJPJ0muDCVCpraHKy73OVqaPuM1ISoTwDg== X-Received: by 2002:a17:903:384b:b0:24e:95bb:88b1 with SMTP id d9443c01a7336-25d267641f0mr178771905ad.34.1758032561755; Tue, 16 Sep 2025 07:22:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, Manos Pitsidianakis Subject: [PATCH v2 03/36] target/arm/hvf: Split out sysreg.c.inc Date: Tue, 16 Sep 2025 07:22:04 -0700 Message-ID: <20250916142238.664316-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916142238.664316-1-richard.henderson@linaro.org> References: <20250916142238.664316-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758032641387116600 Content-Type: text/plain; charset="utf-8" Move the list of supported sysregs to a reuseable file. Reviewed-by: Manos Pitsidianakis Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/hvf/hvf.c | 147 ++---------------------------------- target/arm/hvf/sysreg.c.inc | 146 +++++++++++++++++++++++++++++++++++ 2 files changed, 152 insertions(+), 141 deletions(-) create mode 100644 target/arm/hvf/sysreg.c.inc diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index b77db99079..9f8e3083b4 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -403,150 +403,15 @@ struct hvf_sreg_match { uint32_t cp_idx; }; =20 +#define DEF_SYSREG(HVF_ID, crn, crm, op0, op1, op2) \ + { HVF_ID, HVF_SYSREG(crn, crm, op0, op1, op2) }, + static struct hvf_sreg_match hvf_sreg_match[] =3D { - { HV_SYS_REG_DBGBVR0_EL1, HVF_SYSREG(0, 0, 2, 0, 4) }, - { HV_SYS_REG_DBGBCR0_EL1, HVF_SYSREG(0, 0, 2, 0, 5) }, - { HV_SYS_REG_DBGWVR0_EL1, HVF_SYSREG(0, 0, 2, 0, 6) }, - { HV_SYS_REG_DBGWCR0_EL1, HVF_SYSREG(0, 0, 2, 0, 7) }, - - { HV_SYS_REG_DBGBVR1_EL1, HVF_SYSREG(0, 1, 2, 0, 4) }, - { HV_SYS_REG_DBGBCR1_EL1, HVF_SYSREG(0, 1, 2, 0, 5) }, - { HV_SYS_REG_DBGWVR1_EL1, HVF_SYSREG(0, 1, 2, 0, 6) }, - { HV_SYS_REG_DBGWCR1_EL1, HVF_SYSREG(0, 1, 2, 0, 7) }, - - { HV_SYS_REG_DBGBVR2_EL1, HVF_SYSREG(0, 2, 2, 0, 4) }, - { HV_SYS_REG_DBGBCR2_EL1, HVF_SYSREG(0, 2, 2, 0, 5) }, - { HV_SYS_REG_DBGWVR2_EL1, HVF_SYSREG(0, 2, 2, 0, 6) }, - { HV_SYS_REG_DBGWCR2_EL1, HVF_SYSREG(0, 2, 2, 0, 7) }, - - { HV_SYS_REG_DBGBVR3_EL1, HVF_SYSREG(0, 3, 2, 0, 4) }, - { HV_SYS_REG_DBGBCR3_EL1, HVF_SYSREG(0, 3, 2, 0, 5) }, - { HV_SYS_REG_DBGWVR3_EL1, HVF_SYSREG(0, 3, 2, 0, 6) }, - { HV_SYS_REG_DBGWCR3_EL1, HVF_SYSREG(0, 3, 2, 0, 7) }, - - { HV_SYS_REG_DBGBVR4_EL1, HVF_SYSREG(0, 4, 2, 0, 4) }, - { HV_SYS_REG_DBGBCR4_EL1, HVF_SYSREG(0, 4, 2, 0, 5) }, - { HV_SYS_REG_DBGWVR4_EL1, HVF_SYSREG(0, 4, 2, 0, 6) }, - { HV_SYS_REG_DBGWCR4_EL1, HVF_SYSREG(0, 4, 2, 0, 7) }, - - { HV_SYS_REG_DBGBVR5_EL1, HVF_SYSREG(0, 5, 2, 0, 4) }, - { HV_SYS_REG_DBGBCR5_EL1, HVF_SYSREG(0, 5, 2, 0, 5) }, - { HV_SYS_REG_DBGWVR5_EL1, HVF_SYSREG(0, 5, 2, 0, 6) }, - { HV_SYS_REG_DBGWCR5_EL1, HVF_SYSREG(0, 5, 2, 0, 7) }, - - { HV_SYS_REG_DBGBVR6_EL1, HVF_SYSREG(0, 6, 2, 0, 4) }, - { HV_SYS_REG_DBGBCR6_EL1, HVF_SYSREG(0, 6, 2, 0, 5) }, - { HV_SYS_REG_DBGWVR6_EL1, HVF_SYSREG(0, 6, 2, 0, 6) }, - { HV_SYS_REG_DBGWCR6_EL1, HVF_SYSREG(0, 6, 2, 0, 7) }, - - { HV_SYS_REG_DBGBVR7_EL1, HVF_SYSREG(0, 7, 2, 0, 4) }, - { HV_SYS_REG_DBGBCR7_EL1, HVF_SYSREG(0, 7, 2, 0, 5) }, - { HV_SYS_REG_DBGWVR7_EL1, HVF_SYSREG(0, 7, 2, 0, 6) }, - { HV_SYS_REG_DBGWCR7_EL1, HVF_SYSREG(0, 7, 2, 0, 7) }, - - { HV_SYS_REG_DBGBVR8_EL1, HVF_SYSREG(0, 8, 2, 0, 4) }, - { HV_SYS_REG_DBGBCR8_EL1, HVF_SYSREG(0, 8, 2, 0, 5) }, - { HV_SYS_REG_DBGWVR8_EL1, HVF_SYSREG(0, 8, 2, 0, 6) }, - { HV_SYS_REG_DBGWCR8_EL1, HVF_SYSREG(0, 8, 2, 0, 7) }, - - { HV_SYS_REG_DBGBVR9_EL1, HVF_SYSREG(0, 9, 2, 0, 4) }, - { HV_SYS_REG_DBGBCR9_EL1, HVF_SYSREG(0, 9, 2, 0, 5) }, - { HV_SYS_REG_DBGWVR9_EL1, HVF_SYSREG(0, 9, 2, 0, 6) }, - { HV_SYS_REG_DBGWCR9_EL1, HVF_SYSREG(0, 9, 2, 0, 7) }, - - { HV_SYS_REG_DBGBVR10_EL1, HVF_SYSREG(0, 10, 2, 0, 4) }, - { HV_SYS_REG_DBGBCR10_EL1, HVF_SYSREG(0, 10, 2, 0, 5) }, - { HV_SYS_REG_DBGWVR10_EL1, HVF_SYSREG(0, 10, 2, 0, 6) }, - { HV_SYS_REG_DBGWCR10_EL1, HVF_SYSREG(0, 10, 2, 0, 7) }, - - { HV_SYS_REG_DBGBVR11_EL1, HVF_SYSREG(0, 11, 2, 0, 4) }, - { HV_SYS_REG_DBGBCR11_EL1, HVF_SYSREG(0, 11, 2, 0, 5) }, - { HV_SYS_REG_DBGWVR11_EL1, HVF_SYSREG(0, 11, 2, 0, 6) }, - { HV_SYS_REG_DBGWCR11_EL1, HVF_SYSREG(0, 11, 2, 0, 7) }, - - { HV_SYS_REG_DBGBVR12_EL1, HVF_SYSREG(0, 12, 2, 0, 4) }, - { HV_SYS_REG_DBGBCR12_EL1, HVF_SYSREG(0, 12, 2, 0, 5) }, - { HV_SYS_REG_DBGWVR12_EL1, HVF_SYSREG(0, 12, 2, 0, 6) }, - { HV_SYS_REG_DBGWCR12_EL1, HVF_SYSREG(0, 12, 2, 0, 7) }, - - { HV_SYS_REG_DBGBVR13_EL1, HVF_SYSREG(0, 13, 2, 0, 4) }, - { HV_SYS_REG_DBGBCR13_EL1, HVF_SYSREG(0, 13, 2, 0, 5) }, - { HV_SYS_REG_DBGWVR13_EL1, HVF_SYSREG(0, 13, 2, 0, 6) }, - { HV_SYS_REG_DBGWCR13_EL1, HVF_SYSREG(0, 13, 2, 0, 7) }, - - { HV_SYS_REG_DBGBVR14_EL1, HVF_SYSREG(0, 14, 2, 0, 4) }, - { HV_SYS_REG_DBGBCR14_EL1, HVF_SYSREG(0, 14, 2, 0, 5) }, - { HV_SYS_REG_DBGWVR14_EL1, HVF_SYSREG(0, 14, 2, 0, 6) }, - { HV_SYS_REG_DBGWCR14_EL1, HVF_SYSREG(0, 14, 2, 0, 7) }, - - { HV_SYS_REG_DBGBVR15_EL1, HVF_SYSREG(0, 15, 2, 0, 4) }, - { HV_SYS_REG_DBGBCR15_EL1, HVF_SYSREG(0, 15, 2, 0, 5) }, - { HV_SYS_REG_DBGWVR15_EL1, HVF_SYSREG(0, 15, 2, 0, 6) }, - { HV_SYS_REG_DBGWCR15_EL1, HVF_SYSREG(0, 15, 2, 0, 7) }, - -#ifdef SYNC_NO_RAW_REGS - /* - * The registers below are manually synced on init because they are - * marked as NO_RAW. We still list them to make number space sync easi= er. - */ - { HV_SYS_REG_MDCCINT_EL1, HVF_SYSREG(0, 2, 2, 0, 0) }, - { HV_SYS_REG_MIDR_EL1, HVF_SYSREG(0, 0, 3, 0, 0) }, - { HV_SYS_REG_MPIDR_EL1, HVF_SYSREG(0, 0, 3, 0, 5) }, - { HV_SYS_REG_ID_AA64PFR0_EL1, HVF_SYSREG(0, 4, 3, 0, 0) }, -#endif - { HV_SYS_REG_ID_AA64PFR1_EL1, HVF_SYSREG(0, 4, 3, 0, 1) }, - { HV_SYS_REG_ID_AA64DFR0_EL1, HVF_SYSREG(0, 5, 3, 0, 0) }, - { HV_SYS_REG_ID_AA64DFR1_EL1, HVF_SYSREG(0, 5, 3, 0, 1) }, - { HV_SYS_REG_ID_AA64ISAR0_EL1, HVF_SYSREG(0, 6, 3, 0, 0) }, - { HV_SYS_REG_ID_AA64ISAR1_EL1, HVF_SYSREG(0, 6, 3, 0, 1) }, -#ifdef SYNC_NO_MMFR0 - /* We keep the hardware MMFR0 around. HW limits are there anyway */ - { HV_SYS_REG_ID_AA64MMFR0_EL1, HVF_SYSREG(0, 7, 3, 0, 0) }, -#endif - { HV_SYS_REG_ID_AA64MMFR1_EL1, HVF_SYSREG(0, 7, 3, 0, 1) }, - { HV_SYS_REG_ID_AA64MMFR2_EL1, HVF_SYSREG(0, 7, 3, 0, 2) }, - /* Add ID_AA64MMFR3_EL1 here when HVF supports it */ - - { HV_SYS_REG_MDSCR_EL1, HVF_SYSREG(0, 2, 2, 0, 2) }, - { HV_SYS_REG_SCTLR_EL1, HVF_SYSREG(1, 0, 3, 0, 0) }, - { HV_SYS_REG_CPACR_EL1, HVF_SYSREG(1, 0, 3, 0, 2) }, - { HV_SYS_REG_TTBR0_EL1, HVF_SYSREG(2, 0, 3, 0, 0) }, - { HV_SYS_REG_TTBR1_EL1, HVF_SYSREG(2, 0, 3, 0, 1) }, - { HV_SYS_REG_TCR_EL1, HVF_SYSREG(2, 0, 3, 0, 2) }, - - { HV_SYS_REG_APIAKEYLO_EL1, HVF_SYSREG(2, 1, 3, 0, 0) }, - { HV_SYS_REG_APIAKEYHI_EL1, HVF_SYSREG(2, 1, 3, 0, 1) }, - { HV_SYS_REG_APIBKEYLO_EL1, HVF_SYSREG(2, 1, 3, 0, 2) }, - { HV_SYS_REG_APIBKEYHI_EL1, HVF_SYSREG(2, 1, 3, 0, 3) }, - { HV_SYS_REG_APDAKEYLO_EL1, HVF_SYSREG(2, 2, 3, 0, 0) }, - { HV_SYS_REG_APDAKEYHI_EL1, HVF_SYSREG(2, 2, 3, 0, 1) }, - { HV_SYS_REG_APDBKEYLO_EL1, HVF_SYSREG(2, 2, 3, 0, 2) }, - { HV_SYS_REG_APDBKEYHI_EL1, HVF_SYSREG(2, 2, 3, 0, 3) }, - { HV_SYS_REG_APGAKEYLO_EL1, HVF_SYSREG(2, 3, 3, 0, 0) }, - { HV_SYS_REG_APGAKEYHI_EL1, HVF_SYSREG(2, 3, 3, 0, 1) }, - - { HV_SYS_REG_SPSR_EL1, HVF_SYSREG(4, 0, 3, 0, 0) }, - { HV_SYS_REG_ELR_EL1, HVF_SYSREG(4, 0, 3, 0, 1) }, - { HV_SYS_REG_SP_EL0, HVF_SYSREG(4, 1, 3, 0, 0) }, - { HV_SYS_REG_AFSR0_EL1, HVF_SYSREG(5, 1, 3, 0, 0) }, - { HV_SYS_REG_AFSR1_EL1, HVF_SYSREG(5, 1, 3, 0, 1) }, - { HV_SYS_REG_ESR_EL1, HVF_SYSREG(5, 2, 3, 0, 0) }, - { HV_SYS_REG_FAR_EL1, HVF_SYSREG(6, 0, 3, 0, 0) }, - { HV_SYS_REG_PAR_EL1, HVF_SYSREG(7, 4, 3, 0, 0) }, - { HV_SYS_REG_MAIR_EL1, HVF_SYSREG(10, 2, 3, 0, 0) }, - { HV_SYS_REG_AMAIR_EL1, HVF_SYSREG(10, 3, 3, 0, 0) }, - { HV_SYS_REG_VBAR_EL1, HVF_SYSREG(12, 0, 3, 0, 0) }, - { HV_SYS_REG_CONTEXTIDR_EL1, HVF_SYSREG(13, 0, 3, 0, 1) }, - { HV_SYS_REG_TPIDR_EL1, HVF_SYSREG(13, 0, 3, 0, 4) }, - { HV_SYS_REG_CNTKCTL_EL1, HVF_SYSREG(14, 1, 3, 0, 0) }, - { HV_SYS_REG_CSSELR_EL1, HVF_SYSREG(0, 0, 3, 2, 0) }, - { HV_SYS_REG_TPIDR_EL0, HVF_SYSREG(13, 0, 3, 3, 2) }, - { HV_SYS_REG_TPIDRRO_EL0, HVF_SYSREG(13, 0, 3, 3, 3) }, - { HV_SYS_REG_CNTV_CTL_EL0, HVF_SYSREG(14, 3, 3, 3, 1) }, - { HV_SYS_REG_CNTV_CVAL_EL0, HVF_SYSREG(14, 3, 3, 3, 2) }, - { HV_SYS_REG_SP_EL1, HVF_SYSREG(4, 1, 3, 4, 0) }, +#include "sysreg.c.inc" }; =20 +#undef DEF_SYSREG + int hvf_get_registers(CPUState *cpu) { ARMCPU *arm_cpu =3D ARM_CPU(cpu); diff --git a/target/arm/hvf/sysreg.c.inc b/target/arm/hvf/sysreg.c.inc new file mode 100644 index 0000000000..222698f1d1 --- /dev/null +++ b/target/arm/hvf/sysreg.c.inc @@ -0,0 +1,146 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +DEF_SYSREG(HV_SYS_REG_DBGBVR0_EL1, 0, 0, 2, 0, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR0_EL1, 0, 0, 2, 0, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR0_EL1, 0, 0, 2, 0, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR0_EL1, 0, 0, 2, 0, 7) + +DEF_SYSREG(HV_SYS_REG_DBGBVR1_EL1, 0, 1, 2, 0, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR1_EL1, 0, 1, 2, 0, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR1_EL1, 0, 1, 2, 0, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR1_EL1, 0, 1, 2, 0, 7) + +DEF_SYSREG(HV_SYS_REG_DBGBVR2_EL1, 0, 2, 2, 0, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR2_EL1, 0, 2, 2, 0, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR2_EL1, 0, 2, 2, 0, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR2_EL1, 0, 2, 2, 0, 7) + +DEF_SYSREG(HV_SYS_REG_DBGBVR3_EL1, 0, 3, 2, 0, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR3_EL1, 0, 3, 2, 0, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR3_EL1, 0, 3, 2, 0, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR3_EL1, 0, 3, 2, 0, 7) + +DEF_SYSREG(HV_SYS_REG_DBGBVR4_EL1, 0, 4, 2, 0, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR4_EL1, 0, 4, 2, 0, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR4_EL1, 0, 4, 2, 0, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR4_EL1, 0, 4, 2, 0, 7) + +DEF_SYSREG(HV_SYS_REG_DBGBVR5_EL1, 0, 5, 2, 0, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR5_EL1, 0, 5, 2, 0, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR5_EL1, 0, 5, 2, 0, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR5_EL1, 0, 5, 2, 0, 7) + +DEF_SYSREG(HV_SYS_REG_DBGBVR6_EL1, 0, 6, 2, 0, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR6_EL1, 0, 6, 2, 0, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR6_EL1, 0, 6, 2, 0, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR6_EL1, 0, 6, 2, 0, 7) + +DEF_SYSREG(HV_SYS_REG_DBGBVR7_EL1, 0, 7, 2, 0, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR7_EL1, 0, 7, 2, 0, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR7_EL1, 0, 7, 2, 0, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR7_EL1, 0, 7, 2, 0, 7) + +DEF_SYSREG(HV_SYS_REG_DBGBVR8_EL1, 0, 8, 2, 0, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR8_EL1, 0, 8, 2, 0, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR8_EL1, 0, 8, 2, 0, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR8_EL1, 0, 8, 2, 0, 7) + +DEF_SYSREG(HV_SYS_REG_DBGBVR9_EL1, 0, 9, 2, 0, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR9_EL1, 0, 9, 2, 0, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR9_EL1, 0, 9, 2, 0, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR9_EL1, 0, 9, 2, 0, 7) + +DEF_SYSREG(HV_SYS_REG_DBGBVR10_EL1, 0, 10, 2, 0, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR10_EL1, 0, 10, 2, 0, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR10_EL1, 0, 10, 2, 0, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR10_EL1, 0, 10, 2, 0, 7) + +DEF_SYSREG(HV_SYS_REG_DBGBVR11_EL1, 0, 11, 2, 0, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR11_EL1, 0, 11, 2, 0, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR11_EL1, 0, 11, 2, 0, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR11_EL1, 0, 11, 2, 0, 7) + +DEF_SYSREG(HV_SYS_REG_DBGBVR12_EL1, 0, 12, 2, 0, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR12_EL1, 0, 12, 2, 0, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR12_EL1, 0, 12, 2, 0, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR12_EL1, 0, 12, 2, 0, 7) + +DEF_SYSREG(HV_SYS_REG_DBGBVR13_EL1, 0, 13, 2, 0, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR13_EL1, 0, 13, 2, 0, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR13_EL1, 0, 13, 2, 0, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR13_EL1, 0, 13, 2, 0, 7) + +DEF_SYSREG(HV_SYS_REG_DBGBVR14_EL1, 0, 14, 2, 0, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR14_EL1, 0, 14, 2, 0, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR14_EL1, 0, 14, 2, 0, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR14_EL1, 0, 14, 2, 0, 7) + +DEF_SYSREG(HV_SYS_REG_DBGBVR15_EL1, 0, 15, 2, 0, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR15_EL1, 0, 15, 2, 0, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR15_EL1, 0, 15, 2, 0, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR15_EL1, 0, 15, 2, 0, 7) + +#ifdef SYNC_NO_RAW_REGS +/* + * The registers below are manually synced on init because they are + * marked as NO_RAW. We still list them to make number space sync easier. + */ +DEF_SYSREG(HV_SYS_REG_MDCCINT_EL1, 0, 2, 2, 0, 0) +DEF_SYSREG(HV_SYS_REG_MIDR_EL1, 0, 0, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_MPIDR_EL1, 0, 0, 3, 0, 5) +DEF_SYSREG(HV_SYS_REG_ID_AA64PFR0_EL1, 0, 4, 3, 0, 0) +#endif + +DEF_SYSREG(HV_SYS_REG_ID_AA64PFR1_EL1, 0, 4, 3, 0, 1) +DEF_SYSREG(HV_SYS_REG_ID_AA64DFR0_EL1, 0, 5, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_ID_AA64DFR1_EL1, 0, 5, 3, 0, 1) +DEF_SYSREG(HV_SYS_REG_ID_AA64ISAR0_EL1, 0, 6, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_ID_AA64ISAR1_EL1, 0, 6, 3, 0, 1) + +#ifdef SYNC_NO_MMFR0 +/* We keep the hardware MMFR0 around. HW limits are there anyway */ +DEF_SYSREG(HV_SYS_REG_ID_AA64MMFR0_EL1, 0, 7, 3, 0, 0) +#endif + +DEF_SYSREG(HV_SYS_REG_ID_AA64MMFR1_EL1, 0, 7, 3, 0, 1) +DEF_SYSREG(HV_SYS_REG_ID_AA64MMFR2_EL1, 0, 7, 3, 0, 2) +/* Add ID_AA64MMFR3_EL1 here when HVF supports it */ + +DEF_SYSREG(HV_SYS_REG_MDSCR_EL1, 0, 2, 2, 0, 2) +DEF_SYSREG(HV_SYS_REG_SCTLR_EL1, 1, 0, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_CPACR_EL1, 1, 0, 3, 0, 2) +DEF_SYSREG(HV_SYS_REG_TTBR0_EL1, 2, 0, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_TTBR1_EL1, 2, 0, 3, 0, 1) +DEF_SYSREG(HV_SYS_REG_TCR_EL1, 2, 0, 3, 0, 2) + +DEF_SYSREG(HV_SYS_REG_APIAKEYLO_EL1, 2, 1, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_APIAKEYHI_EL1, 2, 1, 3, 0, 1) +DEF_SYSREG(HV_SYS_REG_APIBKEYLO_EL1, 2, 1, 3, 0, 2) +DEF_SYSREG(HV_SYS_REG_APIBKEYHI_EL1, 2, 1, 3, 0, 3) +DEF_SYSREG(HV_SYS_REG_APDAKEYLO_EL1, 2, 2, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_APDAKEYHI_EL1, 2, 2, 3, 0, 1) +DEF_SYSREG(HV_SYS_REG_APDBKEYLO_EL1, 2, 2, 3, 0, 2) +DEF_SYSREG(HV_SYS_REG_APDBKEYHI_EL1, 2, 2, 3, 0, 3) +DEF_SYSREG(HV_SYS_REG_APGAKEYLO_EL1, 2, 3, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_APGAKEYHI_EL1, 2, 3, 3, 0, 1) + +DEF_SYSREG(HV_SYS_REG_SPSR_EL1, 4, 0, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_ELR_EL1, 4, 0, 3, 0, 1) +DEF_SYSREG(HV_SYS_REG_SP_EL0, 4, 1, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_AFSR0_EL1, 5, 1, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_AFSR1_EL1, 5, 1, 3, 0, 1) +DEF_SYSREG(HV_SYS_REG_ESR_EL1, 5, 2, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_FAR_EL1, 6, 0, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_PAR_EL1, 7, 4, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_MAIR_EL1, 10, 2, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_AMAIR_EL1, 10, 3, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_VBAR_EL1, 12, 0, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_CONTEXTIDR_EL1, 13, 0, 3, 0, 1) +DEF_SYSREG(HV_SYS_REG_TPIDR_EL1, 13, 0, 3, 0, 4) +DEF_SYSREG(HV_SYS_REG_CNTKCTL_EL1, 14, 1, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_CSSELR_EL1, 0, 0, 3, 2, 0) +DEF_SYSREG(HV_SYS_REG_TPIDR_EL0, 13, 0, 3, 3, 2) +DEF_SYSREG(HV_SYS_REG_TPIDRRO_EL0, 13, 0, 3, 3, 3) +DEF_SYSREG(HV_SYS_REG_CNTV_CTL_EL0, 14, 3, 3, 3, 1) +DEF_SYSREG(HV_SYS_REG_CNTV_CVAL_EL0, 14, 3, 3, 3, 2) +DEF_SYSREG(HV_SYS_REG_SP_EL1, 4, 1, 3, 4, 0) --=20 2.43.0 From nobody Sun Sep 28 16:37:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758032726; cv=none; d=zohomail.com; s=zohoarc; b=eUFENLr1u4a0g4djesEu21UNsqKvth1VJbJHBPUz4y+jMZgVePHMrRoLuGmAo1vFg5w8PO4dgFG5HS3T4gogkoVAssCA95sqOUkaAnei/ECRbnEUaYhVlNsCua8wv/BwLO3aNZ468KJrpvGNZ3p6wCL6q7N3v+EaPw3aNAETtu8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758032726; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=942WePPhlrG9gooEEWu4vpO7ddNWZ/8t+XFAij4Q59o=; b=AmQAilOY0k9wB1dEbaQc4Q/WGN16/quA6seUT0aqNWhICzstXB+t7S3D51CSArEO8XKxTSHEUvnEO4prSu3KL0AEFZZTRm5o3cMFKCq3SAK1yZR0J6oovkjZ6oBpBVCLoCjAgYGL3h/46KzfttTSf/HLznha8t1mbT54saU+HrA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175803272658765.6663196577856; Tue, 16 Sep 2025 07:25:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uyWaX-0005uR-87; Tue, 16 Sep 2025 10:23:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uyWa9-0005k3-4B for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:22:59 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uyWZz-0008I0-Rg for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:22:53 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-25caef29325so48616095ad.2 for ; Tue, 16 Sep 2025 07:22:45 -0700 (PDT) Received: from stoup.. ([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2651d2df15esm73459905ad.45.2025.09.16.07.22.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 07:22:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758032564; x=1758637364; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=942WePPhlrG9gooEEWu4vpO7ddNWZ/8t+XFAij4Q59o=; b=u/DU9OewFJy7IbV5ga++dqIY61fLGRcnrkhD+0cRnlrKHoLeSgfkuoBPE96iWYKKUz 64ug5ukVdKPtvofhB7NHE+TlYfwiGf7JdEN1GXRWDXW5vW6ryVIhiOdbcOJ1xS2sjYQO 7tl4X48PipYGNWmUg2uAkHxM5GOq00bGQQ7RXi7CEP+6LmF9Pc9JV/5taB4FsU2rjGbW tGk/Kp83tN9aOQt42v1Ige0naPIv+ImMEEU/20iK1d/2wW2l8DunwlHgyDKSkpeMLxYT Lrh445s9PK1dZJZBK+1UwvsbFRrSsoNgGGGqCwDx4sAo+uhdk7ritf/IjSarKM+XJEzV g6Tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758032564; x=1758637364; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=942WePPhlrG9gooEEWu4vpO7ddNWZ/8t+XFAij4Q59o=; b=tFWP8ROP07lDuY462yFmA8tUfnnarUgeLF/Pch4nPrLSuSU4Y6XGRPL5RdMmyKZDHG Wy86rSGBCh0DpI//tFstWxEObp2PANaSyHR20O84tmjRZ8unUlw6+WFBPFCPM9RnWeJZ 79MG8Y88Z+mOSKPRYvuPRonNvHfn3RSkAlT7U/z6fqScosmjB2i4Mu+Gu+pdBDNUR2qc rctu+QjIhzOaFeF82BNbnrmW/NHvglALzZPxn6oSkqIOr4uJw9YX9Kpcr9Rb5dG4oIVT AZHV8uNOHgCz6gu3eqdm0ZbKslPPQSt+Ys0+H75HyUTOAInz2xwzlVud5qIfyzkjqV/0 r3rQ== X-Gm-Message-State: AOJu0Yxe29BzyX2jtf6rehFioj7BGWyqQ7NY148sIGf3qsUeDWeIRtYi M9LgNKEQuSp6aDD+UOecDnFK2eRgTYVcP7vvUGKfHfBTJKNXnbpA0epZvR21lQFUCpUCL4dyDU0 F4o/t X-Gm-Gg: ASbGncurFzjC+NVAp5fV3JX2TggDpbN9u8TyXb/IsM7mwJOSmDVWzTGrpi83xKVrcbQ vAsOkFZkrUJHfA9WKM0y2WoB9TDZFNXhBdqa1KIJF4OKZrarfZswbOAGgC9x09Askkf+d6O7Psq ByuPhfsSWBXxA2qhPHhhL4IuPBY3SKjGEayDalkNKgPB6jiMhL94/hF4lwojDiLquGP8UsmsUuK upS6sjcI1PLHVRAqrHsiAAywaejRsW/r0o0CVSUVb/D2kbxS4v+PFOW/+ANkDX8TiU5OqUTmMP0 XZI04Ar1yJOd2AGRB04UsnTNxmjPAFf1f/LFv0pN7Oi7a/T9GTj1jWqQwCQt/8Rwskt5skDseOE jlfHfj1R1T4X4pdBghztEzN5fyz9+ X-Google-Smtp-Source: AGHT+IGdYWVdIEa78m98YvcoyTCHCMVdHpV5j6yYuZj3bqQgSrnYbYzMkVNFQeMLuh/tItOoSEMPVg== X-Received: by 2002:a17:903:240d:b0:267:ba92:4d3a with SMTP id d9443c01a7336-267ba924f53mr54058185ad.6.1758032563384; Tue, 16 Sep 2025 07:22:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, Manos Pitsidianakis Subject: [PATCH v2 04/36] target/arm/hvf: Reorder DEF_SYSREG arguments Date: Tue, 16 Sep 2025 07:22:05 -0700 Message-ID: <20250916142238.664316-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916142238.664316-1-richard.henderson@linaro.org> References: <20250916142238.664316-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758032728773116600 Content-Type: text/plain; charset="utf-8" The order of the parameters in the Arm ARM is op0, op1, crn, crm, op2 Reorder the arguments of DEF_SYSREG to match. Mechanical change to sysreg.c.inc using sed 's/\([^,]*\),\([^,]*\),\([^,]*\),\([^,]*\),\([^,]*\)/\1,\4,\5,\2,\3/' Reviewed-by: Manos Pitsidianakis Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/hvf/hvf.c | 2 +- target/arm/hvf/sysreg.c.inc | 224 ++++++++++++++++++------------------ 2 files changed, 113 insertions(+), 113 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 9f8e3083b4..f68924ba1f 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -403,7 +403,7 @@ struct hvf_sreg_match { uint32_t cp_idx; }; =20 -#define DEF_SYSREG(HVF_ID, crn, crm, op0, op1, op2) \ +#define DEF_SYSREG(HVF_ID, op0, op1, crn, crm, op2) \ { HVF_ID, HVF_SYSREG(crn, crm, op0, op1, op2) }, =20 static struct hvf_sreg_match hvf_sreg_match[] =3D { diff --git a/target/arm/hvf/sysreg.c.inc b/target/arm/hvf/sysreg.c.inc index 222698f1d1..f2276d534e 100644 --- a/target/arm/hvf/sysreg.c.inc +++ b/target/arm/hvf/sysreg.c.inc @@ -1,146 +1,146 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ =20 -DEF_SYSREG(HV_SYS_REG_DBGBVR0_EL1, 0, 0, 2, 0, 4) -DEF_SYSREG(HV_SYS_REG_DBGBCR0_EL1, 0, 0, 2, 0, 5) -DEF_SYSREG(HV_SYS_REG_DBGWVR0_EL1, 0, 0, 2, 0, 6) -DEF_SYSREG(HV_SYS_REG_DBGWCR0_EL1, 0, 0, 2, 0, 7) +DEF_SYSREG(HV_SYS_REG_DBGBVR0_EL1, 2, 0, 0, 0, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR0_EL1, 2, 0, 0, 0, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR0_EL1, 2, 0, 0, 0, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR0_EL1, 2, 0, 0, 0, 7) =20 -DEF_SYSREG(HV_SYS_REG_DBGBVR1_EL1, 0, 1, 2, 0, 4) -DEF_SYSREG(HV_SYS_REG_DBGBCR1_EL1, 0, 1, 2, 0, 5) -DEF_SYSREG(HV_SYS_REG_DBGWVR1_EL1, 0, 1, 2, 0, 6) -DEF_SYSREG(HV_SYS_REG_DBGWCR1_EL1, 0, 1, 2, 0, 7) +DEF_SYSREG(HV_SYS_REG_DBGBVR1_EL1, 2, 0, 0, 1, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR1_EL1, 2, 0, 0, 1, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR1_EL1, 2, 0, 0, 1, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR1_EL1, 2, 0, 0, 1, 7) =20 -DEF_SYSREG(HV_SYS_REG_DBGBVR2_EL1, 0, 2, 2, 0, 4) -DEF_SYSREG(HV_SYS_REG_DBGBCR2_EL1, 0, 2, 2, 0, 5) -DEF_SYSREG(HV_SYS_REG_DBGWVR2_EL1, 0, 2, 2, 0, 6) -DEF_SYSREG(HV_SYS_REG_DBGWCR2_EL1, 0, 2, 2, 0, 7) +DEF_SYSREG(HV_SYS_REG_DBGBVR2_EL1, 2, 0, 0, 2, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR2_EL1, 2, 0, 0, 2, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR2_EL1, 2, 0, 0, 2, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR2_EL1, 2, 0, 0, 2, 7) =20 -DEF_SYSREG(HV_SYS_REG_DBGBVR3_EL1, 0, 3, 2, 0, 4) -DEF_SYSREG(HV_SYS_REG_DBGBCR3_EL1, 0, 3, 2, 0, 5) -DEF_SYSREG(HV_SYS_REG_DBGWVR3_EL1, 0, 3, 2, 0, 6) -DEF_SYSREG(HV_SYS_REG_DBGWCR3_EL1, 0, 3, 2, 0, 7) +DEF_SYSREG(HV_SYS_REG_DBGBVR3_EL1, 2, 0, 0, 3, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR3_EL1, 2, 0, 0, 3, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR3_EL1, 2, 0, 0, 3, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR3_EL1, 2, 0, 0, 3, 7) =20 -DEF_SYSREG(HV_SYS_REG_DBGBVR4_EL1, 0, 4, 2, 0, 4) -DEF_SYSREG(HV_SYS_REG_DBGBCR4_EL1, 0, 4, 2, 0, 5) -DEF_SYSREG(HV_SYS_REG_DBGWVR4_EL1, 0, 4, 2, 0, 6) -DEF_SYSREG(HV_SYS_REG_DBGWCR4_EL1, 0, 4, 2, 0, 7) +DEF_SYSREG(HV_SYS_REG_DBGBVR4_EL1, 2, 0, 0, 4, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR4_EL1, 2, 0, 0, 4, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR4_EL1, 2, 0, 0, 4, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR4_EL1, 2, 0, 0, 4, 7) =20 -DEF_SYSREG(HV_SYS_REG_DBGBVR5_EL1, 0, 5, 2, 0, 4) -DEF_SYSREG(HV_SYS_REG_DBGBCR5_EL1, 0, 5, 2, 0, 5) -DEF_SYSREG(HV_SYS_REG_DBGWVR5_EL1, 0, 5, 2, 0, 6) -DEF_SYSREG(HV_SYS_REG_DBGWCR5_EL1, 0, 5, 2, 0, 7) +DEF_SYSREG(HV_SYS_REG_DBGBVR5_EL1, 2, 0, 0, 5, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR5_EL1, 2, 0, 0, 5, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR5_EL1, 2, 0, 0, 5, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR5_EL1, 2, 0, 0, 5, 7) =20 -DEF_SYSREG(HV_SYS_REG_DBGBVR6_EL1, 0, 6, 2, 0, 4) -DEF_SYSREG(HV_SYS_REG_DBGBCR6_EL1, 0, 6, 2, 0, 5) -DEF_SYSREG(HV_SYS_REG_DBGWVR6_EL1, 0, 6, 2, 0, 6) -DEF_SYSREG(HV_SYS_REG_DBGWCR6_EL1, 0, 6, 2, 0, 7) +DEF_SYSREG(HV_SYS_REG_DBGBVR6_EL1, 2, 0, 0, 6, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR6_EL1, 2, 0, 0, 6, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR6_EL1, 2, 0, 0, 6, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR6_EL1, 2, 0, 0, 6, 7) =20 -DEF_SYSREG(HV_SYS_REG_DBGBVR7_EL1, 0, 7, 2, 0, 4) -DEF_SYSREG(HV_SYS_REG_DBGBCR7_EL1, 0, 7, 2, 0, 5) -DEF_SYSREG(HV_SYS_REG_DBGWVR7_EL1, 0, 7, 2, 0, 6) -DEF_SYSREG(HV_SYS_REG_DBGWCR7_EL1, 0, 7, 2, 0, 7) +DEF_SYSREG(HV_SYS_REG_DBGBVR7_EL1, 2, 0, 0, 7, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR7_EL1, 2, 0, 0, 7, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR7_EL1, 2, 0, 0, 7, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR7_EL1, 2, 0, 0, 7, 7) =20 -DEF_SYSREG(HV_SYS_REG_DBGBVR8_EL1, 0, 8, 2, 0, 4) -DEF_SYSREG(HV_SYS_REG_DBGBCR8_EL1, 0, 8, 2, 0, 5) -DEF_SYSREG(HV_SYS_REG_DBGWVR8_EL1, 0, 8, 2, 0, 6) -DEF_SYSREG(HV_SYS_REG_DBGWCR8_EL1, 0, 8, 2, 0, 7) +DEF_SYSREG(HV_SYS_REG_DBGBVR8_EL1, 2, 0, 0, 8, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR8_EL1, 2, 0, 0, 8, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR8_EL1, 2, 0, 0, 8, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR8_EL1, 2, 0, 0, 8, 7) =20 -DEF_SYSREG(HV_SYS_REG_DBGBVR9_EL1, 0, 9, 2, 0, 4) -DEF_SYSREG(HV_SYS_REG_DBGBCR9_EL1, 0, 9, 2, 0, 5) -DEF_SYSREG(HV_SYS_REG_DBGWVR9_EL1, 0, 9, 2, 0, 6) -DEF_SYSREG(HV_SYS_REG_DBGWCR9_EL1, 0, 9, 2, 0, 7) +DEF_SYSREG(HV_SYS_REG_DBGBVR9_EL1, 2, 0, 0, 9, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR9_EL1, 2, 0, 0, 9, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR9_EL1, 2, 0, 0, 9, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR9_EL1, 2, 0, 0, 9, 7) =20 -DEF_SYSREG(HV_SYS_REG_DBGBVR10_EL1, 0, 10, 2, 0, 4) -DEF_SYSREG(HV_SYS_REG_DBGBCR10_EL1, 0, 10, 2, 0, 5) -DEF_SYSREG(HV_SYS_REG_DBGWVR10_EL1, 0, 10, 2, 0, 6) -DEF_SYSREG(HV_SYS_REG_DBGWCR10_EL1, 0, 10, 2, 0, 7) +DEF_SYSREG(HV_SYS_REG_DBGBVR10_EL1, 2, 0, 0, 10, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR10_EL1, 2, 0, 0, 10, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR10_EL1, 2, 0, 0, 10, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR10_EL1, 2, 0, 0, 10, 7) =20 -DEF_SYSREG(HV_SYS_REG_DBGBVR11_EL1, 0, 11, 2, 0, 4) -DEF_SYSREG(HV_SYS_REG_DBGBCR11_EL1, 0, 11, 2, 0, 5) -DEF_SYSREG(HV_SYS_REG_DBGWVR11_EL1, 0, 11, 2, 0, 6) -DEF_SYSREG(HV_SYS_REG_DBGWCR11_EL1, 0, 11, 2, 0, 7) +DEF_SYSREG(HV_SYS_REG_DBGBVR11_EL1, 2, 0, 0, 11, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR11_EL1, 2, 0, 0, 11, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR11_EL1, 2, 0, 0, 11, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR11_EL1, 2, 0, 0, 11, 7) =20 -DEF_SYSREG(HV_SYS_REG_DBGBVR12_EL1, 0, 12, 2, 0, 4) -DEF_SYSREG(HV_SYS_REG_DBGBCR12_EL1, 0, 12, 2, 0, 5) -DEF_SYSREG(HV_SYS_REG_DBGWVR12_EL1, 0, 12, 2, 0, 6) -DEF_SYSREG(HV_SYS_REG_DBGWCR12_EL1, 0, 12, 2, 0, 7) +DEF_SYSREG(HV_SYS_REG_DBGBVR12_EL1, 2, 0, 0, 12, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR12_EL1, 2, 0, 0, 12, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR12_EL1, 2, 0, 0, 12, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR12_EL1, 2, 0, 0, 12, 7) =20 -DEF_SYSREG(HV_SYS_REG_DBGBVR13_EL1, 0, 13, 2, 0, 4) -DEF_SYSREG(HV_SYS_REG_DBGBCR13_EL1, 0, 13, 2, 0, 5) -DEF_SYSREG(HV_SYS_REG_DBGWVR13_EL1, 0, 13, 2, 0, 6) -DEF_SYSREG(HV_SYS_REG_DBGWCR13_EL1, 0, 13, 2, 0, 7) +DEF_SYSREG(HV_SYS_REG_DBGBVR13_EL1, 2, 0, 0, 13, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR13_EL1, 2, 0, 0, 13, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR13_EL1, 2, 0, 0, 13, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR13_EL1, 2, 0, 0, 13, 7) =20 -DEF_SYSREG(HV_SYS_REG_DBGBVR14_EL1, 0, 14, 2, 0, 4) -DEF_SYSREG(HV_SYS_REG_DBGBCR14_EL1, 0, 14, 2, 0, 5) -DEF_SYSREG(HV_SYS_REG_DBGWVR14_EL1, 0, 14, 2, 0, 6) -DEF_SYSREG(HV_SYS_REG_DBGWCR14_EL1, 0, 14, 2, 0, 7) +DEF_SYSREG(HV_SYS_REG_DBGBVR14_EL1, 2, 0, 0, 14, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR14_EL1, 2, 0, 0, 14, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR14_EL1, 2, 0, 0, 14, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR14_EL1, 2, 0, 0, 14, 7) =20 -DEF_SYSREG(HV_SYS_REG_DBGBVR15_EL1, 0, 15, 2, 0, 4) -DEF_SYSREG(HV_SYS_REG_DBGBCR15_EL1, 0, 15, 2, 0, 5) -DEF_SYSREG(HV_SYS_REG_DBGWVR15_EL1, 0, 15, 2, 0, 6) -DEF_SYSREG(HV_SYS_REG_DBGWCR15_EL1, 0, 15, 2, 0, 7) +DEF_SYSREG(HV_SYS_REG_DBGBVR15_EL1, 2, 0, 0, 15, 4) +DEF_SYSREG(HV_SYS_REG_DBGBCR15_EL1, 2, 0, 0, 15, 5) +DEF_SYSREG(HV_SYS_REG_DBGWVR15_EL1, 2, 0, 0, 15, 6) +DEF_SYSREG(HV_SYS_REG_DBGWCR15_EL1, 2, 0, 0, 15, 7) =20 #ifdef SYNC_NO_RAW_REGS /* * The registers below are manually synced on init because they are * marked as NO_RAW. We still list them to make number space sync easier. */ -DEF_SYSREG(HV_SYS_REG_MDCCINT_EL1, 0, 2, 2, 0, 0) -DEF_SYSREG(HV_SYS_REG_MIDR_EL1, 0, 0, 3, 0, 0) -DEF_SYSREG(HV_SYS_REG_MPIDR_EL1, 0, 0, 3, 0, 5) -DEF_SYSREG(HV_SYS_REG_ID_AA64PFR0_EL1, 0, 4, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_MDCCINT_EL1, 2, 0, 0, 2, 0) +DEF_SYSREG(HV_SYS_REG_MIDR_EL1, 3, 0, 0, 0, 0) +DEF_SYSREG(HV_SYS_REG_MPIDR_EL1, 3, 0, 0, 0, 5) +DEF_SYSREG(HV_SYS_REG_ID_AA64PFR0_EL1, 3, 0, 0, 4, 0) #endif =20 -DEF_SYSREG(HV_SYS_REG_ID_AA64PFR1_EL1, 0, 4, 3, 0, 1) -DEF_SYSREG(HV_SYS_REG_ID_AA64DFR0_EL1, 0, 5, 3, 0, 0) -DEF_SYSREG(HV_SYS_REG_ID_AA64DFR1_EL1, 0, 5, 3, 0, 1) -DEF_SYSREG(HV_SYS_REG_ID_AA64ISAR0_EL1, 0, 6, 3, 0, 0) -DEF_SYSREG(HV_SYS_REG_ID_AA64ISAR1_EL1, 0, 6, 3, 0, 1) +DEF_SYSREG(HV_SYS_REG_ID_AA64PFR1_EL1, 3, 0, 0, 4, 1) +DEF_SYSREG(HV_SYS_REG_ID_AA64DFR0_EL1, 3, 0, 0, 5, 0) +DEF_SYSREG(HV_SYS_REG_ID_AA64DFR1_EL1, 3, 0, 0, 5, 1) +DEF_SYSREG(HV_SYS_REG_ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0) +DEF_SYSREG(HV_SYS_REG_ID_AA64ISAR1_EL1, 3, 0, 0, 6, 1) =20 #ifdef SYNC_NO_MMFR0 /* We keep the hardware MMFR0 around. HW limits are there anyway */ -DEF_SYSREG(HV_SYS_REG_ID_AA64MMFR0_EL1, 0, 7, 3, 0, 0) +DEF_SYSREG(HV_SYS_REG_ID_AA64MMFR0_EL1, 3, 0, 0, 7, 0) #endif =20 -DEF_SYSREG(HV_SYS_REG_ID_AA64MMFR1_EL1, 0, 7, 3, 0, 1) -DEF_SYSREG(HV_SYS_REG_ID_AA64MMFR2_EL1, 0, 7, 3, 0, 2) +DEF_SYSREG(HV_SYS_REG_ID_AA64MMFR1_EL1, 3, 0, 0, 7, 1) +DEF_SYSREG(HV_SYS_REG_ID_AA64MMFR2_EL1, 3, 0, 0, 7, 2) /* Add ID_AA64MMFR3_EL1 here when HVF supports it */ =20 -DEF_SYSREG(HV_SYS_REG_MDSCR_EL1, 0, 2, 2, 0, 2) -DEF_SYSREG(HV_SYS_REG_SCTLR_EL1, 1, 0, 3, 0, 0) -DEF_SYSREG(HV_SYS_REG_CPACR_EL1, 1, 0, 3, 0, 2) -DEF_SYSREG(HV_SYS_REG_TTBR0_EL1, 2, 0, 3, 0, 0) -DEF_SYSREG(HV_SYS_REG_TTBR1_EL1, 2, 0, 3, 0, 1) -DEF_SYSREG(HV_SYS_REG_TCR_EL1, 2, 0, 3, 0, 2) +DEF_SYSREG(HV_SYS_REG_MDSCR_EL1, 2, 0, 0, 2, 2) +DEF_SYSREG(HV_SYS_REG_SCTLR_EL1, 3, 0, 1, 0, 0) +DEF_SYSREG(HV_SYS_REG_CPACR_EL1, 3, 0, 1, 0, 2) +DEF_SYSREG(HV_SYS_REG_TTBR0_EL1, 3, 0, 2, 0, 0) +DEF_SYSREG(HV_SYS_REG_TTBR1_EL1, 3, 0, 2, 0, 1) +DEF_SYSREG(HV_SYS_REG_TCR_EL1, 3, 0, 2, 0, 2) =20 -DEF_SYSREG(HV_SYS_REG_APIAKEYLO_EL1, 2, 1, 3, 0, 0) -DEF_SYSREG(HV_SYS_REG_APIAKEYHI_EL1, 2, 1, 3, 0, 1) -DEF_SYSREG(HV_SYS_REG_APIBKEYLO_EL1, 2, 1, 3, 0, 2) -DEF_SYSREG(HV_SYS_REG_APIBKEYHI_EL1, 2, 1, 3, 0, 3) -DEF_SYSREG(HV_SYS_REG_APDAKEYLO_EL1, 2, 2, 3, 0, 0) -DEF_SYSREG(HV_SYS_REG_APDAKEYHI_EL1, 2, 2, 3, 0, 1) -DEF_SYSREG(HV_SYS_REG_APDBKEYLO_EL1, 2, 2, 3, 0, 2) -DEF_SYSREG(HV_SYS_REG_APDBKEYHI_EL1, 2, 2, 3, 0, 3) -DEF_SYSREG(HV_SYS_REG_APGAKEYLO_EL1, 2, 3, 3, 0, 0) -DEF_SYSREG(HV_SYS_REG_APGAKEYHI_EL1, 2, 3, 3, 0, 1) +DEF_SYSREG(HV_SYS_REG_APIAKEYLO_EL1, 3, 0, 2, 1, 0) +DEF_SYSREG(HV_SYS_REG_APIAKEYHI_EL1, 3, 0, 2, 1, 1) +DEF_SYSREG(HV_SYS_REG_APIBKEYLO_EL1, 3, 0, 2, 1, 2) +DEF_SYSREG(HV_SYS_REG_APIBKEYHI_EL1, 3, 0, 2, 1, 3) +DEF_SYSREG(HV_SYS_REG_APDAKEYLO_EL1, 3, 0, 2, 2, 0) +DEF_SYSREG(HV_SYS_REG_APDAKEYHI_EL1, 3, 0, 2, 2, 1) +DEF_SYSREG(HV_SYS_REG_APDBKEYLO_EL1, 3, 0, 2, 2, 2) +DEF_SYSREG(HV_SYS_REG_APDBKEYHI_EL1, 3, 0, 2, 2, 3) +DEF_SYSREG(HV_SYS_REG_APGAKEYLO_EL1, 3, 0, 2, 3, 0) +DEF_SYSREG(HV_SYS_REG_APGAKEYHI_EL1, 3, 0, 2, 3, 1) =20 -DEF_SYSREG(HV_SYS_REG_SPSR_EL1, 4, 0, 3, 0, 0) -DEF_SYSREG(HV_SYS_REG_ELR_EL1, 4, 0, 3, 0, 1) -DEF_SYSREG(HV_SYS_REG_SP_EL0, 4, 1, 3, 0, 0) -DEF_SYSREG(HV_SYS_REG_AFSR0_EL1, 5, 1, 3, 0, 0) -DEF_SYSREG(HV_SYS_REG_AFSR1_EL1, 5, 1, 3, 0, 1) -DEF_SYSREG(HV_SYS_REG_ESR_EL1, 5, 2, 3, 0, 0) -DEF_SYSREG(HV_SYS_REG_FAR_EL1, 6, 0, 3, 0, 0) -DEF_SYSREG(HV_SYS_REG_PAR_EL1, 7, 4, 3, 0, 0) -DEF_SYSREG(HV_SYS_REG_MAIR_EL1, 10, 2, 3, 0, 0) -DEF_SYSREG(HV_SYS_REG_AMAIR_EL1, 10, 3, 3, 0, 0) -DEF_SYSREG(HV_SYS_REG_VBAR_EL1, 12, 0, 3, 0, 0) -DEF_SYSREG(HV_SYS_REG_CONTEXTIDR_EL1, 13, 0, 3, 0, 1) -DEF_SYSREG(HV_SYS_REG_TPIDR_EL1, 13, 0, 3, 0, 4) -DEF_SYSREG(HV_SYS_REG_CNTKCTL_EL1, 14, 1, 3, 0, 0) -DEF_SYSREG(HV_SYS_REG_CSSELR_EL1, 0, 0, 3, 2, 0) -DEF_SYSREG(HV_SYS_REG_TPIDR_EL0, 13, 0, 3, 3, 2) -DEF_SYSREG(HV_SYS_REG_TPIDRRO_EL0, 13, 0, 3, 3, 3) -DEF_SYSREG(HV_SYS_REG_CNTV_CTL_EL0, 14, 3, 3, 3, 1) -DEF_SYSREG(HV_SYS_REG_CNTV_CVAL_EL0, 14, 3, 3, 3, 2) -DEF_SYSREG(HV_SYS_REG_SP_EL1, 4, 1, 3, 4, 0) +DEF_SYSREG(HV_SYS_REG_SPSR_EL1, 3, 0, 4, 0, 0) +DEF_SYSREG(HV_SYS_REG_ELR_EL1, 3, 0, 4, 0, 1) +DEF_SYSREG(HV_SYS_REG_SP_EL0, 3, 0, 4, 1, 0) +DEF_SYSREG(HV_SYS_REG_AFSR0_EL1, 3, 0, 5, 1, 0) +DEF_SYSREG(HV_SYS_REG_AFSR1_EL1, 3, 0, 5, 1, 1) +DEF_SYSREG(HV_SYS_REG_ESR_EL1, 3, 0, 5, 2, 0) +DEF_SYSREG(HV_SYS_REG_FAR_EL1, 3, 0, 6, 0, 0) +DEF_SYSREG(HV_SYS_REG_PAR_EL1, 3, 0, 7, 4, 0) +DEF_SYSREG(HV_SYS_REG_MAIR_EL1, 3, 0, 10, 2, 0) +DEF_SYSREG(HV_SYS_REG_AMAIR_EL1, 3, 0, 10, 3, 0) +DEF_SYSREG(HV_SYS_REG_VBAR_EL1, 3, 0, 12, 0, 0) +DEF_SYSREG(HV_SYS_REG_CONTEXTIDR_EL1, 3, 0, 13, 0, 1) +DEF_SYSREG(HV_SYS_REG_TPIDR_EL1, 3, 0, 13, 0, 4) +DEF_SYSREG(HV_SYS_REG_CNTKCTL_EL1, 3, 0, 14, 1, 0) +DEF_SYSREG(HV_SYS_REG_CSSELR_EL1, 3, 2, 0, 0, 0) +DEF_SYSREG(HV_SYS_REG_TPIDR_EL0, 3, 3, 13, 0, 2) +DEF_SYSREG(HV_SYS_REG_TPIDRRO_EL0, 3, 3, 13, 0, 3) +DEF_SYSREG(HV_SYS_REG_CNTV_CTL_EL0, 3, 3, 14, 3, 1) +DEF_SYSREG(HV_SYS_REG_CNTV_CVAL_EL0, 3, 3, 14, 3, 2) +DEF_SYSREG(HV_SYS_REG_SP_EL1, 3, 4, 4, 1, 0) --=20 2.43.0 From nobody Sun Sep 28 16:37:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2651d2df15esm73459905ad.45.2025.09.16.07.22.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 07:22:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758032564; x=1758637364; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QcyFmSED1U74WI9UXgtn2Nss5f/zzYuv4zo9qx3ZJkk=; b=K/wn7zA+v3WfQFi3s6rOOs3uOS+6RMNDB4Fqtwj2O0TzQlGULj4ul0mXYk/FJfYnkn 5jmYUrR4zcaooybQ2fiJdekFcsPyWzUFhZd6/3vF7trpBEf08LOuq+SSiSqsEgjZHUa3 oUZx9l+RCCT+4HSDhbkbit0syllM98pKnWGk+G2AMd1VX9szKVMZq+nYGhmhYA7qighp NyKg01KXbe5mC1weJ2g0JMh+Trynbi1Jl9xjR+/Mt2NdE8hMYWaPPqPDCHTeAqYMjul7 uFmbFIPUr7R3+6myPVtujXteSp79yPnrbugEpzNa8XVceivUcPnhsCFY5/UMOz2U/pzC OCew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758032564; x=1758637364; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QcyFmSED1U74WI9UXgtn2Nss5f/zzYuv4zo9qx3ZJkk=; b=iDE5f0Dy0MN5tyGq1EVv01R8Auw2GkHKgUaUonMFpxx/lSFZYdsVevhJd8v6pms7An ya45BbogL82+PzGpWbHUb+NJFcGgsKfjgbteL/+spaanResjUN+ztStAAaSqAKp6lzyw CKqyjY+vxsVCYvaqNMacgu6sRnizFIo4k6ZsmenZWviAWLSVGSC+BeTJOddZIDPPC3RF FnebxvrvMkC4egIx3J660rrXJiA5Dg8UckrAYhtBELERUIYiwiEYwPUEMI0YK7jat+Qi ZXVTXosT+IUG8BH2dZfp0mbA6b9BtCWo/ma8yEqNDPx6PGx53e2cADr1vnurzM/nWSNA hXnw== X-Gm-Message-State: AOJu0YzB4cy0zfSQHAaMerOx8mAXcTquV0WBDcGmm2B5kXjKGC7yZYeY WpZceopGH86xGr2jtFLfJVe1nMKRyzkArZ2JtCVmOCGazJC1gRU03qoTBDgx8CXCkkLwAFDzfWS mzE2b X-Gm-Gg: ASbGncusVt/WcoOWRFnLSj7Vr3vOIWnxjvy0DPpbK91AEwpefqAvMjjFmh/94Dudmor wmAGTmbjcS5UV91oy4/XIpN6LAY0GnbMGBYOayrWgeBIGbBB4+XZn8J0KWTwcelRok1qQ3CVvYZ Xm7tLdUmUjPVsStUH6/md5WemLOWD259S2IB+UP+zIucVcQ7JUgekKb1WZxnwZtISDGo8i5G4vn OyG4EmSmgP1DOkJsdtDKAzUbwZ5YPg38rwXrxjOwAgAuNgP5O7sB4cRAVXJnGcoSQIiFxsM12hx 3OpGjDjduUohaPdy31Hie2hMfppAvOOayR3gHBkO+VQLoakYwodbMUHwNck+qHcALBjHgtYOUiY syvdGONuTC+YxzUs3AIkYOMhoOWDm X-Google-Smtp-Source: AGHT+IFO9aLpqlUq4ALNHy4YL2aoDcdWvGCLnoR53xQbmihLpHzayoUaY7Jvd2er+TwKrjBfNG305w== X-Received: by 2002:a17:902:cecf:b0:24d:a3a0:5230 with SMTP id d9443c01a7336-25d27131d84mr259931945ad.58.1758032563990; Tue, 16 Sep 2025 07:22:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, Manos Pitsidianakis Subject: [PATCH v2 05/36] target/arm/hvf: Add KVMID_TO_HVF, HVF_TO_KVMID Date: Tue, 16 Sep 2025 07:22:06 -0700 Message-ID: <20250916142238.664316-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916142238.664316-1-richard.henderson@linaro.org> References: <20250916142238.664316-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758032761241116601 Content-Type: text/plain; charset="utf-8" Conversion between KVM system registers ids and the HVF system register ids is trivial. Reviewed-by: Manos Pitsidianakis Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/hvf/hvf.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index f68924ba1f..7515e59c56 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -403,6 +403,26 @@ struct hvf_sreg_match { uint32_t cp_idx; }; =20 +/* + * QEMU uses KVM system register ids in the migration format. + * Conveniently, HVF uses the same encoding of the op* and cr* parameters + * within the low 16 bits of the ids. Thus conversion between the + * formats is trivial. + */ + +#define KVMID_TO_HVF(KVM) ((KVM) & 0xffff) +#define HVF_TO_KVMID(HVF) \ + (CP_REG_ARM64 | CP_REG_SIZE_U64 | CP_REG_ARM64_SYSREG | (HVF)) + +/* Verify this at compile-time. */ + +#define DEF_SYSREG(HVF_ID, ...) \ + QEMU_BUILD_BUG_ON(HVF_ID !=3D KVMID_TO_HVF(KVMID_AA64_SYS_REG64(__VA_ARG= S__))); + +#include "sysreg.c.inc" + +#undef DEF_SYSREG + #define DEF_SYSREG(HVF_ID, op0, op1, crn, crm, op2) \ { HVF_ID, HVF_SYSREG(crn, crm, op0, op1, op2) }, =20 --=20 2.43.0 From nobody Sun Sep 28 16:37:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758033278; cv=none; d=zohomail.com; s=zohoarc; b=AvwR3YW89SRqk0IqQTMEagt6e2bX18R39FPuA3MvpztH1iNRANjdxWNMoCaLOIb/AyeFJMYmOM3FK3U46yjkM3G45c/rO/AMd4TXNZEWe4m2sA/Cq60krJLUI7feUG0dczFIOgzuepmhxnxmQxjkKg8gR2ajo+d0xskcQ/Z/1fQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758033278; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=xrsLIYa/QaAtepVhdLt9uWw8TsTHaDZ3hg9nTee82WI=; b=CfEUGtHMeELOgorZIqa+3EFuVcc0rSKYSI9Zfx+cI9AvUO5IdNPBYdc+jVCN3842v0AQFT80CC5y2KBiBafwSBpj11OtR4ZSm6aut1lDKy0goIZwDb/dOKRCR3rCV2at2qk4Y0va/Bc6QmwtqxcFT3xDStSsjyZ0vmpOtwhWieA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758033278388973.7890801466963; Tue, 16 Sep 2025 07:34:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uyWap-0006Is-V9; Tue, 16 Sep 2025 10:23:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uyWaC-0005lR-PK for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:23:07 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uyWa7-0008IP-Ky for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:22:58 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-261682fdfceso27761165ad.1 for ; Tue, 16 Sep 2025 07:22:46 -0700 (PDT) Received: from stoup.. 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Reviewed-by: Manos Pitsidianakis Signed-off-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/hvf/hvf.c | 35 +++++++++++++++++++---------------- 1 file changed, 19 insertions(+), 16 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 7515e59c56..98f49ce33a 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -152,9 +152,6 @@ void hvf_arm_init_debug(void) g_array_sized_new(true, true, sizeof(HWWatchpoint), max_hw_wps); } =20 -#define HVF_SYSREG(crn, crm, op0, op1, op2) \ - ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2) - #define SYSREG_OP0_SHIFT 20 #define SYSREG_OP0_MASK 0x3 #define SYSREG_OP0(sysreg) ((sysreg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_M= ASK) @@ -399,7 +396,6 @@ static const struct hvf_reg_match hvf_fpreg_match[] =3D= { =20 struct hvf_sreg_match { int reg; - uint32_t key; uint32_t cp_idx; }; =20 @@ -423,8 +419,7 @@ struct hvf_sreg_match { =20 #undef DEF_SYSREG =20 -#define DEF_SYSREG(HVF_ID, op0, op1, crn, crm, op2) \ - { HVF_ID, HVF_SYSREG(crn, crm, op0, op1, op2) }, +#define DEF_SYSREG(HVF_ID, op0, op1, crn, crm, op2) { HVF_ID }, =20 static struct hvf_sreg_match hvf_sreg_match[] =3D { #include "sysreg.c.inc" @@ -469,13 +464,16 @@ int hvf_get_registers(CPUState *cpu) pstate_write(env, val); =20 for (i =3D 0; i < ARRAY_SIZE(hvf_sreg_match); i++) { + int hvf_id =3D hvf_sreg_match[i].reg; + uint64_t kvm_id =3D HVF_TO_KVMID(hvf_id); + if (hvf_sreg_match[i].cp_idx =3D=3D -1) { continue; } =20 if (cpu->accel->guest_debug_enabled) { /* Handle debug registers */ - switch (hvf_sreg_match[i].reg) { + switch (hvf_id) { case HV_SYS_REG_DBGBVR0_EL1: case HV_SYS_REG_DBGBCR0_EL1: case HV_SYS_REG_DBGWVR0_EL1: @@ -549,8 +547,10 @@ int hvf_get_registers(CPUState *cpu) * vCPU but simply keep the values from the previous * environment. */ - const ARMCPRegInfo *ri; - ri =3D get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_sreg_match= [i].key); + uint32_t key =3D kvm_to_cpreg_id(kvm_id); + const ARMCPRegInfo *ri =3D + get_arm_cp_reginfo(arm_cpu->cp_regs, key); + val =3D read_raw_cp_reg(env, ri); =20 arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] =3D val; @@ -559,7 +559,7 @@ int hvf_get_registers(CPUState *cpu) } } =20 - ret =3D hv_vcpu_get_sys_reg(cpu->accel->fd, hvf_sreg_match[i].reg,= &val); + ret =3D hv_vcpu_get_sys_reg(cpu->accel->fd, hvf_id, &val); assert_hvf_ok(ret); =20 arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] =3D val; @@ -606,13 +606,15 @@ int hvf_put_registers(CPUState *cpu) =20 assert(write_cpustate_to_list(arm_cpu, false)); for (i =3D 0; i < ARRAY_SIZE(hvf_sreg_match); i++) { + int hvf_id =3D hvf_sreg_match[i].reg; + if (hvf_sreg_match[i].cp_idx =3D=3D -1) { continue; } =20 if (cpu->accel->guest_debug_enabled) { /* Handle debug registers */ - switch (hvf_sreg_match[i].reg) { + switch (hvf_id) { case HV_SYS_REG_DBGBVR0_EL1: case HV_SYS_REG_DBGBCR0_EL1: case HV_SYS_REG_DBGWVR0_EL1: @@ -687,7 +689,7 @@ int hvf_put_registers(CPUState *cpu) } =20 val =3D arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx]; - ret =3D hv_vcpu_set_sys_reg(cpu->accel->fd, hvf_sreg_match[i].reg,= val); + ret =3D hv_vcpu_set_sys_reg(cpu->accel->fd, hvf_id, val); assert_hvf_ok(ret); } =20 @@ -922,14 +924,15 @@ int hvf_arch_init_vcpu(CPUState *cpu) =20 /* Populate cp list for all known sysregs */ for (i =3D 0; i < sregs_match_len; i++) { - const ARMCPRegInfo *ri; - uint32_t key =3D hvf_sreg_match[i].key; + int hvf_id =3D hvf_sreg_match[i].reg; + uint64_t kvm_id =3D HVF_TO_KVMID(hvf_id); + uint32_t key =3D kvm_to_cpreg_id(kvm_id); + const ARMCPRegInfo *ri =3D get_arm_cp_reginfo(arm_cpu->cp_regs, ke= y); =20 - ri =3D get_arm_cp_reginfo(arm_cpu->cp_regs, key); if (ri) { assert(!(ri->type & ARM_CP_NO_RAW)); hvf_sreg_match[i].cp_idx =3D sregs_cnt; - arm_cpu->cpreg_indexes[sregs_cnt++] =3D cpreg_to_kvm_id(key); + arm_cpu->cpreg_indexes[sregs_cnt++] =3D kvm_id; } else { hvf_sreg_match[i].cp_idx =3D -1; } --=20 2.43.0 From nobody Sun Sep 28 16:37:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758032769; cv=none; d=zohomail.com; s=zohoarc; b=koVKai9ffIQLIFiACAwyZr/mFSfZTZ49kACj0ct5kr8lX6b4pabSGpp+F8YVerk+q3iU4et9ZLlfm6Z7hMfAtTnUYl2/yPvOkpexmMkZqUZaHnK3d/ArR1nNdUKhQBvjYypc4EOv2uQt3j5FJ3eXHeHjLZzSS3NbNfblvNpHRWY= ARC-Message-Signature: i=1; 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This lets us drop the cp_idx member of hvf_sreg_match, which leaves only one member in the struct. Replace the struct with a const array. Instead of int, use the proper enum type: hv_sys_reg_t. Rename from hvf_sreg_match to hvf_sreg_list because there is no longer any matching going on. Signed-off-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/hvf/hvf.c | 45 +++++++++++++++----------------------------- 1 file changed, 15 insertions(+), 30 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 98f49ce33a..b043eac8c6 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -394,11 +394,6 @@ static const struct hvf_reg_match hvf_fpreg_match[] = =3D { { HV_SIMD_FP_REG_Q31, offsetof(CPUARMState, vfp.zregs[31]) }, }; =20 -struct hvf_sreg_match { - int reg; - uint32_t cp_idx; -}; - /* * QEMU uses KVM system register ids in the migration format. * Conveniently, HVF uses the same encoding of the op* and cr* parameters @@ -419,9 +414,9 @@ struct hvf_sreg_match { =20 #undef DEF_SYSREG =20 -#define DEF_SYSREG(HVF_ID, op0, op1, crn, crm, op2) { HVF_ID }, +#define DEF_SYSREG(HVF_ID, op0, op1, crn, crm, op2) HVF_ID, =20 -static struct hvf_sreg_match hvf_sreg_match[] =3D { +static const hv_sys_reg_t hvf_sreg_list[] =3D { #include "sysreg.c.inc" }; =20 @@ -434,7 +429,7 @@ int hvf_get_registers(CPUState *cpu) hv_return_t ret; uint64_t val; hv_simd_fp_uchar16_t fpval; - int i; + int i, n; =20 for (i =3D 0; i < ARRAY_SIZE(hvf_reg_match); i++) { ret =3D hv_vcpu_get_reg(cpu->accel->fd, hvf_reg_match[i].reg, &val= ); @@ -463,13 +458,9 @@ int hvf_get_registers(CPUState *cpu) assert_hvf_ok(ret); pstate_write(env, val); =20 - for (i =3D 0; i < ARRAY_SIZE(hvf_sreg_match); i++) { - int hvf_id =3D hvf_sreg_match[i].reg; - uint64_t kvm_id =3D HVF_TO_KVMID(hvf_id); - - if (hvf_sreg_match[i].cp_idx =3D=3D -1) { - continue; - } + for (i =3D 0, n =3D arm_cpu->cpreg_array_len; i < n; i++) { + uint64_t kvm_id =3D arm_cpu->cpreg_indexes[i]; + int hvf_id =3D KVMID_TO_HVF(kvm_id); =20 if (cpu->accel->guest_debug_enabled) { /* Handle debug registers */ @@ -553,7 +544,7 @@ int hvf_get_registers(CPUState *cpu) =20 val =3D read_raw_cp_reg(env, ri); =20 - arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] =3D val; + arm_cpu->cpreg_values[i] =3D val; continue; } } @@ -562,7 +553,7 @@ int hvf_get_registers(CPUState *cpu) ret =3D hv_vcpu_get_sys_reg(cpu->accel->fd, hvf_id, &val); assert_hvf_ok(ret); =20 - arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] =3D val; + arm_cpu->cpreg_values[i] =3D val; } assert(write_list_to_cpustate(arm_cpu)); =20 @@ -578,7 +569,7 @@ int hvf_put_registers(CPUState *cpu) hv_return_t ret; uint64_t val; hv_simd_fp_uchar16_t fpval; - int i; + int i, n; =20 for (i =3D 0; i < ARRAY_SIZE(hvf_reg_match); i++) { val =3D *(uint64_t *)((void *)env + hvf_reg_match[i].offset); @@ -605,12 +596,9 @@ int hvf_put_registers(CPUState *cpu) aarch64_save_sp(env, arm_current_el(env)); =20 assert(write_cpustate_to_list(arm_cpu, false)); - for (i =3D 0; i < ARRAY_SIZE(hvf_sreg_match); i++) { - int hvf_id =3D hvf_sreg_match[i].reg; - - if (hvf_sreg_match[i].cp_idx =3D=3D -1) { - continue; - } + for (i =3D 0, n =3D arm_cpu->cpreg_array_len; i < n; i++) { + uint64_t kvm_id =3D arm_cpu->cpreg_indexes[i]; + int hvf_id =3D KVMID_TO_HVF(kvm_id); =20 if (cpu->accel->guest_debug_enabled) { /* Handle debug registers */ @@ -688,7 +676,7 @@ int hvf_put_registers(CPUState *cpu) } } =20 - val =3D arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx]; + val =3D arm_cpu->cpreg_values[i]; ret =3D hv_vcpu_set_sys_reg(cpu->accel->fd, hvf_id, val); assert_hvf_ok(ret); } @@ -899,7 +887,7 @@ int hvf_arch_init_vcpu(CPUState *cpu) { ARMCPU *arm_cpu =3D ARM_CPU(cpu); CPUARMState *env =3D &arm_cpu->env; - uint32_t sregs_match_len =3D ARRAY_SIZE(hvf_sreg_match); + uint32_t sregs_match_len =3D ARRAY_SIZE(hvf_sreg_list); uint32_t sregs_cnt =3D 0; uint64_t pfr; hv_return_t ret; @@ -924,17 +912,14 @@ int hvf_arch_init_vcpu(CPUState *cpu) =20 /* Populate cp list for all known sysregs */ for (i =3D 0; i < sregs_match_len; i++) { - int hvf_id =3D hvf_sreg_match[i].reg; + hv_sys_reg_t hvf_id =3D hvf_sreg_list[i]; uint64_t kvm_id =3D HVF_TO_KVMID(hvf_id); uint32_t key =3D kvm_to_cpreg_id(kvm_id); const ARMCPRegInfo *ri =3D get_arm_cp_reginfo(arm_cpu->cp_regs, ke= y); =20 if (ri) { assert(!(ri->type & ARM_CP_NO_RAW)); - hvf_sreg_match[i].cp_idx =3D sregs_cnt; arm_cpu->cpreg_indexes[sregs_cnt++] =3D kvm_id; - } else { - hvf_sreg_match[i].cp_idx =3D -1; } } arm_cpu->cpreg_array_len =3D sregs_cnt; --=20 2.43.0 From nobody Sun Sep 28 16:37:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758032807; cv=none; d=zohomail.com; s=zohoarc; b=I8muftwI+a7gbOR8+1blmpji7GWCWGKscQr4zh5nEt2z+KAp0Pd2+zOhK/4x4Z+0FtYcAzqotB+p7S45yY3feNlYUyf8fE5HSnrab12w3UZ3RqzM6pdkPX2ADB/K11pZoSp+sagV6eZFFQ6N3r55wTzdTRjD4xHczDdN29RHBf0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758032807; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Tue, 16 Sep 2025 07:22:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v2 08/36] target/arm/hvf: Sort the cpreg_indexes array Date: Tue, 16 Sep 2025 07:22:09 -0700 Message-ID: <20250916142238.664316-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916142238.664316-1-richard.henderson@linaro.org> References: <20250916142238.664316-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758032809742116600 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/hvf/hvf.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index b043eac8c6..99d8672b9b 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -925,6 +925,9 @@ int hvf_arch_init_vcpu(CPUState *cpu) arm_cpu->cpreg_array_len =3D sregs_cnt; arm_cpu->cpreg_vmstate_array_len =3D sregs_cnt; =20 + /* cpreg tuples must be in strictly ascending order */ + qsort(arm_cpu->cpreg_indexes, sregs_cnt, sizeof(uint64_t), compare_u64= ); + assert(write_cpustate_to_list(arm_cpu, false)); =20 /* Set CP_NO_RAW system registers on init */ --=20 2.43.0 From nobody Sun Sep 28 16:37:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2651d2df15esm73459905ad.45.2025.09.16.07.22.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 07:22:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758032567; x=1758637367; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZH0mjB8So3ur3KXNJMzLcfZFHoI3w+OVbUHK09CkjfQ=; b=ri8/oyhVzcYjI6fJtE1HND5l+cMhBbLAJ2SwUZFP2rPA/Juia/8zVIgmxlWd1y03dJ cDB64/JoJa2pkpOgki1BTEWaj6DI0xYYq2lWDrlRUYzSfA88MJfiRZ+RItj6ttiAY4Ir H1TnT9Z9m0xNS36I8AHeYxD+5GaxGAmaUUH1utXH8trdYzDO9214rXhaAvQPvDcHCE4+ v1kF5iB2Nc/5UyOmKS06VvRtFcd7qmCAlRjoI3e83s07KmmKBKLl2z7Zyv8WxiDu08HG AuRpNfbGb4axRq2vW0J7GK+v92vOw13w3onDAloMMHz0pd3bLmrBiqbiEXTEoqisIJfA L5Hw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758032567; x=1758637367; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZH0mjB8So3ur3KXNJMzLcfZFHoI3w+OVbUHK09CkjfQ=; b=olbFJTDkUByuefPTOl33XFv9+8w66XaEwmur5x3NCNg9PJNDDFdaSy5EeqEF3ToHub LNQT9FYMFg5pb9ifTOqopGuZ3ML0CkOAnNXt4JF4jnXvgiKAxLH4QfCo4uEOKnM1K9A5 RxYSDUVq3c2KrJU014zc7e6ZWTMdv8o4SpgKhv6EesIpfCRsVzcImr1MChGw1YNnI5D5 PZT/UpsDN+b2wDU07LpNONoqTNrAsWgrSYjfpE+bkillkXSqN+8IsRKfm7v+aI6HE9GT ye8La0UHFygdi2koKa1Krizd2W4gNR6nZoE21zwH4fzIVNY3fISm3dC5tEBasF4rlJ9X Bffw== X-Gm-Message-State: AOJu0YxWuMHm2wCnliALB0Q5y34Oz4MBlBaFU9DqHRjLZNdgr63OBq9T j6nqKNQFkaAdthY6qUqUAKPp4roTDYzHvyoJSR7HB8iBNeLzdr0YdfeImN+vf8ILfzFkvgWDmnk VcR/3 X-Gm-Gg: ASbGncuTKSypBBy68YVaQwCLdMrNkLQMzJ4LKd8ugNGRVlNpg063wwJQWAm9RFRA+DM sThzC90ARoebHD5glgi9S0ghHuYGfTKVUr6PBFLSCoan6pRuHGi6/ql1COA/mQ+HRlnU38cczuR nEIS17689wNuh7WpBxlKvUeozZvJSv0OVXnL1Bg0vGdkj5CEtMhS9DEHOTZbaot38U8IkBAaCRi tmzfhvqp58yiRdZU0UVMbkrcfY5sFvS1zWCf58SKuir/wLnmzNUIoKNQ95ta5bzXDoQTXAlOtMb 4ZNcSK8nDTsJ0yvBsG0egQPM6hNvw7WB2cDKRg57VOL3AfGFG5dkU5W9q1TUhyMyp30tEmmRFVg KQV0y1o/9kOUtu5f3S62jx+8iais9AVEb1P31zQY= X-Google-Smtp-Source: AGHT+IG+v3H3/O7Wr4EKQVM8edjAxAdCdo/aABxMlATr82uHWyL3hoOKbDN+lOcn/r4nSc30WgXFuQ== X-Received: by 2002:a17:903:478d:b0:264:8a8d:92dd with SMTP id d9443c01a7336-2648a8da428mr133255525ad.20.1758032567416; Tue, 16 Sep 2025 07:22:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v2 09/36] target/arm/hvf: Use raw_read, raw_write to access Date: Tue, 16 Sep 2025 07:22:10 -0700 Message-ID: <20250916142238.664316-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916142238.664316-1-richard.henderson@linaro.org> References: <20250916142238.664316-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758033067464116600 Content-Type: text/plain; charset="utf-8" Reduce the places that know about field types by 2. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/hvf/hvf.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 99d8672b9b..694584cc13 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1153,7 +1153,7 @@ static bool hvf_sysreg_read_cp(CPUState *cpu, uint32_= t reg, uint64_t *val) } else if (ri->readfn) { *val =3D ri->readfn(env, ri); } else { - *val =3D CPREG_FIELD64(env, ri); + *val =3D raw_read(env, ri); } trace_hvf_vgic_read(ri->name, *val); return true; @@ -1435,7 +1435,7 @@ static bool hvf_sysreg_write_cp(CPUState *cpu, uint32= _t reg, uint64_t val) if (ri->writefn) { ri->writefn(env, ri, val); } else { - CPREG_FIELD64(env, ri) =3D val; + raw_write(env, ri, val); } =20 trace_hvf_vgic_write(ri->name, val); --=20 2.43.0 From nobody Sun Sep 28 16:37:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758032988; cv=none; d=zohomail.com; s=zohoarc; b=earK8/ubZo6T758RPuqoxbAbVdwNoiaUwxFGTV0/3ybz/do9oGJZPSyfDiS9T17+x0xqnLlDg3gy2W+YogFqUVtoPbexK2Yy/ac4wEfrtMw2kUbpruah8MkIDE3ckOeLjoTW6IPFu92Td9PsJKOuKtwwKDKA8ed0p3/n/oSYouc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758032988; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=/1Z+zGdBvcvJv/ItuHePFPF4VkGGlPqEflFLb1drkmY=; b=RuM9sWkRAgpTZTq4pM0cjYGhREXIVey7yOrWtOoyizyrSxBDbqOFGePP9NelBflOi9U7BC93ItIccUaUYy5i3n8AiBwrWtwrLaMaU0GXHQgTXefzmXv2xe8ZQMJrO3b8WsnxWsJvQoyQtveUQIFx/idnljm9aI2exdd+w8EK9Dg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758032988292658.4092396537559; Tue, 16 Sep 2025 07:29:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uyWcw-0000gA-2d; Tue, 16 Sep 2025 10:25:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uyWaL-0005nu-Ko for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:23:11 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uyWaB-0008JP-G8 for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:23:02 -0400 Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-264417f3a26so20495725ad.0 for ; Tue, 16 Sep 2025 07:22:49 -0700 (PDT) Received: from stoup.. ([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2651d2df15esm73459905ad.45.2025.09.16.07.22.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 07:22:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758032568; x=1758637368; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/1Z+zGdBvcvJv/ItuHePFPF4VkGGlPqEflFLb1drkmY=; b=tL49jcOD4qJpcO1BffdGEugL/KZOIBtZTmfqY0HwvXJ7jG4xDEmku3zdRW6gsSrFrV KwMhHGclQpL0EX/45wkt1G1VZDy0G9tE2zzPVlRydrY3u5OVImf9J0MIWoWNbPmPi+xf Y0+XdqUQeTJutCQ0XyKFGtDsgFHb7lPbqC0b4Ag29fFMaMuB6Cayj4P/Esj4eRL4NGm8 lTCYcnj53tZac9/jIPaSRRAqu01UQzD5yXMouv2yZsuQTByVNQ7v2YnS8P4fPvY86tkn fOvx9fSkGrMvif3uu3hio9HRq5Y/LR3iU5RXuzC84rj6C34DeDA8zQ1cgU+tgFP5qLNL lYpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758032568; x=1758637368; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/1Z+zGdBvcvJv/ItuHePFPF4VkGGlPqEflFLb1drkmY=; b=Mt9iUIASslEb01vrGK84F6v7UTsgvnd9yI3RnVUWOJhW4puJxu9dI13/9RXebRx7la Jsm34JbDE+CY3TJ0SLWst/67lLhcq/vlUhzNcVBLHYEYe5dkcODy31Is0YZYdr0xt7of lkxe8OUno06wKSQgGiw59nyyN+UaEu0z4nyjBmnLZ5CqCAlihUXXdTVjTMUDJsWpJgOY oPFslArEWy1fBql8MUbknG/Z5lhBVErJr7RNwpA3YHFF66eI/N9nSdr+CGl83zFnvsF9 9cLpOk1FNcbAetDxXmyE9YT2mEDsrBuH32xd7dijhcRiy0nD2/RbVcR/JzhBN2GzWTx7 vxtQ== X-Gm-Message-State: AOJu0Yzc4mI+p1GgDHp6PUVqwyKKg1LHEnJ4fxrf/4Ni0QixN9r78644 gMYRsrRZLczr2KrnzV/ajJuOzS0CYRTD5UULslDFdFBU1Z51DZ6ZvpOnOZQ9hkEYbR72jzmexA7 RyCjL X-Gm-Gg: ASbGncs1bTTwyvhhEUEe528nBCjtPehi9GbKImrSiZlE38LHLxgLsqVaZ1TneBXzl2b +8yMbFCr/YfYEgVV5uoMVD6yR3d+WUqQ+t/ZNtOFCP/r3l6PK0Ww+CZNF0jlaR5T7T8cL+c7VDX 1WEUWigPOZ/fTt53ubsWXluYLKTku7uJYWUJuzOIJSlpXhCMtHvz2Kre7r3piwokCT5wH/CYHL4 APY1LUAuZPqaNknvrliMds9eF9PcMk2CfLlDEWoktHsOHje3a4Wawuv5J0vqEb+6JspbrjrfIaM ZBGQzTkvKHmWJAKAwVNqw1+7rR2RoWFb1kwvwFC2Q8uXkKRX56qHbABfO2PUENVBT8hPpIblLSt ROu10P0wlz5rxx6qjWuNHs5dd/Ns/ X-Google-Smtp-Source: AGHT+IF/2DdPkCN70tDr5478PzxXyOUoTp89QLBFx5j4RTOjD2SNk1fiE9y30CdMJvrSmyvAbMVl0Q== X-Received: by 2002:a17:902:e783:b0:25b:dcbf:43a2 with SMTP id d9443c01a7336-25d2762332amr187793705ad.52.1758032568042; Tue, 16 Sep 2025 07:22:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, Manos Pitsidianakis Subject: [PATCH v2 10/36] target/arm: Use raw_write in cp_reg_reset Date: Tue, 16 Sep 2025 07:22:11 -0700 Message-ID: <20250916142238.664316-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916142238.664316-1-richard.henderson@linaro.org> References: <20250916142238.664316-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758032990308116600 Content-Type: text/plain; charset="utf-8" Reduce the places that know about field types by 1. Reviewed-by: Manos Pitsidianakis Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d0f6fcdfce..48d0f03098 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -192,14 +192,8 @@ static void cp_reg_reset(gpointer key, gpointer value,= gpointer opaque) * This is basically only used for fields in non-core coprocessors * (like the pxa2xx ones). */ - if (!ri->fieldoffset) { - return; - } - - if (cpreg_field_is_64bit(ri)) { - CPREG_FIELD64(&cpu->env, ri) =3D ri->resetvalue; - } else { - CPREG_FIELD32(&cpu->env, ri) =3D ri->resetvalue; + if (ri->fieldoffset) { + raw_write(&cpu->env, ri, ri->resetvalue); } } =20 --=20 2.43.0 From nobody Sun Sep 28 16:37:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758032642; cv=none; d=zohomail.com; s=zohoarc; b=OtcmQudeP5uFNhX8PeZlhSz9ZnnBqJBFBPCkeUsNwt9b6Z2eTpsyYsRn9RV/Q8PiYhsVHUPpDYoELq7jn67yEFO6mR97Dwurn9WLILGdwnc46rx6qHi5Q8AnqyP8ocyWpG4xe5V0V+zRWxlV4WvL6Cx60dQMEx3kGMxWzH7SGcc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758032642; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=BYeHdzgqxopt1Gh2oK2nmvzJnOBU1f7KAls9HRaywqQ=; b=PqOCkHXXwiVpWpJNlb9s0LLNwrfzH9CyJzml5/0fUZ4XO6YVXC7UL/w+0xIGHgF46Lg2IDBPXR6JkBHfNkKYwUWLu9sb/KVIT73LwJrAVFxmWlS4dOV/tlmHtNKW4AnG8V5hStBaon8i4SDZe+uZzxL5wzRP5wZQzZXq89kakrQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758032641912175.01518781499885; Tue, 16 Sep 2025 07:24:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uyWaZ-0005wJ-2u; Tue, 16 Sep 2025 10:23:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uyWaC-0005lP-P2 for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:23:07 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uyWa3-0008JV-UQ for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:22:57 -0400 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-24c8ef94e5dso44815505ad.1 for ; Tue, 16 Sep 2025 07:22:50 -0700 (PDT) Received: from stoup.. ([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2651d2df15esm73459905ad.45.2025.09.16.07.22.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 07:22:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758032569; x=1758637369; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BYeHdzgqxopt1Gh2oK2nmvzJnOBU1f7KAls9HRaywqQ=; b=PWlzF3zqt7VRBpqfd7Pmvyk0prNmZ1potWL3eEe9qmxbiLmKJ2vNqGZqaRdbNQ2xyU wb0yv0gbn0g4kVqTWbneGm5Edl4oBEsm3CugI7atbIUCTE8vE9rcUYw6hELkCeX6b9ef h7TwpaF0VT0s1BAlMOrSAdTLw0dWSsvLe+n8C5K+D7Mc6lmUaoHRqkPW+gxuhxGEMtI0 kivwMaLr7/n28KuzAMqFtxTLmJAlAdJ4Rd81lGsXI2blzgCiJB6qN7+YOtnROJU+wrYw X6v4BQ2hhl+PbuB9x5P6vj2W2us7LDWMeNZXm7TUTy4sZOH6wzb1He3VmgEILt61wZmd dTWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758032569; x=1758637369; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BYeHdzgqxopt1Gh2oK2nmvzJnOBU1f7KAls9HRaywqQ=; b=iZAaknnpcn0NykekgD80DnZtjrNOJ2mNRbA4eCCdcvifnV5LhKT/7MbL/aa/CuK9XZ foipK1IsMSKYidEZks3RKvEpJkHQSorGaOVqBhUe8RPynZT+fR9HZArYHABgEUnnoqxN zVC8hCHrKufjtxuUIA0AU5tCzG7xY/poePzz5Ck/D3RXOKIx+Fw8KXdUYyA0cF4Ym+9p flV02l/sua2+KPE+TfeanTGJIkf4j90YQ0VTQTZxM621oetxlxvS6qrYl4WrN+wiO38X vasqDbhPirMhmYIryg+FwdO4tWoCOEvJ7AotrAlEnhtnMdHb+vnkbO4gei02zkk5epMx lYkA== X-Gm-Message-State: AOJu0YwncG5CrXpgNQ1fLGvPiHnqLx4diCkxZqbh/1NW+My6jut8xgrY 9zcov6Q+jAY/FRs1jZJsPTNUW/aZ0iQqrNeb66XV/aF1zKfJVDbhaAgJ17O6zeY5xsE+A2UcXs9 KiTy+ X-Gm-Gg: ASbGncscpR6tUBX6g0KvbJ9gn4O2lWyzv6ItZ09fpeIZ2nyWZaTf6USBny8KX0/Ox5k PtIZjv9/TGJYWcT338pWTAkAgTRlQ5cPg4X6KaU/hY3r7eDX7Pqnkpm8jGGuhAaJjGW1qh2qpJR 3IHvUMfzp0OB0/BQNQNM55OMdRAJtCxmJ9HpqK2oubj+isdA1FMCx1SqNfWgw3SGyp/WRMX2EQM uKg3hLwEpJ/qBe08lCx95St8vvYCRIjCVCG0VFtVjnEf+a2/GleMx9AZ/YCrVcTwhp4GilR0d5w IM/04vuo4KpmGewDQI0q/mvhhs5MmoieSzQ6ctP2GcpuaxQfHFnXk1tHuFjz01TOUW06Rl9XjxE hacAUOV3DdNKGZ1RmefTLnO3DE3iK X-Google-Smtp-Source: AGHT+IE/n0rkogzIMqt7yinLBP3MltOfxIb+FqpDb1LH5vRquOq/wP5uUqwz/X2Sv7pnSJHiGkzF+w== X-Received: by 2002:a17:903:2b10:b0:266:49eb:45cc with SMTP id d9443c01a7336-267d15efb43mr32448395ad.19.1758032568694; Tue, 16 Sep 2025 07:22:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, Manos Pitsidianakis Subject: [PATCH v2 11/36] target/arm: Rename all ARMCPRegInfo from opaque to ri Date: Tue, 16 Sep 2025 07:22:12 -0700 Message-ID: <20250916142238.664316-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916142238.664316-1-richard.henderson@linaro.org> References: <20250916142238.664316-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758032645550116600 Content-Type: text/plain; charset="utf-8" These pointers are no opaque, they have a specific type. Reviewed-by: Manos Pitsidianakis Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpregs.h | 10 +++++----- target/arm/helper.c | 6 +++--- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index c9506aa6d5..3344a02bd3 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -841,15 +841,15 @@ typedef struct ARMCPRegInfo ARMCPRegInfo; * Access functions for coprocessor registers. These cannot fail and * may not raise exceptions. */ -typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); -typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, +typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *ri); +typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value); /* Access permission check functions for coprocessor registers. */ typedef CPAccessResult CPAccessFn(CPUARMState *env, - const ARMCPRegInfo *opaque, + const ARMCPRegInfo *ri, bool isread); /* Hook function for register reset */ -typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); +typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *ri); =20 #define CP_ANY 0xff =20 @@ -1075,7 +1075,7 @@ void raw_write(CPUARMState *env, const ARMCPRegInfo *= ri, uint64_t value); * CPResetFn that does nothing, for use if no reset is required even * if fieldoffset is non zero. */ -void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); +void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *ri); =20 /* * Return true if this reginfo struct's field in the cpu state struct diff --git a/target/arm/helper.c b/target/arm/helper.c index df9e0c7bca..4ba76c80b1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1073,7 +1073,7 @@ static const ARMCPRegInfo v6k_cp_reginfo[] =3D { .resetvalue =3D 0 }, }; =20 -static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaq= ue) +static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *ri) { ARMCPU *cpu =3D env_archcpu(env); =20 @@ -5426,7 +5426,7 @@ static const ARMCPRegInfo rndr_reginfo[] =3D { .access =3D PL0_R, .readfn =3D rndr_readfn }, }; =20 -static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque, +static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { #ifdef CONFIG_TCG @@ -7884,7 +7884,7 @@ uint64_t arm_cp_read_zero(CPUARMState *env, const ARM= CPRegInfo *ri) return 0; } =20 -void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque) +void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *ri) { /* Helper coprocessor reset function for do-nothing-on-reset registers= */ } --=20 2.43.0 From nobody Sun Sep 28 16:37:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758032749; cv=none; d=zohomail.com; s=zohoarc; b=Jj4ViNqS3m/6GaFHdIfwz0ge6TYdTHcn/bVY7aaDyhKvHO33lUtkdp4DVWFXM4e1cW3QVZamTq67XzvmlNB3LSJj7ix2qL/LSMUZlyNgNsegDBQD/r52S6KywsNHOejxItxxrCAHUAvdLzxirgkL9Q6dFUsMUJ/eWqZUcETHd/Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758032749; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=E7wtwSeAyVxAyxj0iVv+zvWRTdY6KuYaJg6kG2AFAzk=; b=LpXULcB/cnxxchhR1CQwBrV+3hKQ1Ge5woBWDCnYJt6AWdSaNg1+MUsLuGZ9T7Gzod19k7FX6G8JLJgZIaIgdiJf7ya66ewbC4Vm4HFb/RID6h8nTQVcwnJ09ZDqtRytHerbrRGHGn1kgL7TquT2F9UtDKU77xDOSPpL0pKi/tw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758032748969949.3312828365167; Tue, 16 Sep 2025 07:25:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uyWau-0006PN-Ch; Tue, 16 Sep 2025 10:23:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uyWaP-0005q9-Qg for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:23:15 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uyWaI-0008Jm-V2 for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:23:11 -0400 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-24457f581aeso55560315ad.0 for ; Tue, 16 Sep 2025 07:22:50 -0700 (PDT) Received: from stoup.. ([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2651d2df15esm73459905ad.45.2025.09.16.07.22.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 07:22:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758032570; x=1758637370; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=E7wtwSeAyVxAyxj0iVv+zvWRTdY6KuYaJg6kG2AFAzk=; b=NMH3JlZpOMFCDSsdTOVQg8mrKJ10xaCPwptCa/oEVWyxKCpfJTyNy0Ad20edfl4czr URy1aX2RLBQPuP0S2+Olh/ba2woqhfdDw7KZdv9j6KC3nvzitXNV+xKxg4U3qzqw7eVo eObjjjq0Jl2QW5QrlxAhuAuhLLQXQpF2OsmR6kIL0gZsuq1HBGBQLHCery0oqt8N2rFo 00fuQAxXTnF/JObfVivSyFnHNsQY2u6I9LCMc0nyhJ/hkH5jHpGj7BR6SRIojHHq0CrY dwNMs11JpVGT4rQ5kRh2IoLSub3poSuGIlheSbMPc7YUCBXTIqrIenlzkNpLVRH96Nrh f4fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758032570; x=1758637370; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=E7wtwSeAyVxAyxj0iVv+zvWRTdY6KuYaJg6kG2AFAzk=; b=LDvuVZK04nUzdDrpBhm72pPKZmYjrHwpBxa5JRBjzNiKafQecG6xRWE1x0ZBb4Lxy+ G6TL91M2nBXK847u/g0cpVaBl/KT1TCUTiFRUcf/Tmh0PY6Lf3zQ6O7lXiYTNtluX7DS 9QZRJEilxvoCUJqve/pbhV1KMV9qV0350Z9Q8dNaycVxrOKNo2YN6f2v8qRFrpKeu04h ELOdxgSRTyJSJiw+uUYWWB2nfx7o3fblAteWPtOhfG85XYVVRx4vXHcqg9anzkuF2LDG tK+NgxPtCEaRsijYFP5YW5m083uldvLvq2vWpB3C5sds2FuwTlg+tAiQxMeq9Lq+rvZK ezTw== X-Gm-Message-State: AOJu0YzuktMbzXB5Udxwh+AGreQQaAv4Zk0zIH/PW+e2qsG1Atjau9hH eMix+sfKPumgbOIcj2xtc/pgMqlCX5O0gCUoG0EDHpr2Sm3y1S9TiOy66onl0OqVcnpxuCih4be aPWyv X-Gm-Gg: ASbGncsBpTr1VZ+3sM0o0WCBnUXOGpdme2tUOwx2gTz6rjcxHZrai0BZh0bmWzytzGv rl4/9j918HNb5I5CRocXJb1ggjuV9IX6lgfInS1/1mVhtXqRTxm3YERRTX5G9mxIURA7hleFMOU ckagWlfU2c8coDJBHrqNu2ouEPzrxlYqyHV3Z8bwoG2+f0q7Nd92eaSMWhQwBJN+Feg/VkHjD5b bDHNy9wcKv6SCrSjxt7ycCi6c8xAJcjSMp7slXLxaor6dz9A8fV4f8DZo1QVH3alX+SlfO18pHQ TriHamJW9Kzs2ib20q1bpZnnay90ccuXP+z/sttBpma8O/phJ6aYNonQ0b6JIXcl/rgKqk52tn9 V8ohqhYYvymuChQAwr2zx+sdFtCRWnNqzfM7n/Jo= X-Google-Smtp-Source: AGHT+IHlUQdVirHYnlXUBJTD6+fcQ4MnjOs0iMqeNKU+4UIsiEzUhUmfnCxvbsiawthsc7RzdNupvw== X-Received: by 2002:a17:902:f68b:b0:264:ede2:683d with SMTP id d9443c01a7336-264ede26b0bmr117365955ad.56.1758032569582; Tue, 16 Sep 2025 07:22:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, Manos Pitsidianakis Subject: [PATCH v2 12/36] target/arm: Drop define_one_arm_cp_reg_with_opaque Date: Tue, 16 Sep 2025 07:22:13 -0700 Message-ID: <20250916142238.664316-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916142238.664316-1-richard.henderson@linaro.org> References: <20250916142238.664316-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758032751308116600 Content-Type: text/plain; charset="utf-8" The last use of this interface was removed in 603bc048a27f ("hw/arm: Remove pxa2xx_pic"). As the comment in gicv3 stated, keeping pointer references to cpregs has SMP issues, so avoid future temptation by removing the interface. Reviewed-by: Manos Pitsidianakis Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpregs.h | 32 ++++++++------------------------ hw/intc/arm_gicv3_cpuif.c | 10 +--------- target/arm/helper.c | 29 +++++++++++------------------ 3 files changed, 20 insertions(+), 51 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 3344a02bd3..b610716c24 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -906,11 +906,7 @@ struct ARMCPRegInfo { */ uint32_t nv2_redirect_offset; =20 - /* - * The opaque pointer passed to define_arm_cp_regs_with_opaque() when - * this register was defined: can be used to hand data through to the - * register read/write functions, since they are passed the ARMCPRegIn= fo*. - */ + /* This is used only by VHE. */ void *opaque; /* * Value of this register, if it is ARM_CP_CONST. Otherwise, if @@ -1004,27 +1000,15 @@ struct ARMCPRegInfo { #define CPREG_FIELD64(env, ri) \ (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) =20 -void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, const ARMCPRegInfo *re= g, - void *opaque); +void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs); +void define_arm_cp_regs_len(ARMCPU *cpu, const ARMCPRegInfo *regs, size_t = len); =20 -static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *= regs) -{ - define_one_arm_cp_reg_with_opaque(cpu, regs, NULL); -} - -void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *r= egs, - void *opaque, size_t len); - -#define define_arm_cp_regs_with_opaque(CPU, REGS, OPAQUE) \ - do { \ - QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) =3D=3D 0); = \ - define_arm_cp_regs_with_opaque_len(CPU, REGS, OPAQUE, \ - ARRAY_SIZE(REGS)); \ +#define define_arm_cp_regs(CPU, REGS) \ + do { \ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) =3D=3D 0); \ + define_arm_cp_regs_len(CPU, REGS, ARRAY_SIZE(REGS)); \ } while (0) =20 -#define define_arm_cp_regs(CPU, REGS) \ - define_arm_cp_regs_with_opaque(CPU, REGS, NULL) - const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encode= d_cp); =20 /* @@ -1143,7 +1127,7 @@ static inline bool arm_cpreg_traps_in_nv(const ARMCPR= egInfo *ri) * means that the right set of registers is exactly those where * the opc1 field is 4 or 5. (You can see this also in the assert * we do that the opc1 field and the permissions mask line up in - * define_one_arm_cp_reg_with_opaque().) + * define_one_arm_cp_reg().) * Checking the opc1 field is easier for us and avoids the problem * that we do not consistently use the right architectural names * for all sysregs, since we treat the name field as largely for debug. diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 4b4cf09157..72e91f971a 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -3037,15 +3037,7 @@ void gicv3_init_cpuif(GICv3State *s) * cpu->gic_pribits */ =20 - /* Note that we can't just use the GICv3CPUState as an opaque poin= ter - * in define_arm_cp_regs_with_opaque(), because when we're called = back - * it might be with code translated by CPU 0 but run by CPU 1, in - * which case we'd get the wrong value. - * So instead we define the regs with no ri->opaque info, and - * get back to the GICv3CPUState from the CPUARMState. - * - * These CP regs callbacks can be called from either TCG or HVF co= de. - */ + /* These CP regs callbacks can be called from either TCG or HVF. */ define_arm_cp_regs(cpu, gicv3_cpuif_reginfo); =20 /* diff --git a/target/arm/helper.c b/target/arm/helper.c index 4ba76c80b1..5bc8fb23cc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7410,12 +7410,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) } =20 /* - * Private utility function for define_one_arm_cp_reg_with_opaque(): + * Private utility function for define_one_arm_cp_reg(): * add a single reginfo struct to the hash table. */ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, - void *opaque, CPState state, - CPSecureState secstate, + CPState state, CPSecureState secstate, int crm, int opc1, int opc2, const char *name) { @@ -7503,9 +7502,6 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, r2->opc2 =3D opc2; r2->state =3D state; r2->secure =3D secstate; - if (opaque) { - r2->opaque =3D opaque; - } =20 if (make_const) { /* This should not have been a very special register to begin. */ @@ -7610,8 +7606,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, } =20 =20 -void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, - const ARMCPRegInfo *r, void *opaque) +void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r) { /* * Define implementations of coprocessor registers. @@ -7770,7 +7765,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, if (nxs_ri.fgt) { nxs_ri.fgt |=3D R_FGT_NXS_MASK; } - add_cpreg_to_hashtable(cpu, &nxs_ri, opaque, state, + add_cpreg_to_hashtable(cpu, &nxs_ri, state, ARM_CP_SECSTATE_NS, crm, opc1, opc2, name); } @@ -7784,17 +7779,17 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, switch (r->secure) { case ARM_CP_SECSTATE_S: case ARM_CP_SECSTATE_NS: - add_cpreg_to_hashtable(cpu, r, opaque, state, + add_cpreg_to_hashtable(cpu, r, state, r->secure, crm, opc1, o= pc2, r->name); break; case ARM_CP_SECSTATE_BOTH: name =3D g_strdup_printf("%s_S", r->name); - add_cpreg_to_hashtable(cpu, r, opaque, state, + add_cpreg_to_hashtable(cpu, r, state, ARM_CP_SECSTATE_S, crm, opc1, opc2, name); g_free(name); - add_cpreg_to_hashtable(cpu, r, opaque, state, + add_cpreg_to_hashtable(cpu, r, state, ARM_CP_SECSTATE_NS, crm, opc1, opc2, r->nam= e); break; @@ -7806,7 +7801,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, * AArch64 registers get mapped to non-secure inst= ance * of AArch32 */ - add_cpreg_to_hashtable(cpu, r, opaque, state, + add_cpreg_to_hashtable(cpu, r, state, ARM_CP_SECSTATE_NS, crm, opc1, opc2, r->name); } @@ -7817,12 +7812,10 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, } =20 /* Define a whole list of registers */ -void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *r= egs, - void *opaque, size_t len) +void define_arm_cp_regs_len(ARMCPU *cpu, const ARMCPRegInfo *regs, size_t = len) { - size_t i; - for (i =3D 0; i < len; ++i) { - define_one_arm_cp_reg_with_opaque(cpu, regs + i, opaque); + for (size_t i =3D 0; i < len; ++i) { + define_one_arm_cp_reg(cpu, regs + i); } } =20 --=20 2.43.0 From nobody Sun Sep 28 16:37:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758032744; cv=none; d=zohomail.com; s=zohoarc; b=VBTM78zqDes2V7sGcLHx7ZsZlghbNehQQkmqWiFSTPpRc9ke4K12Z4XLPFEfIZCr62Y5vgwE7T93RoxReA3OYqjDoHswXMg580dPDHRtMKY5D86BKklw2zis6V3b49l4msG0UM5EnFWXwxuLbLkTtuz61WKcPtuuJi8s3MsOgfg= ARC-Message-Signature: i=1; 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Tue, 16 Sep 2025 07:22:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, Manos Pitsidianakis Subject: [PATCH v2 13/36] target/arm: Restrict the scope of CPREG_FIELD32, CPREG_FIELD64 Date: Tue, 16 Sep 2025 07:22:14 -0700 Message-ID: <20250916142238.664316-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916142238.664316-1-richard.henderson@linaro.org> References: <20250916142238.664316-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758032747009116600 Content-Type: text/plain; charset="utf-8" Reviewed-by: Manos Pitsidianakis Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpregs.h | 9 --------- target/arm/helper.c | 12 ++++++++++++ 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index b610716c24..812fb1340a 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -991,15 +991,6 @@ struct ARMCPRegInfo { CPAccessFn *orig_accessfn; }; =20 -/* - * Macros which are lvalues for the field in CPUARMState for the - * ARMCPRegInfo *ri. - */ -#define CPREG_FIELD32(env, ri) \ - (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) -#define CPREG_FIELD64(env, ri) \ - (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) - void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs); void define_arm_cp_regs_len(ARMCPU *cpu, const ARMCPRegInfo *regs, size_t = len); =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index 5bc8fb23cc..b310f52724 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -51,6 +51,15 @@ int compare_u64(const void *a, const void *b) return 0; } =20 +/* + * Macros which are lvalues for the field in CPUARMState for the + * ARMCPRegInfo *ri. + */ +#define CPREG_FIELD32(env, ri) \ + (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) +#define CPREG_FIELD64(env, ri) \ + (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) + uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) { assert(ri->fieldoffset); @@ -71,6 +80,9 @@ void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, = uint64_t value) } } =20 +#undef CPREG_FIELD32 +#undef CPREG_FIELD64 + static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri) { return (char *)env + ri->fieldoffset; --=20 2.43.0 From nobody Sun Sep 28 16:37:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758032810; 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Reviewed-by: Manos Pitsidianakis Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpregs.h | 10 ++++++---- target/arm/gdbstub.c | 7 +++++-- target/arm/helper.c | 18 +++++++++++++----- 3 files changed, 24 insertions(+), 11 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 812fb1340a..b6c8eff0dd 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -22,6 +22,7 @@ #define TARGET_ARM_CPREGS_H =20 #include "hw/registerfields.h" +#include "exec/memop.h" #include "target/arm/kvm-consts.h" #include "cpu.h" =20 @@ -1053,12 +1054,13 @@ void raw_write(CPUARMState *env, const ARMCPRegInfo= *ri, uint64_t value); void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *ri); =20 /* - * Return true if this reginfo struct's field in the cpu state struct - * is 64 bits wide. + * Return MO_32 if the field in CPUARMState is uint32_t or + * MO_64 if the field in CPUARMState is uint64_t. */ -static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) +static inline MemOp cpreg_field_type(const ARMCPRegInfo *ri) { - return (ri->state =3D=3D ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BI= T); + return (ri->state =3D=3D ARM_CP_STATE_AA64 || (ri->type & ARM_CP_64BIT) + ? MO_64 : MO_32); } =20 static inline bool cp_access_ok(int current_el, diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index ce4497ad7c..e2fc389170 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -247,10 +247,13 @@ static int arm_gdb_get_sysreg(CPUState *cs, GByteArra= y *buf, int reg) key =3D cpu->dyn_sysreg_feature.data.cpregs.keys[reg]; ri =3D get_arm_cp_reginfo(cpu->cp_regs, key); if (ri) { - if (cpreg_field_is_64bit(ri)) { + switch (cpreg_field_type(ri)) { + case MO_64: return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri)); - } else { + case MO_32: return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri)); + default: + g_assert_not_reached(); } } return 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index b310f52724..b7c483b0d9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -63,20 +63,28 @@ int compare_u64(const void *a, const void *b) uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) { assert(ri->fieldoffset); - if (cpreg_field_is_64bit(ri)) { + switch (cpreg_field_type(ri)) { + case MO_64: return CPREG_FIELD64(env, ri); - } else { + case MO_32: return CPREG_FIELD32(env, ri); + default: + g_assert_not_reached(); } } =20 void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { assert(ri->fieldoffset); - if (cpreg_field_is_64bit(ri)) { + switch (cpreg_field_type(ri)) { + case MO_64: CPREG_FIELD64(env, ri) =3D value; - } else { + break; + case MO_32: CPREG_FIELD32(env, ri) =3D value; + break; + default: + g_assert_not_reached(); } } =20 @@ -2754,7 +2762,7 @@ static void vmsa_ttbr_write(CPUARMState *env, const A= RMCPRegInfo *ri, uint64_t value) { /* If the ASID changes (with a 64-bit write), we must flush the TLB. = */ - if (cpreg_field_is_64bit(ri) && + if (cpreg_field_type(ri) =3D=3D MO_64 && extract64(raw_read(env, ri) ^ value, 48, 16) !=3D 0) { ARMCPU *cpu =3D env_archcpu(env); tlb_flush(CPU(cpu)); --=20 2.43.0 From nobody Sun Sep 28 16:37:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758033323; cv=none; d=zohomail.com; s=zohoarc; b=kuIRP05lA1iQ7YBooNVmQzNI3dX8VrAWzG3MGEJ64KNLW4v9j3njpuFJTVkeX0Qq97paZRuDlRWxHcPrhhVvrS4jXYlees/h0YNSeCTeOSfxqfVkeyry9OqZ3D2owaJIburnjPAb4xPHoNLb4ALjnA26MJ3BkKXh80gUwCfifZI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758033323; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=977BcuDeql0kPwyP7xy6f+rDemPgbKM+wEyJIH6/QAM=; b=G2QXLj6W4jMM4LRjNfF74IuM+g2c8Xvv3U0fugMuPKwOgAzFu8meIJg7ydMf0A4ysuLqJyMVw0mI4EhIPVhE7xnU4VaW242c9Oleeqt3TW8dJ/jC4jZlgZSjlQA8x+u5yikIk4QJzBVvrL5mQdkV0azQSmH9t29+tv6S6k5gRbI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175803332331432.559400960728226; Tue, 16 Sep 2025 07:35:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uyWdr-00036n-D5; Tue, 16 Sep 2025 10:26:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uyWaq-0006Kd-FJ for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:23:40 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uyWaW-0008KN-Di for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:23:40 -0400 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-266a0e83662so16333505ad.0 for ; Tue, 16 Sep 2025 07:22:52 -0700 (PDT) Received: from stoup.. ([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2651d2df15esm73459905ad.45.2025.09.16.07.22.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 07:22:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758032572; x=1758637372; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=977BcuDeql0kPwyP7xy6f+rDemPgbKM+wEyJIH6/QAM=; b=bjh2M2KbErnSmRH9mjG6+9cyI1XosvBCOoyNwVC82rtMukTyO1CSvTtvapPdIpy7lu ZJ1YXmwHwZUKfQdr86z3Q6QV59JJb7W6YoPNxoh0u9oN4I+iFRumEsxP4LLdRNwPXtTJ zDX5YejJHZbCRKxh+yc0GM2BKznG2xWDi8znoMNY/+Nxdzozcw8aNeF3lWK8YAwWSrgB vrByH+6pRUI26W0IMABi3NMvxZWavBU5rRt9QeiZiLw4oU4FAhbkUu3pQ1GtWpralKKP Zdp9XN5c9eDSZe/aAz4kEXLuXTiWRshQx1Px4BssjQOxg+249Mgtg/hQkhsASOZ/20oK Dp6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758032572; x=1758637372; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=977BcuDeql0kPwyP7xy6f+rDemPgbKM+wEyJIH6/QAM=; b=n3W/GdrHrrt84rrYOrOfMBbO37of2oZUMx+5XNMGXFwKHST58TyxK1odPMJGEjpc0t 8xQiO5nnJ3WPKio8koDmSKv4vC7HmJzNEhJTZGXAMGE5jSFWLTnEmo6ABXoyVyuI30Wj 2GC7riqqhLkz6NdoMkpgJGAtrMjfu1vAlZpcO0qDh1r0GM39vXhO1VMytjXdD0P38BKl t2X7WhJGR7pZxIZ0iTvtU06X1tzVt2ZmLaaNPRv50pvKSwUz52RJ2bgx/hBwbKaBqH4d 3gEVnXwp6uK4ii43kN3ZwBu7M91F3lNWjKxUM8/XRYBGWE1gxxdwp9A88XRior9iyP3b 53Jw== X-Gm-Message-State: AOJu0YwDRLWXb9Ed/Lm2otu3Z2ViXOfzH1g2OkBKcwWW4oVRbe4Uk8vi phy4HJqTm2hKK6sppZRSXEZiVkAyT7lnBm0FA8N+fXZpnunXgmpu+bAaeTGvHFlDEw59PN4sJvK I8ySB X-Gm-Gg: ASbGncvjKyeY0ytumqRCUkRxT1u/Y1YsiL1Os3Ca1yyxcxnU7ZbgNIVr5GpumQ6Fu87 5pCLyOGdHv6P38os5ula8hwy/cvweeeP+jM8uh7wISQJBjxARhKmB3XiDP5LmaEERt/YQS0LMc8 IlJX+2Z6xydllSh9Uo/4CTtC5GwtAoJp2MIEYUcdvpaVx5o5ET1PcQ8nSxw6IdI0mez6sOmvv/B bQEPmEf5GSSrufZ5Gu8hcq9Jv4Qp9fBCB3yk/odYq+8cAQCX+RZM0Ki/6wAknddjZ+lPJbbqlVz DXPnN8XY5gNRfLM71TQ0xFdXiHdXzlZ8upMtin7YrfjV3sIRrXrOscwkSAHXGw7dep9kzb50yOY rw+XKgaOJzUVNzHWNsCM9/ai+cHer X-Google-Smtp-Source: AGHT+IG2iXOitsj0rIiXECUvXk5tueRmn0QeAqPPunkUAzstgAMO/bL/1uU/1fB8l8EmmejQ3taH3Q== X-Received: by 2002:a17:902:e849:b0:267:d4c8:c50 with SMTP id d9443c01a7336-267d4c81797mr30152665ad.27.1758032571765; Tue, 16 Sep 2025 07:22:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, Manos Pitsidianakis Subject: [PATCH v2 15/36] target/arm: Add CP_REG_AA32_64BIT_{SHIFT,MASK} Date: Tue, 16 Sep 2025 07:22:16 -0700 Message-ID: <20250916142238.664316-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916142238.664316-1-richard.henderson@linaro.org> References: <20250916142238.664316-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758033325102116600 Content-Type: text/plain; charset="utf-8" Give a name to the bit we're already using. Reviewed-by: Manos Pitsidianakis Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpregs.h | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index b6c8eff0dd..3dc4c9927b 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -178,9 +178,14 @@ enum { #define CP_REG_NS_SHIFT 29 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) =20 +/* Distinguish 32-bit and 64-bit views of AArch32 system registers. */ +#define CP_REG_AA32_64BIT_SHIFT 15 +#define CP_REG_AA32_64BIT_MASK (1 << CP_REG_AA32_64BIT_SHIFT) + #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ - ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ - ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) + (((ns) << CP_REG_NS_SHIFT) | \ + ((is64) << CP_REG_AA32_64BIT_SHIFT) | \ + ((cp) << 16) | ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) =20 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ (CP_REG_AA64_MASK | \ @@ -202,7 +207,7 @@ static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) cpregid |=3D CP_REG_AA64_MASK; } else { if ((kvmid & CP_REG_SIZE_MASK) =3D=3D CP_REG_SIZE_U64) { - cpregid |=3D (1 << 15); + cpregid |=3D CP_REG_AA32_64BIT_MASK; } =20 /* @@ -226,8 +231,8 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) kvmid =3D cpregid & ~CP_REG_AA64_MASK; kvmid |=3D CP_REG_SIZE_U64 | CP_REG_ARM64; } else { - kvmid =3D cpregid & ~(1 << 15); - if (cpregid & (1 << 15)) { + kvmid =3D cpregid & ~CP_REG_AA32_64BIT_MASK; + if (cpregid & CP_REG_AA32_64BIT_MASK) { kvmid |=3D CP_REG_SIZE_U64 | CP_REG_ARM; } else { kvmid |=3D CP_REG_SIZE_U32 | CP_REG_ARM; --=20 2.43.0 From nobody Sun Sep 28 16:37:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758032813; cv=none; d=zohomail.com; s=zohoarc; b=d3cPeoiXCRQfYIvAFWDFgZYk0pEnNhCjN/AjE3JNUY5sOtrVx0VIRAuYjb9L4d07Jy0+gPOYPHBRRwCM1gVyN9xY4qFSbDMqlu0M1oItRzyjLmGHnCCH57AeznzX+3/973lZY8snL2HJC6cmukDHcVNoMX2YXwKSWTZ9jy1rqRs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758032813; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=j4ZSa8lN9EtAmbPaq+Y1Gn9/4VVymrm3E6UBOKY/KQw=; b=BOvDFWiTrtGKxZT4N4I/45iy1g/65Agrd1b2uvUmjFyuYY0q5QzBaC3ksKk8y0usdzE//YGPwT3mGZaluhElWyUQFRSsALCOul1QzSEaPMoPj2bSZh8yvnkXQORzi1EFDi4Xi6ZdsDwzDX5a1jgj1/PBB0pbq+ii3VoYb99L0as= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758032812995153.67381130779586; Tue, 16 Sep 2025 07:26:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uyWdB-0001sX-6h; Tue, 16 Sep 2025 10:26:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uyWan-0006BO-AO for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:23:37 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uyWaU-0008Kd-QH for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:23:31 -0400 Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-2445806e03cso61704735ad.1 for ; Tue, 16 Sep 2025 07:22:53 -0700 (PDT) Received: from stoup.. ([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2651d2df15esm73459905ad.45.2025.09.16.07.22.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 07:22:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758032572; x=1758637372; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=j4ZSa8lN9EtAmbPaq+Y1Gn9/4VVymrm3E6UBOKY/KQw=; b=zmtHak7ZVnd9WepkYPXtH3gVcWy7i4NqseuMEetP8h/cJegDuseGYGjAXaGIsZvE8G DLwCUMVpLjjaerx5xKxQdY++YqeWvkht/MdxUpEnLijIfylliwcGcPyWXVJZevuQCkaM l/QESlC49q9gwP8fMnRzZSfbIJtTB6HmV/xQu0+9q5RBXkGnAEwaYGUN0jVQi90a/6kZ L4SLwMgSeG88f/E1DYcV4RrtOHo9KVXQoJQS4raVdQ2vX7+dKx5jkNTREl3Nz3dKZ4Ty HGHT/rk4NxZDXb5Krm3lWi7KYNM/An8bh6+kupM3X1ihwKTw6yhtFjoJArr83WXD9B/8 629A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758032572; x=1758637372; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=j4ZSa8lN9EtAmbPaq+Y1Gn9/4VVymrm3E6UBOKY/KQw=; b=Ni5ji42a+XUmOf6OSmSusmI1kNlHiYO1Pmj64d/AF0EpSCdZpwtbAABuGcaHEKKeEq vym/2PZKG6xbdQSIZ7Y/L/BmU6KvzqxHP8GMwuML314N8prYd5MqhNa/iqilGegfBpPQ DbPvbBxzqV7hKZiZuT0un1b4OeltEq2HL5q7GEt/cX+Nnpp/Zlb2rL84rQ3U5CX2BcBV EQMnMeICainrSSEsKXJPqoQk8WhWtsBfgfEWFxfDYIdJf+RnrtyjuijvXP6ma65eLDV0 GXL+5haVVmNGN5fhPzpk+nIeJifVQXNwEDc9Q1EHWRKfapuWa5WLhBFnP6Ax6sgwVMAd PPxw== X-Gm-Message-State: AOJu0YySDNnLhmsPxuH7pJqp/QWUekhI/PtOpRZvv+rQonwfRV36Yq7X FGo476rDm2VzC/H5FTVxFn1AhvpWxF7IBOi/rlc3f12LTriGzfIw/3sUUg/qniDAVkl6AixVbF+ 6wZHR X-Gm-Gg: ASbGncumKE+/V7mSDOGQT+1453vtvQvfpsEw/fTiDlZmBFLeDVdhA3rWa7UIuQOtChD PqCzZXHh8Ar5P8fKz04nIunEIH/sIVqeaKpe470dXXutgwdolOHY1Px/Nm04CJuLMUY8oRXASiY 0FFaHXEWyN1HAomNEOHHGUmL8BtLi8jHxR5vnScYuR2sVWcEPV2V+e/Q/9hNe+dXUkC5/Tn8h+c JByFfkXv9zn0VkVH27O+g3Nv2K6G//y1NS5j1papEVF0IUJPwV5U0S4gm+rqen/yjj7F0g5vs6G uyQLALi+IxSeeT1LJNtlXA9Xjnhjpf+a/RiJ4eMRurQnJcUMC9Ef3/oIOS5PvMe1IWaMWEV8J28 G8SouOw4RXXWLv3sYz1BrNyz8cgSE X-Google-Smtp-Source: AGHT+IHZJn4+KP+mPBQ0Yw8XHb9RODBNWjD9hgnnpRjjVATbNrYu825GhBWH6q1IehLr7oY3aXaidA== X-Received: by 2002:a17:902:cf12:b0:24c:da3b:7379 with SMTP id d9443c01a7336-25d248c9d8cmr208336755ad.16.1758032572585; Tue, 16 Sep 2025 07:22:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, Manos Pitsidianakis Subject: [PATCH v2 16/36] target/arm: Rename CP_REG_AA32_NS_{SHIFT,MASK} Date: Tue, 16 Sep 2025 07:22:17 -0700 Message-ID: <20250916142238.664316-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916142238.664316-1-richard.henderson@linaro.org> References: <20250916142238.664316-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758032813829116600 Content-Type: text/plain; charset="utf-8" Rename from CP_REG_NS_* to emphasize this is specific to AArch32. Reviewed-by: Manos Pitsidianakis Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpregs.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 3dc4c9927b..7ebe404163 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -175,15 +175,15 @@ enum { * add a bit to distinguish between secure and non-secure cpregs in the * hashtable. */ -#define CP_REG_NS_SHIFT 29 -#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) +#define CP_REG_AA32_NS_SHIFT 29 +#define CP_REG_AA32_NS_MASK (1 << CP_REG_AA32_NS_SHIFT) =20 /* Distinguish 32-bit and 64-bit views of AArch32 system registers. */ #define CP_REG_AA32_64BIT_SHIFT 15 #define CP_REG_AA32_64BIT_MASK (1 << CP_REG_AA32_64BIT_SHIFT) =20 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ - (((ns) << CP_REG_NS_SHIFT) | \ + (((ns) << CP_REG_AA32_NS_SHIFT) | \ ((is64) << CP_REG_AA32_64BIT_SHIFT) | \ ((cp) << 16) | ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) =20 @@ -214,7 +214,7 @@ static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) * KVM is always non-secure so add the NS flag on AArch32 register * entries. */ - cpregid |=3D 1 << CP_REG_NS_SHIFT; + cpregid |=3D CP_REG_AA32_NS_MASK; } return cpregid; } --=20 2.43.0 From nobody Sun Sep 28 16:37:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758033062; cv=none; d=zohomail.com; s=zohoarc; b=jTmKV2kZyb5S71HQdWCYlPvKfxHTFXNipOkPRgRsYSD/r5w/QL2ugsSO1kIqz1jTVUzjl8IodL9GPxFyiQl6DQMJMxfRPpUAvLsihUsY+ruGCV0scr3T0/Wftwv58v7ARhfbJJhMum7YwGeFhSbzh4gQ83+er4j9x6p0gQw93aI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758033062; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=5WNm+peGJ2zUSPWUGzDEpnW/8pjrsxmYerIn3jmpQec=; b=CNjmLvDO9k/bkvzKOmUqjxHkw34fMbit/IAesAGfeq/6nCDi+fOGMO55D4xYIQJp+d69EB7TtODe15Reg8GZKhVmAwt/1g9onDjZG4q598PHgcx6mM/HvVrYiKAh6iQsQ5UDKqYgWdAURpyuMpRC+BniyeglBKgFt7/kccpjQ4w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758033062757852.5484299199211; Tue, 16 Sep 2025 07:31:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uyWcz-0000xu-2c; Tue, 16 Sep 2025 10:25:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uyWac-000618-W6 for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:23:27 -0400 Received: from mail-pg1-x531.google.com ([2607:f8b0:4864:20::531]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uyWaT-0008Kk-RA for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:23:26 -0400 Received: by mail-pg1-x531.google.com with SMTP id 41be03b00d2f7-b4d1e7d5036so3629302a12.1 for ; Tue, 16 Sep 2025 07:22:54 -0700 (PDT) Received: from stoup.. ([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2651d2df15esm73459905ad.45.2025.09.16.07.22.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 07:22:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758032573; x=1758637373; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5WNm+peGJ2zUSPWUGzDEpnW/8pjrsxmYerIn3jmpQec=; b=ISDnKVuCGLEbKdUqbw2oeMnRl4ZZMf5+WNohibxD53yzGhkg8nI1r+ibQCOpX/k9xi 2Niy9kl6hZawwxqNI8SSO8orn6KQq31jmuxnQl6GZXa04uqogcSpDQTuK/IN9812anEn TK2ZugVb0V88L+Fk6GSn0tjWii7uW7DkjxahYiOYJ7iRDd1Tw2207P4fza8rxlFrxke3 zvktsElc12cYXS6G65plvlVbosD8qPiv3iR/jsmrqttifZ4UHEO9n2SL5oU8Eak5fDAx hDRZ9xlxu2NNKau3aPtZABfdcvThH0RqgAOKFVd1zLz0cLbxDpAZjk8TjtV/ARNSrBXO kKbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758032573; x=1758637373; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5WNm+peGJ2zUSPWUGzDEpnW/8pjrsxmYerIn3jmpQec=; b=fRQE0/LQpwJ3bijI1OBG/dG/KKk/gBh+cCPYDkGs6iiTKHGD29Kg2U8/PpkD3xRodO ERwzzMM2S1s901wFy5YI6BP3OLfA0nlTZPDA3Q4p89TZ72sgtpaTX6372pK1mwJXIEfk mxFT0mmQPogwhKqBXgaSG2209oWBUvEne4NQxuFa4OYLgs2lOb/of/MdjSPjsm2+IeR1 cOaXFNI8AdOa0aNxqFQkk7OWmnL30BEiNnfow74zyQnNGrFRe9wNRuX0gkkaBZ9yeQLy XLc2Q0TMV26rYjKgIoH71aVIUXygi4AnMgoItRv8PfuRlTrmojb980NDJiHr1LPhuJA0 hxXQ== X-Gm-Message-State: AOJu0Ywg9OQtkjK70QiWNzN/i53ek/zZotZcB/OWhy1jpwVgTV+zF4oM ebVeQvp29wQZeZpoifP1KD6eoguKIFTRHX3SBGgDkkUPlif00WXkGLkG5gWOBdTySjy1fUOBjnk kzBe8 X-Gm-Gg: ASbGncvhAjIMIyHxaHH2l/Lqhs6M+ay9f/RzSm9ZcPfeGB0edoyTHiQRN2f06LsHYii QnfgF7UijwqD7mCfT5WukTmdeNB5+kITlbr1mzuO4DwAtV+o/26eQuUZP0kznE3GItm54URjSr7 mIq0NSDJd0qkcW3LndlBBUb4krE0kEhGYOIDdKqroechnh8uXsaOgRuJB5tWfxg2GOU662rBmR9 vTWqo7N+XUs69NmkzkRs2a07Elq2Mc9AvSS7TK18bmHXbij4EhlK1rS/Djx4kIGJGf+OWDmeAep q+OdfLVC2xlmLfNiNZu23oh6vvAVDvFSCGzX09jv4h9sQqTFip6KADQ2WDmH/8ZMwtZtci/eU/e S0TH1voYFao/debTzyGwMyNX06SH/ X-Google-Smtp-Source: AGHT+IF0PNhtt1zGo8dj/E1sITwfcw6yGZWUjoOyDjGhs5mlvkinOMwL0GlUVAwRFM5ap/0bXCdEjQ== X-Received: by 2002:a17:902:ef47:b0:265:c476:9a53 with SMTP id d9443c01a7336-265c4769c71mr90990815ad.41.1758032573227; Tue, 16 Sep 2025 07:22:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v2 17/36] target/arm: Convert init_cpreg_list to g_hash_table_foreach Date: Tue, 16 Sep 2025 07:22:18 -0700 Message-ID: <20250916142238.664316-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916142238.664316-1-richard.henderson@linaro.org> References: <20250916142238.664316-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758033063613116600 Content-Type: text/plain; charset="utf-8" Adjust count_cpreg and add_cpreg_to_list to be used with g_hash_table_foreach instead of g_list_foreach. In this way we have the ARMCPRegInfo pointer directly rather than having to look it up from the key. Delay the sorting of the cpreg_indexes until after add_cpreg_to_list. This allows us to sort the data that we actually care about, the kvm id, as computed within add_cpreg_to_list, instead of having to repeatedly compute the kvm id within cpreg_key_compare. Signed-off-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/helper.c | 54 ++++++++++++++++++--------------------------- 1 file changed, 21 insertions(+), 33 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index b7c483b0d9..cc924adbc7 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -229,11 +229,11 @@ bool write_list_to_cpustate(ARMCPU *cpu) return ok; } =20 -static void add_cpreg_to_list(gpointer key, gpointer opaque) +static void add_cpreg_to_list(gpointer key, gpointer value, gpointer opaqu= e) { ARMCPU *cpu =3D opaque; uint32_t regidx =3D (uintptr_t)key; - const ARMCPRegInfo *ri =3D get_arm_cp_reginfo(cpu->cp_regs, regidx); + const ARMCPRegInfo *ri =3D value; =20 if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) { cpu->cpreg_indexes[cpu->cpreg_array_len] =3D cpreg_to_kvm_id(regid= x); @@ -242,61 +242,49 @@ static void add_cpreg_to_list(gpointer key, gpointer = opaque) } } =20 -static void count_cpreg(gpointer key, gpointer opaque) +static void count_cpreg(gpointer key, gpointer value, gpointer opaque) { ARMCPU *cpu =3D opaque; - const ARMCPRegInfo *ri; - - ri =3D g_hash_table_lookup(cpu->cp_regs, key); + const ARMCPRegInfo *ri =3D value; =20 if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) { cpu->cpreg_array_len++; } } =20 -static gint cpreg_key_compare(gconstpointer a, gconstpointer b, gpointer d) -{ - uint64_t aidx =3D cpreg_to_kvm_id((uintptr_t)a); - uint64_t bidx =3D cpreg_to_kvm_id((uintptr_t)b); - - if (aidx > bidx) { - return 1; - } - if (aidx < bidx) { - return -1; - } - return 0; -} - void init_cpreg_list(ARMCPU *cpu) { /* * Initialise the cpreg_tuples[] array based on the cp_regs hash. * Note that we require cpreg_tuples[] to be sorted by key ID. */ - GList *keys; int arraylen; =20 - keys =3D g_hash_table_get_keys(cpu->cp_regs); - keys =3D g_list_sort_with_data(keys, cpreg_key_compare, NULL); - cpu->cpreg_array_len =3D 0; - - g_list_foreach(keys, count_cpreg, cpu); + g_hash_table_foreach(cpu->cp_regs, count_cpreg, cpu); =20 arraylen =3D cpu->cpreg_array_len; - cpu->cpreg_indexes =3D g_new(uint64_t, arraylen); - cpu->cpreg_values =3D g_new(uint64_t, arraylen); - cpu->cpreg_vmstate_indexes =3D g_new(uint64_t, arraylen); - cpu->cpreg_vmstate_values =3D g_new(uint64_t, arraylen); - cpu->cpreg_vmstate_array_len =3D cpu->cpreg_array_len; + if (arraylen) { + cpu->cpreg_indexes =3D g_new(uint64_t, arraylen); + cpu->cpreg_values =3D g_new(uint64_t, arraylen); + cpu->cpreg_vmstate_indexes =3D g_new(uint64_t, arraylen); + cpu->cpreg_vmstate_values =3D g_new(uint64_t, arraylen); + } else { + cpu->cpreg_indexes =3D NULL; + cpu->cpreg_values =3D NULL; + cpu->cpreg_vmstate_indexes =3D NULL; + cpu->cpreg_vmstate_values =3D NULL; + } + cpu->cpreg_vmstate_array_len =3D arraylen; cpu->cpreg_array_len =3D 0; =20 - g_list_foreach(keys, add_cpreg_to_list, cpu); + g_hash_table_foreach(cpu->cp_regs, add_cpreg_to_list, cpu); =20 assert(cpu->cpreg_array_len =3D=3D arraylen); =20 - g_list_free(keys); + if (arraylen) { + qsort(cpu->cpreg_indexes, arraylen, sizeof(uint64_t), compare_u64); + } } =20 bool arm_pan_enabled(CPUARMState *env) --=20 2.43.0 From nobody Sun Sep 28 16:37:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Bake that in to the result directly. Remove CP_REG_ARM64_SYSREG_CP as unused. Reviewed-by: Manos Pitsidianakis Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpregs.h | 5 ++--- target/arm/kvm-consts.h | 3 --- target/arm/helper.c | 11 +++++------ target/arm/hvf/hvf.c | 3 +-- target/arm/tcg/translate-a64.c | 6 ++---- 5 files changed, 10 insertions(+), 18 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 7ebe404163..95b0b9c78e 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -187,9 +187,8 @@ enum { ((is64) << CP_REG_AA32_64BIT_SHIFT) | \ ((cp) << 16) | ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) =20 -#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ - (CP_REG_AA64_MASK | \ - ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ +#define ENCODE_AA64_CP_REG(crn, crm, op0, op1, op2) \ + (CP_REG_AA64_MASK | CP_REG_ARM64_SYSREG | \ ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h index fdb305eea1..54ae5da7ce 100644 --- a/target/arm/kvm-consts.h +++ b/target/arm/kvm-consts.h @@ -160,9 +160,6 @@ MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A53, KVM_ARM_= TARGET_CORTEX_A53); #define CP_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007 #define CP_REG_ARM64_SYSREG_OP2_SHIFT 0 =20 -/* No kernel define but it's useful to QEMU */ -#define CP_REG_ARM64_SYSREG_CP (CP_REG_ARM64_SYSREG >> CP_REG_ARM_COPROC_S= HIFT) - MISMATCH_CHECK(CP_REG_ARM64, KVM_REG_ARM64); MISMATCH_CHECK(CP_REG_ARM_COPROC_MASK, KVM_REG_ARM_COPROC_MASK); MISMATCH_CHECK(CP_REG_ARM_COPROC_SHIFT, KVM_REG_ARM_COPROC_SHIFT); diff --git a/target/arm/helper.c b/target/arm/helper.c index cc924adbc7..7094b63f82 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4542,7 +4542,7 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCP= U *cpu) }; =20 #define K(op0, op1, crn, crm, op2) \ - ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2) + ENCODE_AA64_CP_REG(crn, crm, op0, op1, op2) =20 static const struct E2HAlias aliases[] =3D { { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0), @@ -7451,10 +7451,9 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons= t ARMCPRegInfo *r, * in their AArch64 view (the .cp value may be non-zero for the * benefit of the AArch32 view). */ - if (cp =3D=3D 0 || r->state =3D=3D ARM_CP_STATE_BOTH) { - cp =3D CP_REG_ARM64_SYSREG_CP; - } - key =3D ENCODE_AA64_CP_REG(cp, r->crn, crm, r->opc0, opc1, opc2); + assert(cp =3D=3D 0 || r->state =3D=3D ARM_CP_STATE_BOTH); + cp =3D 0; + key =3D ENCODE_AA64_CP_REG(r->crn, crm, r->opc0, opc1, opc2); break; default: g_assert_not_reached(); @@ -7679,7 +7678,7 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRe= gInfo *r) } break; case ARM_CP_STATE_AA64: - assert(r->cp =3D=3D 0 || r->cp =3D=3D CP_REG_ARM64_SYSREG_CP); + assert(r->cp =3D=3D 0); break; default: g_assert_not_reached(); diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 694584cc13..6e67d89163 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1124,8 +1124,7 @@ static bool is_id_sysreg(uint32_t reg) =20 static uint32_t hvf_reg2cp_reg(uint32_t reg) { - return ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, - (reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK, + return ENCODE_AA64_CP_REG((reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK, (reg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK, (reg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK, (reg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK, diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 37bedc3780..a560ef0f42 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2466,8 +2466,7 @@ static void handle_sys(DisasContext *s, bool isread, unsigned int op0, unsigned int op1, unsigned int op= 2, unsigned int crn, unsigned int crm, unsigned int rt) { - uint32_t key =3D ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, - crn, crm, op0, op1, op2); + uint32_t key =3D ENCODE_AA64_CP_REG(crn, crm, op0, op1, op2); const ARMCPRegInfo *ri =3D get_arm_cp_reginfo(s->cp_regs, key); bool need_exit_tb =3D false; bool nv_trap_to_el2 =3D false; @@ -2603,8 +2602,7 @@ static void handle_sys(DisasContext *s, bool isread, * We don't use the EL1 register's access function, and * fine-grained-traps on EL1 also do not apply here. */ - key =3D ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, - crn, crm, op0, 0, op2); + key =3D ENCODE_AA64_CP_REG(crn, crm, op0, 0, op2); ri =3D get_arm_cp_reginfo(s->cp_regs, key); assert(ri); assert(cp_access_ok(s->current_el, ri, isread)); --=20 2.43.0 From nobody Sun Sep 28 16:37:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758032785; cv=none; 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([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2651d2df15esm73459905ad.45.2025.09.16.07.22.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 07:22:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758032575; x=1758637375; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZSIAGhmwh8mZ4wBWdZ4ZwC8IrpicHIIk/ZQHhSqFh34=; b=l2tN+n/U5zVOe7rIHWNnZt+WAjC4RKfUMQoN01Uf8Q5BQJ4WW7f9yKBw6R/k3DbIjc p0sugoGXJOjiQ9yNqH9m+hmnSUR92bca0YzOsgNUUQR1PY1z8IhyMVsspeGdj7kR3Ko5 BJtuXjwsi6PKpbvjlYKJyZ4Vqsfy5yQOJLPPtR3p1DjjDn2edBbIHkCCYac9Y3aZa9Ok AO4RdYbVwx523grZ0lUEZQWAb605JVJJfW16KjfguaL+RcB1O71ZmEnaKix4NvnEkDoP 5JORahLokGJqdTx+V+qC+YNvTdtzFU/mahWyspSLuOYAaw21I0CMBgcgB2VamRiBS/yb HLAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758032575; x=1758637375; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZSIAGhmwh8mZ4wBWdZ4ZwC8IrpicHIIk/ZQHhSqFh34=; b=u3ceUT4VWiemE9u/O/OIE+5TwmCzHUBM6/Jn9hBzuFql4K/Bt9o9PERnSfH2oppWyl a7r2schCrgBB3xNpY8370nXY8LI29wAobkVLq8ikLkhJcTz8qXS1dv2Udrup3KB2lJC8 X2PNARjKnqrm8Io59TH6q/bcdks3fYubPMrGpSnbbFTLNg8N7kU3OSsV4Q9dHTrzMJh3 +0CeBtFcjv3NJ8lDeYYrcf6ETEfRyownjbacw+nCLaxJFgA2WAIHMWEF+dUyy0SwtK1s SvSTdu9UgWyfhZk8Nt1R0NF0fkQhH46zVswcYALcUWbEqpSwgZ+t/GVTy7+MJaNd9YPn 9WZw== X-Gm-Message-State: AOJu0YwI5rXF2iu/HCO3ELh0xGD+NOYx0w4fWUCFgqCEFge8pTBFoCZD yWM+tgDzygLft/2+e/Gxb06QvtCEZhvDCOs+YwViAnDLLM12KJgZi38kAX9Rqf7y4f/qjoQCU1C x125I X-Gm-Gg: ASbGnct4FrCyQdJrzWVR7OHlcbdL9rDvszKfhzbQz9G39eaJTzucR+ES2UBR7gHYndg ez1M6HLPJVaQu20O7sGYK/3dKsdUBUMQbcshI5SbItxRY0Gt0h1bYzZwIAmRx/5EQD0d16NWr6W v+Vx3q/cPUknuc/SdRJynueVehwtuuB2Fpu85OPnpSwdjeYugU0oFLtnZncdX1WabfK8S7JWz6H 45csbo3Oc/M/fddnWI9yqyCPDlsGBC/vbIX5xC02PFuwgJ4H74w+dztMJDGgbvf6tGuGV86uBjC Q9OYGhSYo/DV6xVvKSp339/PzYDz1Sta2x3N3+D8JcxwDcPGFsAmK6Scy0GnE5TMPM+RF1Ji8Io rq4CWWIHxrUqSmF/pPcHb9wS/65KM X-Google-Smtp-Source: AGHT+IEaTBui/B91+WuP7qzd0c/v5oaVCMAIgu//8CktMGyP697FmZZgXaXtjUwiQNvnERoSdLxpFw== X-Received: by 2002:a17:902:cec6:b0:266:88ae:be6d with SMTP id d9443c01a7336-26688aec242mr94412115ad.6.1758032574645; Tue, 16 Sep 2025 07:22:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, Manos Pitsidianakis Subject: [PATCH v2 19/36] target/arm: Reorder ENCODE_AA64_CP_REG arguments Date: Tue, 16 Sep 2025 07:22:20 -0700 Message-ID: <20250916142238.664316-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916142238.664316-1-richard.henderson@linaro.org> References: <20250916142238.664316-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758032785582116600 Content-Type: text/plain; charset="utf-8" The order of the parameters in the Arm ARM is op0, op1, crn, crm, op2 Reorder the arguments of ENCODE_AA64_CP_REG to match. Reviewed-by: Manos Pitsidianakis Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpregs.h | 2 +- target/arm/helper.c | 4 ++-- target/arm/hvf/hvf.c | 6 +++--- target/arm/tcg/translate-a64.c | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 95b0b9c78e..7bdf6cf847 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -187,7 +187,7 @@ enum { ((is64) << CP_REG_AA32_64BIT_SHIFT) | \ ((cp) << 16) | ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) =20 -#define ENCODE_AA64_CP_REG(crn, crm, op0, op1, op2) \ +#define ENCODE_AA64_CP_REG(op0, op1, crn, crm, op2) \ (CP_REG_AA64_MASK | CP_REG_ARM64_SYSREG | \ ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ diff --git a/target/arm/helper.c b/target/arm/helper.c index 7094b63f82..8b63eacb91 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4542,7 +4542,7 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCP= U *cpu) }; =20 #define K(op0, op1, crn, crm, op2) \ - ENCODE_AA64_CP_REG(crn, crm, op0, op1, op2) + ENCODE_AA64_CP_REG(op0, op1, crn, crm, op2) =20 static const struct E2HAlias aliases[] =3D { { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0), @@ -7453,7 +7453,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, */ assert(cp =3D=3D 0 || r->state =3D=3D ARM_CP_STATE_BOTH); cp =3D 0; - key =3D ENCODE_AA64_CP_REG(r->crn, crm, r->opc0, opc1, opc2); + key =3D ENCODE_AA64_CP_REG(r->opc0, opc1, r->crn, crm, opc2); break; default: g_assert_not_reached(); diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 6e67d89163..8b467b3663 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1124,10 +1124,10 @@ static bool is_id_sysreg(uint32_t reg) =20 static uint32_t hvf_reg2cp_reg(uint32_t reg) { - return ENCODE_AA64_CP_REG((reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK, - (reg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK, - (reg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK, + return ENCODE_AA64_CP_REG((reg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK, (reg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK, + (reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK, + (reg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK, (reg >> SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK); } =20 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index a560ef0f42..0ec309f1ea 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2466,7 +2466,7 @@ static void handle_sys(DisasContext *s, bool isread, unsigned int op0, unsigned int op1, unsigned int op= 2, unsigned int crn, unsigned int crm, unsigned int rt) { - uint32_t key =3D ENCODE_AA64_CP_REG(crn, crm, op0, op1, op2); + uint32_t key =3D ENCODE_AA64_CP_REG(op0, op1, crn, crm, op2); const ARMCPRegInfo *ri =3D get_arm_cp_reginfo(s->cp_regs, key); bool need_exit_tb =3D false; bool nv_trap_to_el2 =3D false; @@ -2602,7 +2602,7 @@ static void handle_sys(DisasContext *s, bool isread, * We don't use the EL1 register's access function, and * fine-grained-traps on EL1 also do not apply here. */ - key =3D ENCODE_AA64_CP_REG(crn, crm, op0, 0, op2); + key =3D ENCODE_AA64_CP_REG(op0, 0, crn, crm, op2); ri =3D get_arm_cp_reginfo(s->cp_regs, key); assert(ri); assert(cp_access_ok(s->current_el, ri, isread)); --=20 2.43.0 From nobody Sun Sep 28 16:37:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758032858650243.3488295999698; Tue, 16 Sep 2025 07:27:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uyWau-0006PJ-BE; Tue, 16 Sep 2025 10:23:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uyWab-0005yr-Nh for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:23:25 -0400 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uyWaT-0008LZ-Pz for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:23:25 -0400 Received: by mail-pg1-x529.google.com with SMTP id 41be03b00d2f7-b49b56a3f27so3256633a12.1 for ; Tue, 16 Sep 2025 07:22:56 -0700 (PDT) Received: from stoup.. ([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2651d2df15esm73459905ad.45.2025.09.16.07.22.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 07:22:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758032575; x=1758637375; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=O3ZI3DSvuSnKVozoGKOUzCAQ9C1UttOP4zYBt0a8luk=; b=Hfkk6nz7AEi+6meQ1pCJcKsOZhfM203qM1V9Z9M3IIzXYcRzP6St6j1swXBTWvpIhb wDo7/+5Qfrss+LHNJJzXk2U+6dE9/wArYY/4+JANu0K693z4HGwxzJUF9gk2qJeHHV/g rhYXoEko9sEAkTMO/UlS3uUmdADtyerogt0b9qfmFsFF60vPu4qoAiEwe+MaKoWrsnfk x8uql2P9oKRoak0DMgCAhvR1P7fUsI8iAb8CD3W8RNGUYtO4/oQcikqUzMh9afOkU+jX wky76JI865nbFvPvlwvfrfkZSW+VkyU0Occ4ZPFt3Ys4IRdjWxdiAuESpYhiwV0QYVUq ejsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758032575; x=1758637375; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=O3ZI3DSvuSnKVozoGKOUzCAQ9C1UttOP4zYBt0a8luk=; b=lZDMLIik+/5mLdi2IH2rJqEBNqxBJkmAHMdx9cn/IJCAvoSbCvjC8HVRroZpftGw8f CQACtK81V6jIwnRdwIvcMKBzKtm3penMpdHwijM4zUV45ROqoxT4ptwyr25ELYF3VaoX feqWbB0ks+OhGX+BRxE3n0rXHX+l7mVuGAQl6mEzeMXgdSCJQgaA9NxJdOfjBcw8nZlU OwhCxYK42jLXX+UUC2OppLdHJA/zQ0BzDTlfPN7bj4M+iyKKJsGqdxgU0CESCA2rKHcE YulU/MmOPg5olLrR88yqQYyoDCpuBzaJANnbkAKVY45rMnkU6UPElrWYDMImwV63drzN m1mQ== X-Gm-Message-State: AOJu0Yy87LuW0nqTWAQL17zhVLj/s3mdl71r6IFeSbS2ws5hmf6MJGas E8YkHxiFm2KJYHM8t6g9WUhCdKrJHLeOuPGelLV7bNCHsdjGyyqSQuSD69Gg1UeUbj+pwc8q9WK beha9 X-Gm-Gg: ASbGncuNeZVSNPHUplBAop6CH51/cXxT/NmwuEpUmsqskcAXTLy3no1EPSBDSjMTBTK 4O3WEZzOiDO7X0epittHq+I1JmT73A3gd8YRiEe827ZHbLFRCbqsCJ02vdJNm8IyY0e4xk00IaR +v0LdB6DHVpJOSVasfDfdQadxtU8i/DaIrmyrr3xcP2QaRi8Q9QIZm3XUBNoGSziGu/9SLeuUhp vMt99sK0juQg6xQTn6QAR7AYaJz7nk8zCyVQAgEGB2kb/aOWeUCVzM5dH9CiVjaZbnmyZ4z7dU/ l7DSC5gwx5Ir5rlbgN58j489bhrmuxjAwXB7/AUVdYuxyb5ZHnNzKXlT3UOWogEu2m05WIS7qTV b0NZDXpooiFIexLTd3rrgfxUUiWmsrUi2HafzfDE= X-Google-Smtp-Source: AGHT+IEliu+Ux8ncYvtfLYROnFdzKeiFM8UHKSBUqvd3juzX+RrflFEdZz1RIIhhHxfDG7KCpF0jzA== X-Received: by 2002:a17:903:230d:b0:263:671e:397b with SMTP id d9443c01a7336-263671e3beemr122575215ad.7.1758032575412; Tue, 16 Sep 2025 07:22:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v2 20/36] target/arm: Split out add_cpreg_to_hashtable_aa{32, 64} Date: Tue, 16 Sep 2025 07:22:21 -0700 Message-ID: <20250916142238.664316-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916142238.664316-1-richard.henderson@linaro.org> References: <20250916142238.664316-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1758032860549116600 Content-Type: text/plain; charset="utf-8" The nesting level for the inner loop of define_one_arm_cp_reg was overly deep. Split out that code into two functions, for the AArch32 and AArch64 paths separately. Simplify the innermost loop to a switch statement over r->state. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/helper.c | 147 +++++++++++++++++++++++--------------------- 1 file changed, 76 insertions(+), 71 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8b63eacb91..ec78c8f08f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7612,6 +7612,66 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons= t ARMCPRegInfo *r, g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2); } =20 +static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, const ARMCPRegInfo *r, + int crm, int opc1, int opc2) +{ + /* + * Under AArch32 CP registers can be common + * (same for secure and non-secure world) or banked. + */ + char *name; + + assert(!(r->type & ARM_CP_ADD_TLBI_NXS)); /* aa64 only */ + + switch (r->secure) { + case ARM_CP_SECSTATE_S: + case ARM_CP_SECSTATE_NS: + add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, + r->secure, crm, opc1, opc2, r->name); + break; + case ARM_CP_SECSTATE_BOTH: + name =3D g_strdup_printf("%s_S", r->name); + add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, + ARM_CP_SECSTATE_S, crm, opc1, opc2, name); + g_free(name); + add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, + ARM_CP_SECSTATE_NS, crm, opc1, opc2, r->nam= e); + break; + default: + g_assert_not_reached(); + } +} + +static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu, const ARMCPRegInfo *r, + int crm, int opc1, int opc2) +{ + if ((r->type & ARM_CP_ADD_TLBI_NXS) && + cpu_isar_feature(aa64_xs, cpu)) { + /* + * This is a TLBI insn which has an NXS variant. The + * NXS variant is at the same encoding except that + * crn is +1, and has the same behaviour except for + * fine-grained trapping. Add the NXS insn here and + * then fall through to add the normal register. + * add_cpreg_to_hashtable() copies the cpreg struct + * and name that it is passed, so it's OK to use + * a local struct here. + */ + ARMCPRegInfo nxs_ri =3D *r; + g_autofree char *name =3D g_strdup_printf("%sNXS", r->name); + + assert(nxs_ri.crn < 0xf); + nxs_ri.crn++; + if (nxs_ri.fgt) { + nxs_ri.fgt |=3D R_FGT_NXS_MASK; + } + add_cpreg_to_hashtable(cpu, &nxs_ri, ARM_CP_STATE_AA64, + ARM_CP_SECSTATE_NS, crm, opc1, opc2, name); + } + + add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA64, ARM_CP_SECSTATE_NS, + crm, opc1, opc2, r->name); +} =20 void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r) { @@ -7639,14 +7699,12 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCP= RegInfo *r) * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of * the register, if any. */ - int crm, opc1, opc2; int crmmin =3D (r->crm =3D=3D CP_ANY) ? 0 : r->crm; int crmmax =3D (r->crm =3D=3D CP_ANY) ? 15 : r->crm; int opc1min =3D (r->opc1 =3D=3D CP_ANY) ? 0 : r->opc1; int opc1max =3D (r->opc1 =3D=3D CP_ANY) ? 7 : r->opc1; int opc2min =3D (r->opc2 =3D=3D CP_ANY) ? 0 : r->opc2; int opc2max =3D (r->opc2 =3D=3D CP_ANY) ? 7 : r->opc2; - CPState state; =20 /* 64 bit registers have only CRm and Opc1 fields */ assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); @@ -7743,75 +7801,22 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCP= RegInfo *r) } } =20 - for (crm =3D crmmin; crm <=3D crmmax; crm++) { - for (opc1 =3D opc1min; opc1 <=3D opc1max; opc1++) { - for (opc2 =3D opc2min; opc2 <=3D opc2max; opc2++) { - for (state =3D ARM_CP_STATE_AA32; - state <=3D ARM_CP_STATE_AA64; state++) { - if (r->state !=3D state && r->state !=3D ARM_CP_STATE_= BOTH) { - continue; - } - if ((r->type & ARM_CP_ADD_TLBI_NXS) && - cpu_isar_feature(aa64_xs, cpu)) { - /* - * This is a TLBI insn which has an NXS variant. T= he - * NXS variant is at the same encoding except that - * crn is +1, and has the same behaviour except for - * fine-grained trapping. Add the NXS insn here and - * then fall through to add the normal register. - * add_cpreg_to_hashtable() copies the cpreg struct - * and name that it is passed, so it's OK to use - * a local struct here. - */ - ARMCPRegInfo nxs_ri =3D *r; - g_autofree char *name =3D g_strdup_printf("%sNXS",= r->name); - - assert(state =3D=3D ARM_CP_STATE_AA64); - assert(nxs_ri.crn < 0xf); - nxs_ri.crn++; - if (nxs_ri.fgt) { - nxs_ri.fgt |=3D R_FGT_NXS_MASK; - } - add_cpreg_to_hashtable(cpu, &nxs_ri, state, - ARM_CP_SECSTATE_NS, - crm, opc1, opc2, name); - } - if (state =3D=3D ARM_CP_STATE_AA32) { - /* - * Under AArch32 CP registers can be common - * (same for secure and non-secure world) or banke= d. - */ - char *name; - - switch (r->secure) { - case ARM_CP_SECSTATE_S: - case ARM_CP_SECSTATE_NS: - add_cpreg_to_hashtable(cpu, r, state, - r->secure, crm, opc1, o= pc2, - r->name); - break; - case ARM_CP_SECSTATE_BOTH: - name =3D g_strdup_printf("%s_S", r->name); - add_cpreg_to_hashtable(cpu, r, state, - ARM_CP_SECSTATE_S, - crm, opc1, opc2, name); - g_free(name); - add_cpreg_to_hashtable(cpu, r, state, - ARM_CP_SECSTATE_NS, - crm, opc1, opc2, r->nam= e); - break; - default: - g_assert_not_reached(); - } - } else { - /* - * AArch64 registers get mapped to non-secure inst= ance - * of AArch32 - */ - add_cpreg_to_hashtable(cpu, r, state, - ARM_CP_SECSTATE_NS, - crm, opc1, opc2, r->name); - } + for (int crm =3D crmmin; crm <=3D crmmax; crm++) { + for (int opc1 =3D opc1min; opc1 <=3D opc1max; opc1++) { + for (int opc2 =3D opc2min; opc2 <=3D opc2max; opc2++) { + switch (r->state) { + case ARM_CP_STATE_AA32: + add_cpreg_to_hashtable_aa32(cpu, r, crm, opc1, opc2); + break; + case ARM_CP_STATE_AA64: + add_cpreg_to_hashtable_aa64(cpu, r, crm, opc1, opc2); + break; + case ARM_CP_STATE_BOTH: + add_cpreg_to_hashtable_aa32(cpu, r, crm, opc1, opc2); + add_cpreg_to_hashtable_aa64(cpu, r, crm, opc1, opc2); + break; + default: + g_assert_not_reached(); } } } --=20 2.43.0 From nobody Sun Sep 28 16:37:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758033171; cv=none; d=zohomail.com; s=zohoarc; b=PwK5Cys8VVeLg7OtNozDDz1D5q1Qh6iga1zjgkF92Fkq4s8IoLorrJNyj6aqONzOy4/uYU8ucSgy9z1tsjRhJJCIhm4RL4+up68jFLQ/hbD75RDEcJvMqqvkd+zkspn2YnEihqJHnHCHMOkOi9smMhuc8DyV4j1LSN0mmN9rfYc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758033171; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=nCzDp8Y5rVmGyXdmc/HyYS3z4EeUCME39z0RM1On4WM=; b=Z0V2nfbm87yROT6ZTbWAHCJ1ZHpKi9c4GnQPLpJ1PHp5snm/kj3kcHH4sIskGYlqwmtFUqFGa8O6ewWSGUL/LZv7hFXLNoijot6Z899sirspoNer9Sdm4GTIC+Vc+N9lv7ypBevTDZt1KFzuuQ8Gw+2DW0RCP5XUJQT4eDnXwT4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758033171400578.5948675912358; Tue, 16 Sep 2025 07:32:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uyWaY-0005wD-SV; Tue, 16 Sep 2025 10:23:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uyWaL-0005ny-O6 for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:23:11 -0400 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uyWaB-0008Lh-K3 for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:23:02 -0400 Received: by mail-pf1-x434.google.com with SMTP id d2e1a72fcca58-77619f3f41aso3158736b3a.2 for ; Tue, 16 Sep 2025 07:22:57 -0700 (PDT) Received: from stoup.. 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Remove some extra parens; distribute ! across && to simplify. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/helper.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index ec78c8f08f..8a805695e7 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7706,12 +7706,17 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCP= RegInfo *r) int opc2min =3D (r->opc2 =3D=3D CP_ANY) ? 0 : r->opc2; int opc2max =3D (r->opc2 =3D=3D CP_ANY) ? 7 : r->opc2; =20 - /* 64 bit registers have only CRm and Opc1 fields */ - assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); + /* + * AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless. + * Moreover, the encoding test just following in general prevents + * shared encoding so ARM_CP_STATE_BOTH won't work either. + */ + assert(r->state =3D=3D ARM_CP_STATE_AA32 || !(r->type & ARM_CP_64BIT)); + /* AArch32 64-bit registers have only CRm and Opc1 fields. */ + assert(!(r->type & ARM_CP_64BIT) || !(r->opc2 || r->crn)); /* op0 only exists in the AArch64 encodings */ - assert((r->state !=3D ARM_CP_STATE_AA32) || (r->opc0 =3D=3D 0)); - /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */ - assert((r->state !=3D ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT)); + assert(r->state !=3D ARM_CP_STATE_AA32 || r->opc0 =3D=3D 0); + /* * This API is only for Arm's system coprocessors (14 and 15) or * (M-profile or v7A-and-earlier only) for implementation defined --=20 2.43.0 From nobody Sun Sep 28 16:37:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758033012; cv=none; d=zohomail.com; s=zohoarc; b=aqBfRf7UExh1ljM5px2DZh/NZxvDJDVFsxbptHkVEa2I3+pDS/4B0XfcQACOLKwpXdbLCVWaNiPq0pb1TLOpCepmmA+crbJGQzaNnA9GLvOHQeNuKOB8JpUKJpkYfpArXHc/t8PQazU+ccJn6xo516j2HPEm440e/X8Oq0P/Pvo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758033012; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=bzhiPXajZJRszhCyhe8mLWWa9FpDgmyenFp0rRBwLqQ=; b=fybv0FMCG0fTYw5zHcfcrO4pdFIIsystmK+3y0qce0DdvYVP7kpG3e0b54/IUSVLivHhbUm8qoN19n00kMswhWHpHXahmXICYZrmI9GddHruKAOdB6GiOSA8j6QAt/Ppgu9JAk4qmgveEwu+dFf5tEoR8Bddtlfw2CF5ttP4MZ8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758033012737757.8139469284637; Tue, 16 Sep 2025 07:30:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uyWcw-0000hU-W7; Tue, 16 Sep 2025 10:25:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uyWan-0006BR-Aj for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:23:37 -0400 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uyWaU-0008Lu-SH for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:23:32 -0400 Received: by mail-pg1-x52c.google.com with SMTP id 41be03b00d2f7-b49c1c130c9so3703839a12.0 for ; Tue, 16 Sep 2025 07:22:58 -0700 (PDT) Received: from stoup.. ([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2651d2df15esm73459905ad.45.2025.09.16.07.22.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 07:22:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758032577; x=1758637377; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bzhiPXajZJRszhCyhe8mLWWa9FpDgmyenFp0rRBwLqQ=; b=mwNUyMLzMpJCFOJX4T2uqSQ6Dgkw371+U4aezzqI2+EmUb8aqwQYaYiws9+Sg3k146 3HuVg47P3NibGYjEPqXW+sBu0Qq5i9zKI6ncoqACTdm0L6M76qLpCMNaMk4QEiecSvkS wJJ0Jasd+xRNU8RXm6W4oOtU9iiZYRfL0BgVigOG6RhmzBZzQjLkzKGyuCq128bDWc5E eDM92U896fNtNclJZAypXppLwX0uq34k4fd0UaNbvJbE/k3Of+fMII+k/RWCup+9hzYZ oyGsPfhbjc3QAq2DaBOQcefzw6gMkJPpveiGHZqgiUxQaqhF9+66qxKWP8N35Yelw0ZE TEpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758032577; x=1758637377; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bzhiPXajZJRszhCyhe8mLWWa9FpDgmyenFp0rRBwLqQ=; b=t6rdnSZIGEGOJq7qAtS6hkgAAxTAN/y2twoVSH/opk5p5MmnhlVPYr7L+X/MHn/Dn6 OcpGyj8PAjgovMBbG/ZHj7pB9wGnUfLoqMLfWV4BzPZegblhDG4KjCorHShevz65e3ik /dDco4u7wdUM/JXnd9fAXkuZEUIX3XVb3vHsYGY2zPEcQfWEIk2WSMwI6O0vHA1f1Oti sbBqE5itTYWwQvjhFgC2tdCHFwcSKbSpwW7iwic11LsNVtZnStVUWYn6rxWiPi3LKx/D SpEoJEGSOJ222Ew90/vF0SBwqtg+QNaS8FqxUi+OzQPVTlgSCL25scZY/+Hyx+H4360B Pysg== X-Gm-Message-State: AOJu0YyyJIgaUvN1YZi8rpjtTyEUZ23FTvSTvtAB5BHDUQrZyyTrbCCx 6HksoLx3QobnayZ5laFygMWiZtkJndMgGUq4/BrNhsf6tuzXF38KiSO20paUBKi2uGE0iHdiItS A5xF8 X-Gm-Gg: ASbGnctrHDj6eZazgxey0LJ4s7rTA9E7Tofav4mTTIRUbCVLohVWJpaNUD96x7eh49Q BXi+hQ3njwewNka3fdAnO7a1CeqIPG2BBUo8CfAwqOWrRos4nR5GhHRthuzYQdzboTCfQw6wm// TWbV+pdi112kQfQWaXlsMBpkVUR6UNZQ3on9KkGgTnE/KbMv9qhwgJZ3hK/gd8jLzLZNzTsJqB1 VbupNldrl4aoCY/JDSbL2CGvopn2MRuM3wbWsKpGcevVsC3ss8CD9fIPxH6ocuZf4JOzPFz5+is u2P5DQ7m0NIzY2bewBV5Jd5kPAFeMhuATU+sajIsFdeO3d+tOQA7nPa+ROMs4UjaiJhXVxZwIOS KIiyz9nwAUATAB1C91STl21VID10c X-Google-Smtp-Source: AGHT+IENfarK0YxcFSJU0siJSUN3UzZfT2Zm22mSlnTTj8nQUyl171MTi5rWdHR6/FDp6Zd0BFiHxA== X-Received: by 2002:a17:902:cf09:b0:260:b4c7:986d with SMTP id d9443c01a7336-260b4c799f1mr149063525ad.36.1758032576764; Tue, 16 Sep 2025 07:22:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v2 22/36] target/arm: Move cp processing to define_one_arm_cp_reg Date: Tue, 16 Sep 2025 07:22:23 -0700 Message-ID: <20250916142238.664316-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916142238.664316-1-richard.henderson@linaro.org> References: <20250916142238.664316-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758033015314116600 Content-Type: text/plain; charset="utf-8" Processing of cp was split between add_cpreg_to_hashtable and define_one_arm_cp_reg. Unify it all to the top-level function. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/helper.c | 53 +++++++++++++++++++-------------------------- 1 file changed, 22 insertions(+), 31 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8a805695e7..0eedbacc2b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7423,7 +7423,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) */ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, CPState state, CPSecureState secstate, - int crm, int opc1, int opc2, + int cp, int crm, int opc1, int opc2, const char *name) { CPUARMState *env =3D &cpu->env; @@ -7431,28 +7431,14 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, con= st ARMCPRegInfo *r, ARMCPRegInfo *r2; bool is64 =3D r->type & ARM_CP_64BIT; bool ns =3D secstate & ARM_CP_SECSTATE_NS; - int cp =3D r->cp; size_t name_len; bool make_const; =20 switch (state) { case ARM_CP_STATE_AA32: - /* We assume it is a cp15 register if the .cp field is left unset.= */ - if (cp =3D=3D 0 && r->state =3D=3D ARM_CP_STATE_BOTH) { - cp =3D 15; - } key =3D ENCODE_CP_REG(cp, is64, ns, r->crn, crm, opc1, opc2); break; case ARM_CP_STATE_AA64: - /* - * To allow abbreviation of ARMCPRegInfo definitions, we treat - * cp =3D=3D 0 as equivalent to the value for "standard guest-visi= ble - * sysreg". STATE_BOTH definitions are also always "standard sysr= eg" - * in their AArch64 view (the .cp value may be non-zero for the - * benefit of the AArch32 view). - */ - assert(cp =3D=3D 0 || r->state =3D=3D ARM_CP_STATE_BOTH); - cp =3D 0; key =3D ENCODE_AA64_CP_REG(r->opc0, opc1, r->crn, crm, opc2); break; default: @@ -7613,7 +7599,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, } =20 static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, const ARMCPRegInfo *r, - int crm, int opc1, int opc2) + int cp, int crm, int opc1, int opc= 2) { /* * Under AArch32 CP registers can be common @@ -7626,16 +7612,16 @@ static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu= , const ARMCPRegInfo *r, switch (r->secure) { case ARM_CP_SECSTATE_S: case ARM_CP_SECSTATE_NS: - add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, - r->secure, crm, opc1, opc2, r->name); + add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, r->secure, + cp, crm, opc1, opc2, r->name); break; case ARM_CP_SECSTATE_BOTH: name =3D g_strdup_printf("%s_S", r->name); - add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, - ARM_CP_SECSTATE_S, crm, opc1, opc2, name); + add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, ARM_CP_SECSTATE_= S, + cp, crm, opc1, opc2, name); g_free(name); - add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, - ARM_CP_SECSTATE_NS, crm, opc1, opc2, r->nam= e); + add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, ARM_CP_SECSTATE_= NS, + cp, crm, opc1, opc2, r->name); break; default: g_assert_not_reached(); @@ -7666,11 +7652,11 @@ static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu= , const ARMCPRegInfo *r, nxs_ri.fgt |=3D R_FGT_NXS_MASK; } add_cpreg_to_hashtable(cpu, &nxs_ri, ARM_CP_STATE_AA64, - ARM_CP_SECSTATE_NS, crm, opc1, opc2, name); + ARM_CP_SECSTATE_NS, 0, crm, opc1, opc2, nam= e); } =20 add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA64, ARM_CP_SECSTATE_NS, - crm, opc1, opc2, r->name); + 0, crm, opc1, opc2, r->name); } =20 void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r) @@ -7705,6 +7691,7 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRe= gInfo *r) int opc1max =3D (r->opc1 =3D=3D CP_ANY) ? 7 : r->opc1; int opc2min =3D (r->opc2 =3D=3D CP_ANY) ? 0 : r->opc2; int opc2max =3D (r->opc2 =3D=3D CP_ANY) ? 7 : r->opc2; + int cp =3D r->cp; =20 /* * AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless. @@ -7727,21 +7714,25 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCP= RegInfo *r) */ switch (r->state) { case ARM_CP_STATE_BOTH: - /* 0 has a special meaning, but otherwise the same rules as AA32. = */ - if (r->cp =3D=3D 0) { + /* + * If the cp field is left unset, assume cp15. + * Otherwise apply the same rules as AA32. + */ + if (cp =3D=3D 0) { + cp =3D 15; break; } /* fall through */ case ARM_CP_STATE_AA32: if (arm_feature(&cpu->env, ARM_FEATURE_V8) && !arm_feature(&cpu->env, ARM_FEATURE_M)) { - assert(r->cp >=3D 14 && r->cp <=3D 15); + assert(cp >=3D 14 && cp <=3D 15); } else { - assert(r->cp < 8 || (r->cp >=3D 14 && r->cp <=3D 15)); + assert(cp < 8 || (cp >=3D 14 && cp <=3D 15)); } break; case ARM_CP_STATE_AA64: - assert(r->cp =3D=3D 0); + assert(cp =3D=3D 0); break; default: g_assert_not_reached(); @@ -7811,13 +7802,13 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCP= RegInfo *r) for (int opc2 =3D opc2min; opc2 <=3D opc2max; opc2++) { switch (r->state) { case ARM_CP_STATE_AA32: - add_cpreg_to_hashtable_aa32(cpu, r, crm, opc1, opc2); + add_cpreg_to_hashtable_aa32(cpu, r, cp, crm, opc1, opc= 2); break; case ARM_CP_STATE_AA64: add_cpreg_to_hashtable_aa64(cpu, r, crm, opc1, opc2); break; case ARM_CP_STATE_BOTH: - add_cpreg_to_hashtable_aa32(cpu, r, crm, opc1, opc2); + add_cpreg_to_hashtable_aa32(cpu, r, cp, crm, opc1, opc= 2); add_cpreg_to_hashtable_aa64(cpu, r, crm, opc1, opc2); break; default: --=20 2.43.0 From nobody Sun Sep 28 16:37:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758033065; cv=none; d=zohomail.com; s=zohoarc; b=KsP1ibNo1uLfWiqZN0r+0VrxVcr5YSac0BVVpFL0Ofo33mqx33tDsH0iCkFCuLvnXwxrK/D4rFuByKo/QONvTmj5zkGf6V59GH08xET4wuhUmoWNPhHjqONxFfBQpnnSzlaLoqHCpIwv28X1PumfWtCrSou6YCWBD5lpbxiPuEU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758033065; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=izULxd/xPJJeJxDcsNdLsFI/0M1j8/7oFIq6UaqJp58=; b=ByYEmbXqSi2XvC+EYy8PtD3ys2/RYZHZ4QSLzZF4kznk5Zsp5Muk14DKz1GeY44kbEN61a7HklzgoBttNAn8aShoXxZ1nuDCFwBXVj0D40WzNU6rTnXoDNfWwwDmAV8sieLSlOAVCzacRa4DBgrVEO8eGJGpMF7g5YQq2bWK6T4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758033065606199.30353853933445; Tue, 16 Sep 2025 07:31:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uyWbW-0006l2-7z; Tue, 16 Sep 2025 10:24:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uyWaZ-0005wx-LF for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:23:23 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uyWaT-0008M5-O2 for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:23:23 -0400 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-267f0fe72a1so2622805ad.2 for ; Tue, 16 Sep 2025 07:22:58 -0700 (PDT) Received: from stoup.. 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Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/helper.c | 123 +++++++++++++++++++++++--------------------- 1 file changed, 64 insertions(+), 59 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0eedbacc2b..4a109a113d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7432,7 +7432,6 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, bool is64 =3D r->type & ARM_CP_64BIT; bool ns =3D secstate & ARM_CP_SECSTATE_NS; size_t name_len; - bool make_const; =20 switch (state) { case ARM_CP_STATE_AA32: @@ -7453,32 +7452,6 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons= t ARMCPRegInfo *r, } } =20 - /* - * Eliminate registers that are not present because the EL is missing. - * Doing this here makes it easier to put all registers for a given - * feature into the same ARMCPRegInfo array and define them all at onc= e. - */ - make_const =3D false; - if (arm_feature(env, ARM_FEATURE_EL3)) { - /* - * An EL2 register without EL2 but with EL3 is (usually) RES0. - * See rule RJFFP in section D1.1.3 of DDI0487H.a. - */ - int min_el =3D ctz32(r->access) / 2; - if (min_el =3D=3D 2 && !arm_feature(env, ARM_FEATURE_EL2)) { - if (r->type & ARM_CP_EL3_NO_EL2_UNDEF) { - return; - } - make_const =3D !(r->type & ARM_CP_EL3_NO_EL2_KEEP); - } - } else { - CPAccessRights max_el =3D (arm_feature(env, ARM_FEATURE_EL2) - ? PL2_RW : PL1_RW); - if ((r->access & max_el) =3D=3D 0) { - return; - } - } - /* Combine cpreg and name into one allocation. */ name_len =3D strlen(name) + 1; r2 =3D g_malloc(sizeof(*r2) + name_len); @@ -7496,38 +7469,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons= t ARMCPRegInfo *r, r2->state =3D state; r2->secure =3D secstate; =20 - if (make_const) { - /* This should not have been a very special register to begin. */ - int old_special =3D r2->type & ARM_CP_SPECIAL_MASK; - assert(old_special =3D=3D 0 || old_special =3D=3D ARM_CP_NOP); - /* - * Set the special function to CONST, retaining the other flags. - * This is important for e.g. ARM_CP_SVE so that we still - * take the SVE trap if CPTR_EL3.EZ =3D=3D 0. - */ - r2->type =3D (r2->type & ~ARM_CP_SPECIAL_MASK) | ARM_CP_CONST; - /* - * Usually, these registers become RES0, but there are a few - * special cases like VPIDR_EL2 which have a constant non-zero - * value with writes ignored. - */ - if (!(r->type & ARM_CP_EL3_NO_EL2_C_NZ)) { - r2->resetvalue =3D 0; - } - /* - * ARM_CP_CONST has precedence, so removing the callbacks and - * offsets are not strictly necessary, but it is potentially - * less confusing to debug later. - */ - r2->readfn =3D NULL; - r2->writefn =3D NULL; - r2->raw_readfn =3D NULL; - r2->raw_writefn =3D NULL; - r2->resetfn =3D NULL; - r2->fieldoffset =3D 0; - r2->bank_fieldoffsets[0] =3D 0; - r2->bank_fieldoffsets[1] =3D 0; - } else { + { bool isbanked =3D r->bank_fieldoffsets[0] && r->bank_fieldoffsets[= 1]; =20 if (isbanked) { @@ -7692,6 +7634,8 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRe= gInfo *r) int opc2min =3D (r->opc2 =3D=3D CP_ANY) ? 0 : r->opc2; int opc2max =3D (r->opc2 =3D=3D CP_ANY) ? 7 : r->opc2; int cp =3D r->cp; + ARMCPRegInfo r_const; + CPUARMState *env =3D &cpu->env; =20 /* * AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless. @@ -7797,6 +7741,67 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPR= egInfo *r) } } =20 + /* + * Eliminate registers that are not present because the EL is missing. + * Doing this here makes it easier to put all registers for a given + * feature into the same ARMCPRegInfo array and define them all at onc= e. + */ + if (arm_feature(env, ARM_FEATURE_EL3)) { + /* + * An EL2 register without EL2 but with EL3 is (usually) RES0. + * See rule RJFFP in section D1.1.3 of DDI0487H.a. + */ + int min_el =3D ctz32(r->access) / 2; + if (min_el =3D=3D 2 && !arm_feature(env, ARM_FEATURE_EL2)) { + if (r->type & ARM_CP_EL3_NO_EL2_UNDEF) { + return; + } + if (!(r->type & ARM_CP_EL3_NO_EL2_KEEP)) { + /* This should not have been a very special register. */ + int old_special =3D r->type & ARM_CP_SPECIAL_MASK; + assert(old_special =3D=3D 0 || old_special =3D=3D ARM_CP_N= OP); + + r_const =3D *r; + + /* + * Set the special function to CONST, retaining the other = flags. + * This is important for e.g. ARM_CP_SVE so that we still + * take the SVE trap if CPTR_EL3.EZ =3D=3D 0. + */ + r_const.type =3D (r->type & ~ARM_CP_SPECIAL_MASK) | ARM_CP= _CONST; + /* + * Usually, these registers become RES0, but there are a f= ew + * special cases like VPIDR_EL2 which have a constant non-= zero + * value with writes ignored. + */ + if (!(r->type & ARM_CP_EL3_NO_EL2_C_NZ)) { + r_const.resetvalue =3D 0; + } + /* + * ARM_CP_CONST has precedence, so removing the callbacks = and + * offsets are not strictly necessary, but it is potential= ly + * less confusing to debug later. + */ + r_const.readfn =3D NULL; + r_const.writefn =3D NULL; + r_const.raw_readfn =3D NULL; + r_const.raw_writefn =3D NULL; + r_const.resetfn =3D NULL; + r_const.fieldoffset =3D 0; + r_const.bank_fieldoffsets[0] =3D 0; + r_const.bank_fieldoffsets[1] =3D 0; + + r =3D &r_const; + } + } + } else { + CPAccessRights max_el =3D (arm_feature(env, ARM_FEATURE_EL2) + ? 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Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/helper.c | 39 +++++++++++++++++++-------------------- 1 file changed, 19 insertions(+), 20 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 4a109a113d..a5195e296d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7424,26 +7424,13 @@ void register_cp_regs_for_features(ARMCPU *cpu) static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, CPState state, CPSecureState secstate, int cp, int crm, int opc1, int opc2, - const char *name) + const char *name, uint32_t key) { CPUARMState *env =3D &cpu->env; - uint32_t key; ARMCPRegInfo *r2; - bool is64 =3D r->type & ARM_CP_64BIT; bool ns =3D secstate & ARM_CP_SECSTATE_NS; size_t name_len; =20 - switch (state) { - case ARM_CP_STATE_AA32: - key =3D ENCODE_CP_REG(cp, is64, ns, r->crn, crm, opc1, opc2); - break; - case ARM_CP_STATE_AA64: - key =3D ENCODE_AA64_CP_REG(r->opc0, opc1, r->crn, crm, opc2); - break; - default: - g_assert_not_reached(); - } - /* Overriding of an existing definition must be explicitly requested. = */ if (!(r->type & ARM_CP_OVERRIDE)) { const ARMCPRegInfo *oldreg =3D get_arm_cp_reginfo(cpu->cp_regs, ke= y); @@ -7548,22 +7535,28 @@ static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu= , const ARMCPRegInfo *r, * (same for secure and non-secure world) or banked. */ char *name; + bool is64 =3D r->type & ARM_CP_64BIT; + uint32_t key =3D ENCODE_CP_REG(cp, is64, 0, r->crn, crm, opc1, opc2); =20 assert(!(r->type & ARM_CP_ADD_TLBI_NXS)); /* aa64 only */ =20 switch (r->secure) { - case ARM_CP_SECSTATE_S: case ARM_CP_SECSTATE_NS: + key |=3D CP_REG_AA32_NS_MASK; + /* fall through */ + case ARM_CP_SECSTATE_S: add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, r->secure, - cp, crm, opc1, opc2, r->name); + cp, crm, opc1, opc2, r->name, key); break; case ARM_CP_SECSTATE_BOTH: name =3D g_strdup_printf("%s_S", r->name); add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, ARM_CP_SECSTATE_= S, - cp, crm, opc1, opc2, name); + cp, crm, opc1, opc2, name, key); g_free(name); + + key |=3D CP_REG_AA32_NS_MASK; add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, ARM_CP_SECSTATE_= NS, - cp, crm, opc1, opc2, r->name); + cp, crm, opc1, opc2, r->name, key); break; default: g_assert_not_reached(); @@ -7573,6 +7566,8 @@ static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, = const ARMCPRegInfo *r, static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu, const ARMCPRegInfo *r, int crm, int opc1, int opc2) { + uint32_t key =3D ENCODE_AA64_CP_REG(r->opc0, opc1, r->crn, crm, opc2); + if ((r->type & ARM_CP_ADD_TLBI_NXS) && cpu_isar_feature(aa64_xs, cpu)) { /* @@ -7587,18 +7582,22 @@ static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu= , const ARMCPRegInfo *r, */ ARMCPRegInfo nxs_ri =3D *r; g_autofree char *name =3D g_strdup_printf("%sNXS", r->name); + uint32_t nxs_key; =20 assert(nxs_ri.crn < 0xf); nxs_ri.crn++; + nxs_key =3D key + (1 << CP_REG_ARM64_SYSREG_CRN_SHIFT); if (nxs_ri.fgt) { nxs_ri.fgt |=3D R_FGT_NXS_MASK; } + add_cpreg_to_hashtable(cpu, &nxs_ri, ARM_CP_STATE_AA64, - ARM_CP_SECSTATE_NS, 0, crm, opc1, opc2, nam= e); + ARM_CP_SECSTATE_NS, 0, crm, opc1, opc2, + name, nxs_key); } =20 add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA64, ARM_CP_SECSTATE_NS, - 0, crm, opc1, opc2, r->name); + 0, crm, opc1, opc2, r->name, key); } =20 void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r) --=20 2.43.0 From nobody Sun Sep 28 16:37:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758033252; cv=none; d=zohomail.com; s=zohoarc; b=I2iSBueAq0DrLboa6uHwTtd+XqaBnM8JpVw7D2+kVhOWLfe2JO7iA4BKnlIsOeRUZFBgKhoPpTOvPL5UxrF0gPr83viRv+wtz10hdSUUVSOE0aT5A3e0hqXrq+jmc3SOe+YEi/rNTSF4lQyPcFr/sNSwrI76wLfJ257is6rUlXo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758033252; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/helper.c | 29 +++++++++++++++++++++++------ 1 file changed, 23 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index a5195e296d..7f55ea726d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7417,6 +7417,28 @@ void register_cp_regs_for_features(ARMCPU *cpu) #endif } =20 +/* + * Copy a ARMCPRegInfo structure, allocating it along with the name + * and an optional suffix to the name. + */ +static ARMCPRegInfo *alloc_cpreg(const ARMCPRegInfo *in, + const char *name, const char *suffix) +{ + size_t name_len =3D strlen(name); + size_t suff_len =3D suffix ? strlen(suffix) : 0; + ARMCPRegInfo *out =3D g_malloc(sizeof(*in) + name_len + suff_len + 1); + char *p =3D (char *)(out + 1); + + *out =3D *in; + out->name =3D p; + + memcpy(p, name, name_len + 1); + if (suffix) { + memcpy(p + name_len, suffix, suff_len + 1); + } + return out; +} + /* * Private utility function for define_one_arm_cp_reg(): * add a single reginfo struct to the hash table. @@ -7429,7 +7451,6 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, CPUARMState *env =3D &cpu->env; ARMCPRegInfo *r2; bool ns =3D secstate & ARM_CP_SECSTATE_NS; - size_t name_len; =20 /* Overriding of an existing definition must be explicitly requested. = */ if (!(r->type & ARM_CP_OVERRIDE)) { @@ -7439,11 +7460,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons= t ARMCPRegInfo *r, } } =20 - /* Combine cpreg and name into one allocation. */ - name_len =3D strlen(name) + 1; - r2 =3D g_malloc(sizeof(*r2) + name_len); - *r2 =3D *r; - r2->name =3D memcpy(r2 + 1, name, name_len); + r2 =3D alloc_cpreg(r, name, NULL); =20 /* * Update fields to match the instantiation, overwiting wildcards --=20 2.43.0 From nobody Sun Sep 28 16:37:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758032967; cv=none; d=zohomail.com; s=zohoarc; b=ODM+9H6oko+QHhL3WPs7hMDY+Xp3KJT/mmIu2oR+8uvxi49xyBlCKeZ/zaO10Xvq3o0RTFT+txCjNMaNiBYWPfGuplG8KyBCJ8zeVrtHxoyTKiOmbb/p7fNkIyRO2LQdiLjqfczt0DQCIF3bIDaCdSUeduyWYIkchX2fNwubSN4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758032967; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=jRgfGoWkJBViaWdfAuuV3gVCQiMB3rBg0skWkT97tNk=; b=Pg+WG0q2dJjQz80x9f32z3KLVkUnkpyDQEJtspeigPHNG8VPTQ+AmYcEghRZL7FSWHTy8O+GgC8sTwjt0BESQmT+/ATFOVd4J845ZNoGZtRDttvntSpQ2f/gtH4tx0hcRDdgTrfk+xJ+v4sSKeVLY1gykbiaVT0fEobVMcoo+Mo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758032967216753.9316959148781; Tue, 16 Sep 2025 07:29:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uyWap-0006Gi-HX; Tue, 16 Sep 2025 10:23:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uyWaP-0005qA-PX for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:23:15 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uyWaE-0008Mg-FQ for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:23:11 -0400 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-2445826fd9dso65604575ad.3 for ; Tue, 16 Sep 2025 07:23:00 -0700 (PDT) Received: from stoup.. ([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2651d2df15esm73459905ad.45.2025.09.16.07.22.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 07:22:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758032580; x=1758637380; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jRgfGoWkJBViaWdfAuuV3gVCQiMB3rBg0skWkT97tNk=; b=tQByyXcTa7IKRSB8ZWM4+ZTk2/esMRKDZ8zBS9Q3LL1D0SeuuSkC/yhdtEFR4190dp DFsE1LzHCmC+2bdx9umrsvjmbbh9g5o/yDinq0ytzGQioEcdCxnpJQU7Nk6ORkINxc6A kZgtMi0eEgjaeIK2slbvyCjwpmcTl+uW0bBM2IGu8W7711YZUKvDS9dWBiI+QYpxBDo2 MEgkhDRFyTtWyq+mRSpg/NGMBuJXxbpruzjeth8TcQIlhxwqIhhWazU01W6Ljje7dsja KRxCUZxWwIvt2ac/Zah6GyPAZ8pX7m1Pev64X3xyUPiHwa2MPkipLjU1JezsKjAQB1nF e2ww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758032580; x=1758637380; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jRgfGoWkJBViaWdfAuuV3gVCQiMB3rBg0skWkT97tNk=; b=eqU9usU58ruPQdTeqegPAcKxkJEyPiNwzxw6yaEAQgwAM0cr3Fkn0gjYAbGL46lkCp okzKcj+sKuJGb6/vEVSKjh7RnPSgkOcopA2K+b2MpsF1uUxLwMYqMkGsefw0zow8bMha jOj3KcJXcg6DFKBE40rxUysNzqeRCd4bRoKcY1c7xdgWcfMPmEsdPVjeLuJy5G+jxCnV u7kruBoin/G7/HlRlYWCxqhKHN05mDU5p3UwqXNJCUNT0YeuSwANOdhZfQx/yh1EhFTx ksZE+jvA+Pxhxu+UrHnKTPzI15CZdfYFnPwBEkG8IcXg6akcRLSwTI7lp3YVltf/ME1o u/HA== X-Gm-Message-State: AOJu0YyqZEbxXgmVuRdqMfZwXMWClwPJWcojoU4+0OSGiLuAFFg+h7Q5 PslE2UKbeMSIGAyFwSpAJuCcCuV1c18Cjw7xRSxPO6H8s8awIPVAzHTGAnbw0qmjo+GYU1Bi7pU Pwdk6 X-Gm-Gg: ASbGnctuipVFWGJJbyLNlOYfvSUFODR0K0lB+FzJmpq8tc6MvhmsUo1jxrlPONi/LWz 8pn8toWPmcwhHbn706yao9alHv7RMG6GKi1xANe3mw+JJu/ruc2pf0k2EuFaYeYRloQJk7zRbVO mwlT80ZmI0lVJ2qZJxTg9kredkV1VRjvWQyp7yLeQ0y7p9zcqKMoNkAf1SoQD51KiZPARIm5/Q1 kaIB9vFWt9Aqn2CUcWTFDlk7WucY0spYXX5VzdGRwoQipwWpMAU7RFP/r1J1iZboDmC7ElbBVHk vLTpePBnAOokAWI3DqeepNu7IqiZFAn931xMNnMjyN7LCwqUCtTFasTbKaDRyIcq5fWhHrGOCNl rVKEwXAoBfnqLRm/HnhMOOEpoaurH X-Google-Smtp-Source: AGHT+IEKg8RBNQVZfjsGxxqrsTnQ/ZBF4bXbkMjZ2HndW1XegnOq6B70B5k+pKzbPOExU5yiP7nkGQ== X-Received: by 2002:a17:902:d2cf:b0:266:e0e6:873e with SMTP id d9443c01a7336-266e0e68a56mr103540915ad.57.1758032579582; Tue, 16 Sep 2025 07:22:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v2 26/36] target/arm: Hoist the allocation of ARMCPRegInfo Date: Tue, 16 Sep 2025 07:22:27 -0700 Message-ID: <20250916142238.664316-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916142238.664316-1-richard.henderson@linaro.org> References: <20250916142238.664316-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758032968261116600 Content-Type: text/plain; charset="utf-8" Pass in a newly allocated structure, rather than having to dance around allocation of the name and the structure. Since we no longer have two copies of the structure handy within add_cpreg_to_hashtable, delay the writeback of concrete values over wildcards until we're done querying the wildcards. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/helper.c | 97 ++++++++++++++++++++++----------------------- 1 file changed, 48 insertions(+), 49 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7f55ea726d..71dd094fac 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7443,13 +7443,12 @@ static ARMCPRegInfo *alloc_cpreg(const ARMCPRegInfo= *in, * Private utility function for define_one_arm_cp_reg(): * add a single reginfo struct to the hash table. */ -static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, +static void add_cpreg_to_hashtable(ARMCPU *cpu, ARMCPRegInfo *r, CPState state, CPSecureState secstate, int cp, int crm, int opc1, int opc2, - const char *name, uint32_t key) + uint32_t key) { CPUARMState *env =3D &cpu->env; - ARMCPRegInfo *r2; bool ns =3D secstate & ARM_CP_SECSTATE_NS; =20 /* Overriding of an existing definition must be explicitly requested. = */ @@ -7460,19 +7459,6 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons= t ARMCPRegInfo *r, } } =20 - r2 =3D alloc_cpreg(r, name, NULL); - - /* - * Update fields to match the instantiation, overwiting wildcards - * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH. - */ - r2->cp =3D cp; - r2->crm =3D crm; - r2->opc1 =3D opc1; - r2->opc2 =3D opc2; - r2->state =3D state; - r2->secure =3D secstate; - { bool isbanked =3D r->bank_fieldoffsets[0] && r->bank_fieldoffsets[= 1]; =20 @@ -7482,7 +7468,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, * Overwriting fieldoffset as the array is only used to define * banked registers but later only fieldoffset is used. */ - r2->fieldoffset =3D r->bank_fieldoffsets[ns]; + r->fieldoffset =3D r->bank_fieldoffsets[ns]; } if (state =3D=3D ARM_CP_STATE_AA32) { if (isbanked) { @@ -7499,19 +7485,19 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, con= st ARMCPRegInfo *r, */ if ((r->state =3D=3D ARM_CP_STATE_BOTH && ns) || (arm_feature(env, ARM_FEATURE_V8) && !ns)) { - r2->type |=3D ARM_CP_ALIAS; + r->type |=3D ARM_CP_ALIAS; } } else if ((secstate !=3D r->secure) && !ns) { /* * The register is not banked so we only want to allow * migration of the non-secure instance. */ - r2->type |=3D ARM_CP_ALIAS; + r->type |=3D ARM_CP_ALIAS; } =20 if (HOST_BIG_ENDIAN && - r->state =3D=3D ARM_CP_STATE_BOTH && r2->fieldoffset) { - r2->fieldoffset +=3D sizeof(uint32_t); + r->state =3D=3D ARM_CP_STATE_BOTH && r->fieldoffset) { + r->fieldoffset +=3D sizeof(uint32_t); } } } @@ -7523,35 +7509,46 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, con= st ARMCPRegInfo *r, * multiple times. Special registers (ie NOP/WFI) are * never migratable and not even raw-accessible. */ - if (r2->type & ARM_CP_SPECIAL_MASK) { - r2->type |=3D ARM_CP_NO_RAW; + if (r->type & ARM_CP_SPECIAL_MASK) { + r->type |=3D ARM_CP_NO_RAW; } if (((r->crm =3D=3D CP_ANY) && crm !=3D 0) || ((r->opc1 =3D=3D CP_ANY) && opc1 !=3D 0) || ((r->opc2 =3D=3D CP_ANY) && opc2 !=3D 0)) { - r2->type |=3D ARM_CP_ALIAS | ARM_CP_NO_GDB; + r->type |=3D ARM_CP_ALIAS | ARM_CP_NO_GDB; } =20 + /* + * Update fields to match the instantiation, overwiting wildcards + * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH. + */ + r->cp =3D cp; + r->crm =3D crm; + r->opc1 =3D opc1; + r->opc2 =3D opc2; + r->state =3D state; + r->secure =3D secstate; + /* * Check that raw accesses are either forbidden or handled. Note that * we can't assert this earlier because the setup of fieldoffset for * banked registers has to be done first. */ - if (!(r2->type & ARM_CP_NO_RAW)) { - assert(!raw_accessors_invalid(r2)); + if (!(r->type & ARM_CP_NO_RAW)) { + assert(!raw_accessors_invalid(r)); } =20 - g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2); + g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r); } =20 -static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, const ARMCPRegInfo *r, +static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, ARMCPRegInfo *r, int cp, int crm, int opc1, int opc= 2) { /* * Under AArch32 CP registers can be common * (same for secure and non-secure world) or banked. */ - char *name; + ARMCPRegInfo *r_s; bool is64 =3D r->type & ARM_CP_64BIT; uint32_t key =3D ENCODE_CP_REG(cp, is64, 0, r->crn, crm, opc1, opc2); =20 @@ -7563,24 +7560,23 @@ static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu= , const ARMCPRegInfo *r, /* fall through */ case ARM_CP_SECSTATE_S: add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, r->secure, - cp, crm, opc1, opc2, r->name, key); + cp, crm, opc1, opc2, key); break; case ARM_CP_SECSTATE_BOTH: - name =3D g_strdup_printf("%s_S", r->name); - add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, ARM_CP_SECSTATE_= S, - cp, crm, opc1, opc2, name, key); - g_free(name); + r_s =3D alloc_cpreg(r, r->name, "_S"); + add_cpreg_to_hashtable(cpu, r_s, ARM_CP_STATE_AA32, ARM_CP_SECSTAT= E_S, + cp, crm, opc1, opc2, key); =20 key |=3D CP_REG_AA32_NS_MASK; add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, ARM_CP_SECSTATE_= NS, - cp, crm, opc1, opc2, r->name, key); + cp, crm, opc1, opc2, key); break; default: g_assert_not_reached(); } } =20 -static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu, const ARMCPRegInfo *r, +static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu, ARMCPRegInfo *r, int crm, int opc1, int opc2) { uint32_t key =3D ENCODE_AA64_CP_REG(r->opc0, opc1, r->crn, crm, opc2); @@ -7597,24 +7593,23 @@ static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu= , const ARMCPRegInfo *r, * and name that it is passed, so it's OK to use * a local struct here. */ - ARMCPRegInfo nxs_ri =3D *r; - g_autofree char *name =3D g_strdup_printf("%sNXS", r->name); + ARMCPRegInfo *nxs_ri =3D alloc_cpreg(r, r->name, "NXS"); uint32_t nxs_key; =20 - assert(nxs_ri.crn < 0xf); - nxs_ri.crn++; + assert(nxs_ri->crn < 0xf); + nxs_ri->crn++; nxs_key =3D key + (1 << CP_REG_ARM64_SYSREG_CRN_SHIFT); - if (nxs_ri.fgt) { - nxs_ri.fgt |=3D R_FGT_NXS_MASK; + if (nxs_ri->fgt) { + nxs_ri->fgt |=3D R_FGT_NXS_MASK; } =20 - add_cpreg_to_hashtable(cpu, &nxs_ri, ARM_CP_STATE_AA64, + add_cpreg_to_hashtable(cpu, nxs_ri, ARM_CP_STATE_AA64, ARM_CP_SECSTATE_NS, 0, crm, opc1, opc2, - name, nxs_key); + nxs_key); } =20 add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA64, ARM_CP_SECSTATE_NS, - 0, crm, opc1, opc2, r->name, key); + 0, crm, opc1, opc2, key); } =20 void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r) @@ -7821,16 +7816,20 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCP= RegInfo *r) for (int crm =3D crmmin; crm <=3D crmmax; crm++) { for (int opc1 =3D opc1min; opc1 <=3D opc1max; opc1++) { for (int opc2 =3D opc2min; opc2 <=3D opc2max; opc2++) { + ARMCPRegInfo *r2 =3D alloc_cpreg(r, r->name, NULL); + ARMCPRegInfo *r3; + switch (r->state) { case ARM_CP_STATE_AA32: - add_cpreg_to_hashtable_aa32(cpu, r, cp, crm, opc1, opc= 2); + add_cpreg_to_hashtable_aa32(cpu, r2, cp, crm, opc1, op= c2); break; case ARM_CP_STATE_AA64: - add_cpreg_to_hashtable_aa64(cpu, r, crm, opc1, opc2); + add_cpreg_to_hashtable_aa64(cpu, r2, crm, opc1, opc2); break; case ARM_CP_STATE_BOTH: - add_cpreg_to_hashtable_aa32(cpu, r, cp, crm, opc1, opc= 2); - add_cpreg_to_hashtable_aa64(cpu, r, crm, opc1, opc2); + r3 =3D alloc_cpreg(r2, r2->name, NULL); + add_cpreg_to_hashtable_aa32(cpu, r2, cp, crm, opc1, op= c2); + add_cpreg_to_hashtable_aa64(cpu, r3, crm, opc1, opc2); break; default: g_assert_not_reached(); --=20 2.43.0 From nobody Sun Sep 28 16:37:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 71dd094fac..da3dd073d3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7421,9 +7421,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) * Copy a ARMCPRegInfo structure, allocating it along with the name * and an optional suffix to the name. */ -static ARMCPRegInfo *alloc_cpreg(const ARMCPRegInfo *in, - const char *name, const char *suffix) +static ARMCPRegInfo *alloc_cpreg(const ARMCPRegInfo *in, const char *suffi= x) { + const char *name =3D in->name; size_t name_len =3D strlen(name); size_t suff_len =3D suffix ? strlen(suffix) : 0; ARMCPRegInfo *out =3D g_malloc(sizeof(*in) + name_len + suff_len + 1); @@ -7563,7 +7563,7 @@ static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, = ARMCPRegInfo *r, cp, crm, opc1, opc2, key); break; case ARM_CP_SECSTATE_BOTH: - r_s =3D alloc_cpreg(r, r->name, "_S"); + r_s =3D alloc_cpreg(r, "_S"); add_cpreg_to_hashtable(cpu, r_s, ARM_CP_STATE_AA32, ARM_CP_SECSTAT= E_S, cp, crm, opc1, opc2, key); =20 @@ -7593,7 +7593,7 @@ static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu, = ARMCPRegInfo *r, * and name that it is passed, so it's OK to use * a local struct here. */ - ARMCPRegInfo *nxs_ri =3D alloc_cpreg(r, r->name, "NXS"); + ARMCPRegInfo *nxs_ri =3D alloc_cpreg(r, "NXS"); uint32_t nxs_key; =20 assert(nxs_ri->crn < 0xf); @@ -7816,7 +7816,7 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRe= gInfo *r) for (int crm =3D crmmin; crm <=3D crmmax; crm++) { for (int opc1 =3D opc1min; opc1 <=3D opc1max; opc1++) { for (int opc2 =3D opc2min; opc2 <=3D opc2max; opc2++) { - ARMCPRegInfo *r2 =3D alloc_cpreg(r, r->name, NULL); + ARMCPRegInfo *r2 =3D alloc_cpreg(r, NULL); ARMCPRegInfo *r3; =20 switch (r->state) { @@ -7827,7 +7827,7 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRe= gInfo *r) add_cpreg_to_hashtable_aa64(cpu, r2, crm, opc1, opc2); break; case ARM_CP_STATE_BOTH: - r3 =3D alloc_cpreg(r2, r2->name, NULL); + r3 =3D alloc_cpreg(r2, NULL); add_cpreg_to_hashtable_aa32(cpu, r2, cp, crm, opc1, op= c2); add_cpreg_to_hashtable_aa64(cpu, r3, crm, opc1, opc2); break; --=20 2.43.0 From nobody Sun Sep 28 16:37:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758032871; cv=none; d=zohomail.com; s=zohoarc; b=HovAKUWNwA7zZzWfd7co7ejl/JeWz73yWlsWuRhRE/SHpYx6ooNSH1kAl3+LiP27AnpNY8geu4Rij7DEjcPxWgLOngPVTuK6PgQ4Rh3DJOB9CGS4W8XbQkyl0QR+4eCovhFJL3jj16mGSLmlNNhCtoUvbqAp7S6masNkPgNER6Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758032871; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=iFvrkXppk9qW3dQaIUV7du/mSWSAFGQyLCbJPSszGi0=; b=n78vopTCR/75EtFWXyhImX/C+yZnG+DDZTQXOWIoxkxpQPsApVmdUb5Nlglgd0NXfkCj8QQmJanRWaILB4vj+Ju7DURqtR4JA/T3pqheXIiLkHuht96vL7qM5SjY+LB8WtzvhBdU7KNJJa4H0aGRWpKH/OdE8b3bjzytZNhC/yY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758032871448719.0892871571114; Tue, 16 Sep 2025 07:27:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uyWcN-0007RH-Gb; Tue, 16 Sep 2025 10:25:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uyWab-0005y7-02 for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:23:25 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uyWaT-0008NR-Pv for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:23:24 -0400 Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-24457f581aeso55563405ad.0 for ; Tue, 16 Sep 2025 07:23:03 -0700 (PDT) Received: from stoup.. ([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2651d2df15esm73459905ad.45.2025.09.16.07.23.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 07:23:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758032582; x=1758637382; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iFvrkXppk9qW3dQaIUV7du/mSWSAFGQyLCbJPSszGi0=; b=ohax2Rt6HfKUrn8WG4X3m38AO+JFqe5yl2w6a016T+LDQ7oTZ6PTu360TzBrwqRXZG cgiynJHsVeco8jWrXs1g9dvf0o3j13E5jm5hlXXva9dK2TR5LYEHHYdW4FmkxtgaiKVd oR1W7tZzRj7H6xW9rp1UTEylSSXZDrBZSCmfIkA0NUggSEy05pPtqEwRHqOnagKiNSXa jp/dbrR/NF8IkWZz8N291g3iNmx/C/cLHbM/QwGbI5sFPM0/IFH6uFJXizA5SLAdDR3E 89a+006JKVcCsAnr/k1tp/vFa9NrzcBShJFeAeRcqA6A9EsOfvB3K31DakrNUNjaCe4x Owtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758032582; x=1758637382; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iFvrkXppk9qW3dQaIUV7du/mSWSAFGQyLCbJPSszGi0=; b=oeDsF7EHg6cHJS7mflbXArJ9J26MXFUEcLYBJNGcbWpd2HWzVHPF76nBTeutvyt86F tefWTVipNB/aULPc/MA5AFAGOfx5RnszNUi19elboXqzQ04235JRilKSf8fsTuRvoV7N lEc3v+QvvLCWmVTX0I6FzYvpWETz2EPx8MFzovsBBzPGaHI4RnT027HnmiOcyKVXZsM7 U5tCJobo1NiZNOobOShH/WPDFvvZpm8qrN6uF9U/ElvPbeR3DzdeZgtfKT/Tl3zLMHb8 5BAwPUNul6Xx36+j85LujF69/WfmKNrfXci8F2OdrVYvgh2SXan4EFZBBuNVFCGhR5/v 462g== X-Gm-Message-State: AOJu0Yyq9wZVGtUchao0AsCNSYkIf3vOmOnZQB9NULzyGSDplUguN38l l4/WB7vJ68vINp9M6MNLRNl4i5qIkRdXcnqXF5Aq/folCgqIZUL8j9dRXVXsmsgEBlqF5WnxyfC QG+FE X-Gm-Gg: ASbGncvHs1pKVGKQwWFEhoLPBQb100QSfuPbIrWBLPYwNe12jhaHxLfNqg4YYee0YJV g3MG/GFkUf1B8zh/r0zRdkmHa4IACd9DwpSbdVsVDCv9XM6xNyLluzdxqiCXaMuheOJuO5pwPBM yb7rzVm9yjjLwwd72XXhyZD4xePCVpcoeo/yMV8uTF80ANXN9WuUDT2Vq9LEY0xIFdIV+fZflzB 4w7eKJRtEp693o9N7dvOByOwLrpON9pMfGCeH6OfoSpqMlmmffXX+j1GWME2lUCWHXyANIjXnZd StU/jM/7WLs/or/HRFgRDeIMJHuDGBkAef54MLrmd+QrfZsuhSPIDOWoQBZN063vmL72kKT2zmg rwupEn8WAipQoyo+UMYKXqvcItUJb X-Google-Smtp-Source: AGHT+IETPo01soMbT7PfDX618eaXGP3wwZ6+IeqFVDMBk3dznVd9SPlYZYu/Vk+THaw6tnB/li8UvA== X-Received: by 2002:a17:903:8c3:b0:260:c48c:3fba with SMTP id d9443c01a7336-260c48c4123mr148767645ad.47.1758032582027; Tue, 16 Sep 2025 07:23:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v2 28/36] target/arm: Move alias setting for wildcards Date: Tue, 16 Sep 2025 07:22:29 -0700 Message-ID: <20250916142238.664316-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916142238.664316-1-richard.henderson@linaro.org> References: <20250916142238.664316-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758032872518116600 Content-Type: text/plain; charset="utf-8" Move this test from add_cpreg_to_hashtable to define_one_arm_cp_reg_with_opaque, where we can also simplify it based on the loop variables. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/helper.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index da3dd073d3..9156cc72ae 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7503,20 +7503,12 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, ARM= CPRegInfo *r, } =20 /* - * By convention, for wildcarded registers only the first - * entry is used for migration; the others are marked as - * ALIAS so we don't try to transfer the register - * multiple times. Special registers (ie NOP/WFI) are - * never migratable and not even raw-accessible. + * Special registers (ie NOP/WFI) are never migratable and + * are not even raw-accessible. */ if (r->type & ARM_CP_SPECIAL_MASK) { r->type |=3D ARM_CP_NO_RAW; } - if (((r->crm =3D=3D CP_ANY) && crm !=3D 0) || - ((r->opc1 =3D=3D CP_ANY) && opc1 !=3D 0) || - ((r->opc2 =3D=3D CP_ANY) && opc2 !=3D 0)) { - r->type |=3D ARM_CP_ALIAS | ARM_CP_NO_GDB; - } =20 /* * Update fields to match the instantiation, overwiting wildcards @@ -7819,6 +7811,16 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPR= egInfo *r) ARMCPRegInfo *r2 =3D alloc_cpreg(r, NULL); ARMCPRegInfo *r3; =20 + /* + * By convention for wildcarded registers, only the first + * entry is used for migration; the others are marked as + * ALIAS so we don't try to transfer the register + * multiple times. + */ + if (crm !=3D crmmin || opc1 !=3D opc1min || opc2 !=3D opc2= min) { + r2->type |=3D ARM_CP_ALIAS | ARM_CP_NO_GDB; + } + switch (r->state) { case ARM_CP_STATE_AA32: add_cpreg_to_hashtable_aa32(cpu, r2, cp, crm, opc1, op= c2); --=20 2.43.0 From nobody Sun Sep 28 16:37:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758032738; cv=none; d=zohomail.com; s=zohoarc; b=ODqUqv3E/WrhoBUgaIGf5oVavVJixTmAE2dauMNbMKNsjqP03YgCOi/h5w7ukxDdmk4taLKGP9s2Qz06UVoGwf/Vm1l62dJ9hBiVoSQXWGv3Q72hAaXlvNUqhCJlnQQgTG1SRC5jC1Zfxt78yMSnSwcGdjAxUf6KvsRh/xqwMDg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758032738; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=QTfmC+EHekiKULjrHnOchac3Nz1KC9/zPXCI44LaJl4=; b=RyW/EJwXBYfQfV8rQ5Z8KplQoM9xcAaxaYAg49mvWi1TB1vOih3uYvLBARScON5BzF6vttPPIxDxjJ8xh04BqM3w54k2719Rx6RuDnfEnjop6/jPYmulM5M4WjdSs3Jl00OwNT0UZjm2AzImwU89QU2kBQhjW+8vE19J625L4dQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758032738088918.3867969803287; Tue, 16 Sep 2025 07:25:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uyWbl-00071y-Pt; Tue, 16 Sep 2025 10:24:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uyWam-0006BF-VT for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:23:37 -0400 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uyWaU-0008NX-R2 for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:23:31 -0400 Received: by mail-pg1-x529.google.com with SMTP id 41be03b00d2f7-b4c1fc383eeso3710086a12.1 for ; Tue, 16 Sep 2025 07:23:03 -0700 (PDT) Received: from stoup.. ([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2651d2df15esm73459905ad.45.2025.09.16.07.23.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 07:23:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758032583; x=1758637383; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QTfmC+EHekiKULjrHnOchac3Nz1KC9/zPXCI44LaJl4=; b=NyBM7xnzjlWYrZyN8EtPAWgSfXIfFFw9jPegaC+tFCyLJslIXOCFeD59/5pyeh/aTq sxfhpaaUf4Dtb0S6FQzbK794IxVhdZWG2Z7JWsDWdq6YCBmzcnE+yeHGHMra8sVsLzL9 W4fUD7AJ03SsC6kS6/1Mugmo1GMvHGFThih79aje5mKGzUd0maU7FwR3/SJImtzGXzhl 44Ti7U1ouYDZdBqZoIiPDQ/xH8O9k7NHF84TFuJH7NQpVnDKSU2D6MvW3WmxDzhYFbS0 vrudnC8yz4OpZ4nwK9dARZceexVnLBSTAmHTcBB3reEgesKJPb6IboyUHY9bUEp90eUl Z4zA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758032583; x=1758637383; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QTfmC+EHekiKULjrHnOchac3Nz1KC9/zPXCI44LaJl4=; b=J7FLazMia4uBJul7ZisR1FWQHProFPB4EAYM/A+f39YBZ6kbdjiKCoTX+nUgp9na7b melkPkBZKAFgy72YhwhqD5wkI0Zp0im5rAIDbOavCev8WAkH+sctspx0BzX/GvTEOemp nAotm6eRpuCQJIdU55YWVuHrh/OTVddT/cDiXpDiV7qGUDp4ugJ1tEudnHykhNDXOTWB glXCaV6riUobfmnpVtZoJzBaa6tcOyDkixMlci5zQ2yTESJuuvN31vxDT9Lu3tQl9p9x xdCummPdVZ99xoLOJeE0HPAnAmd7cLuxqcnRQWc7zPXyjG9cMVX3gtBlyXvH6Z78aw85 K/0Q== X-Gm-Message-State: AOJu0YygrdbDJjowveJY9ieel0+de56RLopyJUTpvd7whThWNASJt5Da 38qKLbh5gW+3Ek6wun6bOsLDTvgg76IbBgNSFWhO90m60fmh2ixgnGfiaNHuwn4CV5Wz0M6m0ou saWod X-Gm-Gg: ASbGnct3N/5WedOSdlwLTHwyJzPTqBD5WodvU+vjvDJ5Xaw7eKQbo5qciCcTxq5ZXsa PKpmoah7x3Ko5GeFnf6+teis3xdOpcK8/2pLUe1hUuI8aW+mSneoUfPDyE+/xJAa104wZsKSwDJ rwhi9Z5UY2tgai+dBoeFk9OSf8LYTZ/LTtNtK8qROVTAeM0nnziSfrWBGx9fyP7ucLZVHCTQB5J 1ImMb30iUI7m0P9ZTM0qWAvaBNKRWn6vPkCHngoQVvSzANQhQ2Lhbb8tyhkrn2dZ8rNN41jQjlH 1ZCcQ3HSUL+3kzaekDDjAxQD8XcfRnTy8zlL0Kpcd4lvebiJPf1htWME4KrrRFsjQ7cauFBkdL8 no0/ErmYakk82MNJVEIAylMgPc/dG X-Google-Smtp-Source: AGHT+IFoERqKLyR1iYNDsGk5975Zt3MbltqsNVAb58sthGhtAxJnbGzlFE9tryDQKZdTPbXnl4H4hw== X-Received: by 2002:a17:903:3c30:b0:24d:7314:fe64 with SMTP id d9443c01a7336-25d27828f01mr229384205ad.57.1758032582606; Tue, 16 Sep 2025 07:23:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v2 29/36] target/arm: Move writeback of CP_ANY fields Date: Tue, 16 Sep 2025 07:22:30 -0700 Message-ID: <20250916142238.664316-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916142238.664316-1-richard.henderson@linaro.org> References: <20250916142238.664316-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758032739273116600 Content-Type: text/plain; charset="utf-8" Move the writeback of cp, crm, opc1, opc2 to define_one_arm_cp_reg, which means we don't have to pass all those parameters down to subroutines. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/helper.c | 52 ++++++++++++++++++++++----------------------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 9156cc72ae..7828268c7f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7445,7 +7445,6 @@ static ARMCPRegInfo *alloc_cpreg(const ARMCPRegInfo *= in, const char *suffix) */ static void add_cpreg_to_hashtable(ARMCPU *cpu, ARMCPRegInfo *r, CPState state, CPSecureState secstate, - int cp, int crm, int opc1, int opc2, uint32_t key) { CPUARMState *env =3D &cpu->env; @@ -7512,12 +7511,8 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, ARMC= PRegInfo *r, =20 /* * Update fields to match the instantiation, overwiting wildcards - * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH. + * such as ARM_CP_STATE_BOTH or ARM_CP_SECSTATE_BOTH. */ - r->cp =3D cp; - r->crm =3D crm; - r->opc1 =3D opc1; - r->opc2 =3D opc2; r->state =3D state; r->secure =3D secstate; =20 @@ -7533,8 +7528,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, ARMCP= RegInfo *r, g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r); } =20 -static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, ARMCPRegInfo *r, - int cp, int crm, int opc1, int opc= 2) +static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, ARMCPRegInfo *r) { /* * Under AArch32 CP registers can be common @@ -7542,7 +7536,8 @@ static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, = ARMCPRegInfo *r, */ ARMCPRegInfo *r_s; bool is64 =3D r->type & ARM_CP_64BIT; - uint32_t key =3D ENCODE_CP_REG(cp, is64, 0, r->crn, crm, opc1, opc2); + uint32_t key =3D ENCODE_CP_REG(r->cp, is64, 0, r->crn, + r->crm, r->opc1, r->opc2); =20 assert(!(r->type & ARM_CP_ADD_TLBI_NXS)); /* aa64 only */ =20 @@ -7551,27 +7546,26 @@ static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu= , ARMCPRegInfo *r, key |=3D CP_REG_AA32_NS_MASK; /* fall through */ case ARM_CP_SECSTATE_S: - add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, r->secure, - cp, crm, opc1, opc2, key); + add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, r->secure, key); break; case ARM_CP_SECSTATE_BOTH: r_s =3D alloc_cpreg(r, "_S"); - add_cpreg_to_hashtable(cpu, r_s, ARM_CP_STATE_AA32, ARM_CP_SECSTAT= E_S, - cp, crm, opc1, opc2, key); + add_cpreg_to_hashtable(cpu, r_s, ARM_CP_STATE_AA32, + ARM_CP_SECSTATE_S, key); =20 key |=3D CP_REG_AA32_NS_MASK; - add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, ARM_CP_SECSTATE_= NS, - cp, crm, opc1, opc2, key); + add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, + ARM_CP_SECSTATE_NS, key); break; default: g_assert_not_reached(); } } =20 -static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu, ARMCPRegInfo *r, - int crm, int opc1, int opc2) +static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu, ARMCPRegInfo *r) { - uint32_t key =3D ENCODE_AA64_CP_REG(r->opc0, opc1, r->crn, crm, opc2); + uint32_t key =3D ENCODE_AA64_CP_REG(r->opc0, r->opc1, + r->crn, r->crm, r->opc2); =20 if ((r->type & ARM_CP_ADD_TLBI_NXS) && cpu_isar_feature(aa64_xs, cpu)) { @@ -7596,12 +7590,11 @@ static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu= , ARMCPRegInfo *r, } =20 add_cpreg_to_hashtable(cpu, nxs_ri, ARM_CP_STATE_AA64, - ARM_CP_SECSTATE_NS, 0, crm, opc1, opc2, - nxs_key); + ARM_CP_SECSTATE_NS, nxs_key); } =20 - add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA64, ARM_CP_SECSTATE_NS, - 0, crm, opc1, opc2, key); + add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA64, + ARM_CP_SECSTATE_NS, key); } =20 void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r) @@ -7821,17 +7814,24 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCP= RegInfo *r) r2->type |=3D ARM_CP_ALIAS | ARM_CP_NO_GDB; } =20 + /* Overwrite CP_ANY with the instantiation. */ + r2->crm =3D crm; + r2->opc1 =3D opc1; + r2->opc2 =3D opc2; + switch (r->state) { case ARM_CP_STATE_AA32: - add_cpreg_to_hashtable_aa32(cpu, r2, cp, crm, opc1, op= c2); + add_cpreg_to_hashtable_aa32(cpu, r2); break; case ARM_CP_STATE_AA64: - add_cpreg_to_hashtable_aa64(cpu, r2, crm, opc1, opc2); + add_cpreg_to_hashtable_aa64(cpu, r2); break; case ARM_CP_STATE_BOTH: r3 =3D alloc_cpreg(r2, NULL); - add_cpreg_to_hashtable_aa32(cpu, r2, cp, crm, opc1, op= c2); - add_cpreg_to_hashtable_aa64(cpu, r3, crm, opc1, opc2); + r2->cp =3D cp; + add_cpreg_to_hashtable_aa32(cpu, r2); + r3->cp =3D 0; + add_cpreg_to_hashtable_aa64(cpu, r3); break; default: g_assert_not_reached(); --=20 2.43.0 From nobody Sun Sep 28 16:37:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758032726; cv=none; d=zohomail.com; s=zohoarc; b=YnFESCcRyIyIVv09isUWW/Kcar4hLKIkCVHc6uCQWwS9t2UuO4iXV5LkkQ2G4lfs+OroOC/ifAits3tjvxNVr/gHpYH2Lq1yp+vB2/mXwu2bwuzUCVqPKHON87PjFtWtL3AjSIXsDB7oScVQ7E23Zx0WYnjm9UmrOyrEnkTHh5c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758032726; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/helper.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7828268c7f..0f681c15e0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7493,14 +7493,21 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, ARM= CPRegInfo *r, */ r->type |=3D ARM_CP_ALIAS; } - - if (HOST_BIG_ENDIAN && - r->state =3D=3D ARM_CP_STATE_BOTH && r->fieldoffset) { - r->fieldoffset +=3D sizeof(uint32_t); - } } } =20 + /* + * For 32-bit AArch32 regs shared with 64-bit AArch64 regs, + * adjust the field offset for endianness. This had to be + * delayed until banked registers were resolved. + */ + if (HOST_BIG_ENDIAN && + state =3D=3D ARM_CP_STATE_AA32 && + r->state =3D=3D ARM_CP_STATE_BOTH && + r->fieldoffset) { + r->fieldoffset +=3D sizeof(uint32_t); + } + /* * Special registers (ie NOP/WFI) are never migratable and * are not even raw-accessible. --=20 2.43.0 From nobody Sun Sep 28 16:37:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758032708; cv=none; d=zohomail.com; s=zohoarc; b=b7Xtl1f5zkKJwY0boSysAurZAe0Rh0pJuEBTcD9AfGYih1C9wzCnKiRzRfqY01W3qlMIH5/TQoNBzhdgBbgTpzGUAoj2uTKJX8nLMGgpid5ljWKb8RkNZZf6TxRTqiyM38L8roO9LMxKjAoDXoRi5cHKIEj2njTGE/drIRcrWq8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758032708; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=RcKPQdIEUX2PNEvjBDHi7h42HjJJAKk2WkX9D2rphHM=; b=ao0YNjk9ivE2mSLkTmRL8qbnwFiMkLQVTedOvGoICgiKay631zordtQhJWLdLDnY+fzIq7mm2ua7kX/Bpe/yQ5m/b+y2k+p7qhl/T1HzJsmPeDwHLqJf5LCnVeIYUnm+eMjCbEre71uJfYkiKBVJrTe35bEM9L2c0oqXWEgjQJg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758032708727185.17731053886382; Tue, 16 Sep 2025 07:25:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uyWat-0006O4-EY; Tue, 16 Sep 2025 10:23:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uyWaW-0005uF-MO for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:23:20 -0400 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uyWaP-0008Nw-Gf for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:23:18 -0400 Received: by mail-pg1-x530.google.com with SMTP id 41be03b00d2f7-b523af71683so4503486a12.3 for ; Tue, 16 Sep 2025 07:23:05 -0700 (PDT) Received: from stoup.. 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Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.h | 3 +-- target/arm/tcg/translate.h | 2 ++ target/arm/tcg/hflags.c | 8 +++++--- target/arm/tcg/translate-a64.c | 3 ++- 4 files changed, 10 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c15d79a106..4a22b216b3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3093,8 +3093,7 @@ FIELD(TBFLAG_A64, ATA0, 31, 1) FIELD(TBFLAG_A64, NV, 32, 1) FIELD(TBFLAG_A64, NV1, 33, 1) FIELD(TBFLAG_A64, NV2, 34, 1) -/* Set if FEAT_NV2 RAM accesses use the EL2&0 translation regime */ -FIELD(TBFLAG_A64, NV2_MEM_E20, 35, 1) +FIELD(TBFLAG_A64, E2H, 35, 1) /* Set if FEAT_NV2 RAM accesses are big-endian */ FIELD(TBFLAG_A64, NV2_MEM_BE, 36, 1) FIELD(TBFLAG_A64, AH, 37, 1) /* FPCR.AH */ diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index f974996f3f..cd67c0ed07 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -150,6 +150,8 @@ typedef struct DisasContext { bool trap_eret; /* True if FEAT_LSE2 SCTLR_ELx.nAA is set */ bool naa; + /* True if HCR_EL2.E2H is set */ + bool e2h; /* True if FEAT_NV HCR_EL2.NV is enabled */ bool nv; /* True if NV enabled and HCR_EL2.NV1 is set */ diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index 59ab526375..6969d41ea0 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -258,6 +258,11 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *e= nv, int el, int fp_el, DP_TBFLAG_A64(flags, TBII, tbii); DP_TBFLAG_A64(flags, TBID, tbid); =20 + /* E2H is used by both VHE and NV2. */ + if (hcr & HCR_E2H) { + DP_TBFLAG_A64(flags, E2H, 1); + } + if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { int sve_el =3D sve_exception_el(env, el); =20 @@ -390,9 +395,6 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *en= v, int el, int fp_el, } if (hcr & HCR_NV2) { DP_TBFLAG_A64(flags, NV2, 1); - if (hcr & HCR_E2H) { - DP_TBFLAG_A64(flags, NV2_MEM_E20, 1); - } if (env->cp15.sctlr_el[2] & SCTLR_EE) { DP_TBFLAG_A64(flags, NV2_MEM_BE, 1); } diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 0ec309f1ea..599e7a36ee 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -10304,10 +10304,11 @@ static void aarch64_tr_init_disas_context(DisasCo= ntextBase *dcbase, dc->pstate_za =3D EX_TBFLAG_A64(tb_flags, PSTATE_ZA); dc->sme_trap_nonstreaming =3D EX_TBFLAG_A64(tb_flags, SME_TRAP_NONSTRE= AMING); dc->naa =3D EX_TBFLAG_A64(tb_flags, NAA); + dc->e2h =3D EX_TBFLAG_A64(tb_flags, E2H); dc->nv =3D EX_TBFLAG_A64(tb_flags, NV); dc->nv1 =3D EX_TBFLAG_A64(tb_flags, NV1); dc->nv2 =3D EX_TBFLAG_A64(tb_flags, NV2); - dc->nv2_mem_e20 =3D EX_TBFLAG_A64(tb_flags, NV2_MEM_E20); + dc->nv2_mem_e20 =3D dc->nv2 && dc->e2h; dc->nv2_mem_be =3D EX_TBFLAG_A64(tb_flags, NV2_MEM_BE); dc->fpcr_ah =3D EX_TBFLAG_A64(tb_flags, AH); dc->fpcr_nep =3D EX_TBFLAG_A64(tb_flags, NEP); --=20 2.43.0 From nobody Sun Sep 28 16:37:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 16 Sep 2025 07:23:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v2 32/36] target/arm: Split out redirect_cpreg Date: Tue, 16 Sep 2025 07:22:33 -0700 Message-ID: <20250916142238.664316-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916142238.664316-1-richard.henderson@linaro.org> References: <20250916142238.664316-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758033254789116600 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/tcg/translate-a64.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 599e7a36ee..c0fa2137b6 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2455,6 +2455,19 @@ static void gen_sysreg_undef(DisasContext *s, bool i= sread, gen_exception_insn(s, 0, EXCP_UDEF, syndrome); } =20 +/* + * Look up @key, returning the cpreg, which must exist. + * Additionally, the new cpreg must also be accessible. + */ +static const ARMCPRegInfo * +redirect_cpreg(DisasContext *s, uint32_t key, bool isread) +{ + const ARMCPRegInfo *ri =3D get_arm_cp_reginfo(s->cp_regs, key); + assert(ri); + assert(cp_access_ok(s->current_el, ri, isread)); + return ri; +} + /* MRS - move from system register * MSR (register) - move to system register * SYS @@ -2603,9 +2616,7 @@ static void handle_sys(DisasContext *s, bool isread, * fine-grained-traps on EL1 also do not apply here. */ key =3D ENCODE_AA64_CP_REG(op0, 0, crn, crm, op2); - ri =3D get_arm_cp_reginfo(s->cp_regs, key); - assert(ri); - assert(cp_access_ok(s->current_el, ri, isread)); + ri =3D redirect_cpreg(s, key, isread); /* * We might not have done an update_pc earlier, so check we don't * need it. We could support this in future if necessary. --=20 2.43.0 From nobody Sun Sep 28 16:37:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758033317; cv=none; d=zohomail.com; s=zohoarc; b=EF9GQUIdRuVl1/xVHsQOKgY9LmDi8362Lhg+FgYeJyNarRjhRrAuJi/CCZiYggNIt3kITHUfI+qg0woCq1ukVNJDUvhW1EvgdwcFz1E3u9QyPlTA8ke0/X3Z6lfMmRHa9lzzfOfPCHexctrJoEnTKEIDF2/I8qsjli6a7LEK7c0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758033317; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=wb3ffh10yt9XUqD1An7QFUP22NN64A7VcTxbgqStNMo=; b=lwj2Nji+pnZ4Q6C18wvo0h+Jj7U2A/o9JBWgovd6HU24tMaN+lERyDf9SJmJ+WppSFDXBCXu9MtM6qQZNaI3yKbMtUWe8yidxebLGQQUlu0qR+GZxQq+CjHjuwg3gVRNmDosNIqjF6FtX9uzMTtQ0n5CNFQSSjzm9t7DgVi93wY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758033317542475.99104809814787; Tue, 16 Sep 2025 07:35:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uyWcs-0000ND-E1; Tue, 16 Sep 2025 10:25:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uyWaT-0005t3-KN for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:23:18 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uyWaN-0008ON-D4 for qemu-devel@nongnu.org; Tue, 16 Sep 2025 10:23:15 -0400 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-2445806e03cso61708725ad.1 for ; Tue, 16 Sep 2025 07:23:07 -0700 (PDT) Received: from stoup.. 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Tue, 16 Sep 2025 07:23:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, Manos Pitsidianakis Subject: [PATCH v2 33/36] target/arm: Redirect VHE FOO_EL1 -> FOO_EL2 during translation Date: Tue, 16 Sep 2025 07:22:34 -0700 Message-ID: <20250916142238.664316-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916142238.664316-1-richard.henderson@linaro.org> References: <20250916142238.664316-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758033319236116601 Content-Type: text/plain; charset="utf-8" Reviewed-by: Manos Pitsidianakis Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpregs.h | 6 ++++ target/arm/gdbstub.c | 5 ++++ target/arm/helper.c | 53 +--------------------------------- target/arm/tcg/translate-a64.c | 9 ++++++ 4 files changed, 21 insertions(+), 52 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 7bdf6cf847..d34ed0d40b 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -911,6 +911,12 @@ struct ARMCPRegInfo { */ uint32_t nv2_redirect_offset; =20 + /* + * With VHE, with E2H, at EL2, access to this EL0/EL1 reg redirects + * to the EL2 reg with the specified key. + */ + uint32_t vhe_redir_to_el2; + /* This is used only by VHE. */ void *opaque; /* diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index e2fc389170..3727dc01af 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -249,6 +249,11 @@ static int arm_gdb_get_sysreg(CPUState *cs, GByteArray= *buf, int reg) if (ri) { switch (cpreg_field_type(ri)) { case MO_64: + if (ri->vhe_redir_to_el2 && + (arm_hcr_el2_eff(env) & HCR_E2H) && + arm_current_el(env) =3D=3D 2) { + ri =3D get_arm_cp_reginfo(cpu->cp_regs, ri->vhe_redir_to_e= l2); + } return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri)); case MO_32: return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri)); diff --git a/target/arm/helper.c b/target/arm/helper.c index 0f681c15e0..49bb1e8365 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4456,47 +4456,6 @@ static CPAccessResult access_el1nvvct(CPUARMState *e= nv, const ARMCPRegInfo *ri, return e2h_access(env, ri, isread); } =20 -/* Test if system register redirection is to occur in the current state. = */ -static bool redirect_for_e2h(CPUARMState *env) -{ - return arm_current_el(env) =3D=3D 2 && (arm_hcr_el2_eff(env) & HCR_E2H= ); -} - -static uint64_t el2_e2h_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - CPReadFn *readfn; - - if (redirect_for_e2h(env)) { - /* Switch to the saved EL2 version of the register. */ - ri =3D ri->opaque; - readfn =3D ri->readfn; - } else { - readfn =3D ri->orig_readfn; - } - if (readfn =3D=3D NULL) { - readfn =3D raw_read; - } - return readfn(env, ri); -} - -static void el2_e2h_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - CPWriteFn *writefn; - - if (redirect_for_e2h(env)) { - /* Switch to the saved EL2 version of the register. */ - ri =3D ri->opaque; - writefn =3D ri->writefn; - } else { - writefn =3D ri->orig_writefn; - } - if (writefn =3D=3D NULL) { - writefn =3D raw_write; - } - writefn(env, ri, value); -} - static uint64_t el2_e2h_e12_read(CPUARMState *env, const ARMCPRegInfo *ri) { /* Pass the EL1 register accessor its ri, not the EL12 alias ri */ @@ -4676,17 +4635,7 @@ static void define_arm_vh_e2h_redirects_aliases(ARMC= PU *cpu) (gpointer)(uintptr_t)a->new_key, new_reg); g_assert(ok); =20 - src_reg->opaque =3D dst_reg; - src_reg->orig_readfn =3D src_reg->readfn ?: raw_read; - src_reg->orig_writefn =3D src_reg->writefn ?: raw_write; - if (!src_reg->raw_readfn) { - src_reg->raw_readfn =3D raw_read; - } - if (!src_reg->raw_writefn) { - src_reg->raw_writefn =3D raw_write; - } - src_reg->readfn =3D el2_e2h_read; - src_reg->writefn =3D el2_e2h_write; + src_reg->vhe_redir_to_el2 =3D a->dst_key; } } #endif diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index c0fa2137b6..3ef24fb0c3 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2573,6 +2573,15 @@ static void handle_sys(DisasContext *s, bool isread, } } =20 + if (ri->vhe_redir_to_el2 && s->current_el =3D=3D 2 && s->e2h) { + /* + * This one of the FOO_EL1 registers which redirect to FOO_EL2 + * from EL2 when HCR_EL2.E2H is set. + */ + key =3D ri->vhe_redir_to_el2; + ri =3D redirect_cpreg(s, key, isread); + } + if (ri->accessfn || (ri->fgt && s->fgt_active)) { /* Emit code to perform further access permissions checks at * runtime; this may result in an exception. --=20 2.43.0 From nobody Sun Sep 28 16:37:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2651d2df15esm73459905ad.45.2025.09.16.07.23.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 07:23:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758032587; x=1758637387; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AyiB622GUdP8Ps2sW1QaI66OgFpDcJd68CYchnKzFN8=; b=j4ZUVu3auucrlCRrYIp8nTFehpis1L9K05zj9OZXCQFEkfMRqYWpYEUHLpwSlIdk+O BAEuth3VUU5G3QuDhC6yMW+ecW1mRvWhbYJEwU2m4UGNL75/ScameNsTP7pl32T4UegP +SVvgT//Fs8UZzWOfEc3yIpR3OhpJ4/z4GdWsGAjHI8FrFYyO42CAxkDm5icPTa07pMy uXfkYUtWXrpFHtWk5N1cwBnBr8PrhEFaYL3KFthk+DrbrGUrSEsR8mLJl+hhajv4T6dw PWLMiTTebhL0MJXvD0ooUsHyrMPrxvEUzgXpDho1bt6llJIsTAYRMaaE8cbU3W7tPHfx yLLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758032587; x=1758637387; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AyiB622GUdP8Ps2sW1QaI66OgFpDcJd68CYchnKzFN8=; b=QFVKIiwvj2iFXH2Qo2QKUeGw1KROVSReZiQSFRClAbRsMbgbwjAHo/bQc10vgVZ+C4 ANaiSdXePZxC6GS0hpJNIk6mbkNQWypDL30mlKyf0ek/KobMuGgLL5YarXwggTgNMK+3 siAHdneBGxTjG0nETuvAb53ChFUWl/PvLMWABMHrt2Aj1vGsDCnK/rbWOwSe8gxoBfgW VNovpBacwfTRM8YZ31rsXeSEIMBAt3ZOkJeO9ED/tXUqGiTpO/Lt+Ma2dYu0Nq35EIQ+ ZnJZX+kfoX8qqF5qnI0jVpIX1WCLwXxRN03t8d+dzyt3dzEBp5oERF7lzdANLaN+9cxl ZIJA== X-Gm-Message-State: AOJu0YzrFh+QV1xCxeEUmoFoNZhtxEQ6zKjIg99sRf2NWRhJ6WZosRNX ELFRYHZ73zezm7e0KvK8e5If/bFiDm/LOIq8QnS/xVHvDGh1nMAu+Jopu0gIyo0bByqj8FVroWc BM8t3 X-Gm-Gg: ASbGncuuWRqtFN4hSypdpyYJAeUw96RXT8b+yGUcB3NSQv6y8fRB4svSKa7p+HHcEtU ZjD1PBerND1F3Qb3L500hiDwnvc6AY0hmfrCnpXClHtFQ9M/70NfrQav52GzOFxXJtax4nRCyGt 90smuF79D6BU7PheyVb6EdzLIsCJHy8Lm5bj05C7vbbsSSKpWEq1zY30wnaEdaDQ1X5erEYOoxC dHe2v7hq4C4tbO2YFpdl2cISv+Wk6O8hFDXcbobgpG04WeCv0OcG1EsJ3hh2uKYt7fkujGesdsL UiEFCo71V18iQeIV9ewb0mGNS/v3gs8qk5lYdaUYdzCkBxQuc1TVpb0HMMgq62jyjVqjiHsJAOz xhoFxVWMcKhAa5blGK+YZ0E5aGSAN6FBrV0AitsA= X-Google-Smtp-Source: AGHT+IFWXcg/tjajSOgda4sLcCf8URs2u3c/XsoOVKZyVxiebVe7pitg4847tYzBuRcrml5Qe9+DxQ== X-Received: by 2002:a17:902:cf09:b0:260:b4c7:986d with SMTP id d9443c01a7336-260b4c799f1mr149069845ad.36.1758032587128; Tue, 16 Sep 2025 07:23:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v2 34/36] target/arm: Redirect VHE FOO_EL12 to FOO_EL1 during translation Date: Tue, 16 Sep 2025 07:22:35 -0700 Message-ID: <20250916142238.664316-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916142238.664316-1-richard.henderson@linaro.org> References: <20250916142238.664316-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1758033252623116600 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpregs.h | 22 ++++--------- target/arm/gdbstub.c | 2 ++ target/arm/helper.c | 57 +++------------------------------- target/arm/tcg/translate-a64.c | 12 +++++++ 4 files changed, 25 insertions(+), 68 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index d34ed0d40b..f5d6a1c386 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -917,8 +917,12 @@ struct ARMCPRegInfo { */ uint32_t vhe_redir_to_el2; =20 - /* This is used only by VHE. */ - void *opaque; + /* + * With VHE, with E2H, at EL2+, access to this EL02/EL12 reg + * redirects to the EL0/EL1 reg with the specified key. + */ + uint32_t vhe_redir_to_el01; + /* * Value of this register, if it is ARM_CP_CONST. Otherwise, if * fieldoffset is non-zero, the reset value of the register. @@ -986,20 +990,6 @@ struct ARMCPRegInfo { * fieldoffset is 0 then no reset will be done. */ CPResetFn *resetfn; - - /* - * "Original" readfn, writefn, accessfn. - * For ARMv8.1-VHE register aliases, we overwrite the read/write - * accessor functions of various EL1/EL0 to perform the runtime - * check for which sysreg should actually be modified, and then - * forwards the operation. Before overwriting the accessors, - * the original function is copied here, so that accesses that - * really do go to the EL1/EL0 version proceed normally. - * (The corresponding EL2 register is linked via opaque.) - */ - CPReadFn *orig_readfn; - CPWriteFn *orig_writefn; - CPAccessFn *orig_accessfn; }; =20 void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs); diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 3727dc01af..269bc6c132 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -253,6 +253,8 @@ static int arm_gdb_get_sysreg(CPUState *cs, GByteArray = *buf, int reg) (arm_hcr_el2_eff(env) & HCR_E2H) && arm_current_el(env) =3D=3D 2) { ri =3D get_arm_cp_reginfo(cpu->cp_regs, ri->vhe_redir_to_e= l2); + } else if (ri->vhe_redir_to_el01) { + ri =3D get_arm_cp_reginfo(cpu->cp_regs, ri->vhe_redir_to_e= l01); } return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri)); case MO_32: diff --git a/target/arm/helper.c b/target/arm/helper.c index 49bb1e8365..8074c50241 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4456,42 +4456,6 @@ static CPAccessResult access_el1nvvct(CPUARMState *e= nv, const ARMCPRegInfo *ri, return e2h_access(env, ri, isread); } =20 -static uint64_t el2_e2h_e12_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - /* Pass the EL1 register accessor its ri, not the EL12 alias ri */ - return ri->orig_readfn(env, ri->opaque); -} - -static void el2_e2h_e12_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* Pass the EL1 register accessor its ri, not the EL12 alias ri */ - return ri->orig_writefn(env, ri->opaque, value); -} - -static CPAccessResult el2_e2h_e12_access(CPUARMState *env, - const ARMCPRegInfo *ri, - bool isread) -{ - if (arm_current_el(env) =3D=3D 1) { - /* - * This must be a FEAT_NV access (will either trap or redirect - * to memory). None of the registers with _EL12 aliases want to - * apply their trap controls for this kind of access, so don't - * call the orig_accessfn or do the "UNDEF when E2H is 0" check. - */ - return CP_ACCESS_OK; - } - /* FOO_EL12 aliases only exist when E2H is 1; otherwise they UNDEF */ - if (!(arm_hcr_el2_eff(env) & HCR_E2H)) { - return CP_ACCESS_UNDEFINED; - } - if (ri->orig_accessfn) { - return ri->orig_accessfn(env, ri->opaque, isread); - } - return CP_ACCESS_OK; -} - static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) { struct E2HAlias { @@ -4585,9 +4549,6 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCP= U *cpu) g_assert(strcmp(src_reg->name, a->src_name) =3D=3D 0); g_assert(strcmp(dst_reg->name, a->dst_name) =3D=3D 0); =20 - /* None of the core system registers use opaque; we will. */ - g_assert(src_reg->opaque =3D=3D NULL); - /* Create alias before redirection so we dup the right data. */ new_reg =3D g_memdup(src_reg, sizeof(ARMCPRegInfo)); =20 @@ -4606,19 +4567,11 @@ static void define_arm_vh_e2h_redirects_aliases(ARM= CPU *cpu) >> CP_REG_ARM64_SYSREG_OP1_SHIFT; new_reg->opc2 =3D (a->new_key & CP_REG_ARM64_SYSREG_OP2_MASK) >> CP_REG_ARM64_SYSREG_OP2_SHIFT; - new_reg->opaque =3D src_reg; - new_reg->orig_readfn =3D src_reg->readfn ?: raw_read; - new_reg->orig_writefn =3D src_reg->writefn ?: raw_write; - new_reg->orig_accessfn =3D src_reg->accessfn; - if (!new_reg->raw_readfn) { - new_reg->raw_readfn =3D raw_read; - } - if (!new_reg->raw_writefn) { - new_reg->raw_writefn =3D raw_write; - } - new_reg->readfn =3D el2_e2h_e12_read; - new_reg->writefn =3D el2_e2h_e12_write; - new_reg->accessfn =3D el2_e2h_e12_access; + new_reg->vhe_redir_to_el01 =3D a->src_key; + new_reg->readfn =3D NULL; + new_reg->writefn =3D NULL; + new_reg->accessfn =3D NULL; + new_reg->fieldoffset =3D 0; =20 /* * If the _EL1 register is redirected to memory by FEAT_NV2, diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 3ef24fb0c3..6728e362b6 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2580,6 +2580,18 @@ static void handle_sys(DisasContext *s, bool isread, */ key =3D ri->vhe_redir_to_el2; ri =3D redirect_cpreg(s, key, isread); + } else if (ri->vhe_redir_to_el01 && s->current_el >=3D 2) { + /* + * This is one of the FOO_EL12 registers. + * With !E2H, they all UNDEF. + * With E2H, from EL2 or EL3, they redirect to FOO_EL1. + */ + if (!s->e2h) { + gen_sysreg_undef(s, isread, op0, op1, op2, crn, crm, rt); + return; + } + key =3D ri->vhe_redir_to_el01; + ri =3D redirect_cpreg(s, key, isread); } =20 if (ri->accessfn || (ri->fgt && s->fgt_active)) { --=20 2.43.0 From nobody Sun Sep 28 16:37:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1758032755; cv=none; d=zohomail.com; s=zohoarc; b=aecJxIO56f2mjLmGlXzEeUJf1AVnQUAgFsxrIPyaMXdwu+4NmgDVjvc4GYP6S1Hs5+1t/KAh+9+EAd+b9vlSJbZSdFwFLCX4y8jF9oucIEIMZV9GM8pzfK7joySiIQO8Ghag57Rkj17xoOR/251sSGXi7JyNAOydkml5Px9O+do= ARC-Message-Signature: i=1; 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Reviewed-by: Manos Pitsidianakis Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/helper.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8074c50241..4172fcaa21 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -671,7 +671,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { */ { .name =3D "WFAR", .cp =3D 15, .crn =3D 6, .crm =3D 0, .opc1 =3D 0, .= opc2 =3D 1, .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0, }, - { .name =3D "CPACR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, + { .name =3D "CPACR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 1, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, .accessfn =3D cpac= r_access, .fgt =3D FGT_CPACR_EL1, .nv2_redirect_offset =3D 0x100 | NV2_REDIR_NV1, @@ -2018,7 +2018,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { .resetfn =3D arm_gt_cntfrq_reset, }, /* overall control: mostly access permissions */ - { .name =3D "CNTKCTL", .state =3D ARM_CP_STATE_BOTH, + { .name =3D "CNTKCTL_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 14, .crm =3D 1, .opc2 =3D 0, .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_cntkctl), @@ -3077,8 +3077,8 @@ static uint64_t mpidr_read(CPUARMState *env, const AR= MCPRegInfo *ri) } =20 static const ARMCPRegInfo lpae_cp_reginfo[] =3D { - /* NOP AMAIR0/1 */ - { .name =3D "AMAIR0", .state =3D ARM_CP_STATE_BOTH, + /* AMAIR0 is mapped to AMAIR_EL1[31:0] */ + { .name =3D "AMAIR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 10, .crm =3D 3, .opc1 =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_AMAIR_EL1, @@ -4469,11 +4469,11 @@ static void define_arm_vh_e2h_redirects_aliases(ARM= CPU *cpu) =20 static const struct E2HAlias aliases[] =3D { { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0), - "SCTLR", "SCTLR_EL2", "SCTLR_EL12" }, + "SCTLR_EL1", "SCTLR_EL2", "SCTLR_EL12" }, { K(3, 0, 1, 0, 3), K(3, 4, 1, 0, 3), K(3, 5, 1, 0, 3), "SCTLR2_EL1", "SCTLR2_EL2", "SCTLR2_EL12", isar_feature_aa64_sct= lr2 }, { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2), - "CPACR", "CPTR_EL2", "CPACR_EL12" }, + "CPACR_EL1", "CPTR_EL2", "CPACR_EL12" }, { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0), "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" }, { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1), @@ -4497,13 +4497,13 @@ static void define_arm_vh_e2h_redirects_aliases(ARM= CPU *cpu) { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0), "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" }, { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0), - "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" }, + "AMAIR_EL1", "AMAIR_EL2", "AMAIR_EL12" }, { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0), - "VBAR", "VBAR_EL2", "VBAR_EL12" }, + "VBAR_EL1", "VBAR_EL2", "VBAR_EL12" }, { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1), "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" }, { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0), - "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" }, + "CNTKCTL_EL1", "CNTHCTL_EL2", "CNTKCTL_EL12" }, =20 /* * Note that redirection of ZCR is mentioned in the description @@ -7145,7 +7145,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) =20 if (arm_feature(env, ARM_FEATURE_VBAR)) { static const ARMCPRegInfo vbar_cp_reginfo[] =3D { - { .name =3D "VBAR", .state =3D ARM_CP_STATE_BOTH, + { .name =3D "VBAR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 12, .crm =3D 0, .opc1 =3D 0, .opc2 =3D= 0, .access =3D PL1_RW, .writefn =3D vbar_write, .accessfn =3D access_nv1, @@ -7161,7 +7161,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) /* Generic registers whose values depend on the implementation */ { ARMCPRegInfo sctlr =3D { - .name =3D "SCTLR", .state =3D ARM_CP_STATE_BOTH, + .name =3D "SCTLR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_SCTLR_EL1, --=20 2.43.0 From nobody Sun Sep 28 16:37:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Clear the fields within add_cpreg_to_hashtable_aa32. Create the FOO_EL12 cpreg within add_cpreg_to_hashtable_aa64; add ARM_CP_NO_RAW. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpregs.h | 6 +- target/arm/helper.c | 249 ++++++++++++++++++-------------------------- 2 files changed, 107 insertions(+), 148 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index f5d6a1c386..9818be4429 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -918,8 +918,10 @@ struct ARMCPRegInfo { uint32_t vhe_redir_to_el2; =20 /* - * With VHE, with E2H, at EL2+, access to this EL02/EL12 reg - * redirects to the EL0/EL1 reg with the specified key. + * For VHE. Before registration, this field holds the key for an + * EL02/EL12 reg to be created to point back to this EL0/EL1 reg. + * After registration, this field is set only on the EL02/EL12 reg + * and points back to the EL02/EL12 reg for redirection with E2H. */ uint32_t vhe_redir_to_el01; =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index 4172fcaa21..5353d6a5f0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -454,6 +454,8 @@ static const ARMCPRegInfo cp_reginfo[] =3D { .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_CONTEXTIDR_EL1, .nv2_redirect_offset =3D 0x108 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 13, 0, 1), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 13, 0, 1), .secure =3D ARM_CP_SECSTATE_NS, .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[1]), .resetvalue =3D 0, .writefn =3D contextidr_write, .raw_writefn =3D r= aw_write, }, @@ -674,6 +676,8 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { { .name =3D "CPACR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 1, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, .accessfn =3D cpac= r_access, .fgt =3D FGT_CPACR_EL1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 1, 1, 2), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 1, 0, 2), .nv2_redirect_offset =3D 0x100 | NV2_REDIR_NV1, .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.cpac= r_el1), .resetfn =3D cpacr_reset, .writefn =3D cpacr_write, .readfn =3D cpac= r_read }, @@ -956,12 +960,16 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_AFSR0_EL1, .nv2_redirect_offset =3D 0x128 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 5, 1, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 5, 1, 0), .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "AFSR1_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 1, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_AFSR1_EL1, .nv2_redirect_offset =3D 0x130 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 5, 1, 1), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 5, 1, 1), .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, /* * MAIR can just read-as-written because we don't implement caches @@ -972,6 +980,8 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_MAIR_EL1, .nv2_redirect_offset =3D 0x140 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 10, 2, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 10, 2, 0), .fieldoffset =3D offsetof(CPUARMState, cp15.mair_el[1]), .resetvalue =3D 0 }, { .name =3D "MAIR_EL3", .state =3D ARM_CP_STATE_AA64, @@ -2021,6 +2031,8 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { { .name =3D "CNTKCTL_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 14, .crm =3D 1, .opc2 =3D 0, .access =3D PL1_RW, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 14, 1, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 14, 1, 0), .fieldoffset =3D offsetof(CPUARMState, cp15.c14_cntkctl), .resetvalue =3D 0, }, @@ -2811,6 +2823,8 @@ static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] =3D { .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_FAR_EL1, .nv2_redirect_offset =3D 0x220 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 6, 0, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 6, 0, 0), .fieldoffset =3D offsetof(CPUARMState, cp15.far_el[1]), .resetvalue =3D 0, }, }; @@ -2821,12 +2835,16 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_ESR_EL1, .nv2_redirect_offset =3D 0x138 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 5, 2, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 5, 2, 0), .fieldoffset =3D offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = =3D 0, }, { .name =3D "TTBR0_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_TTBR0_EL1, .nv2_redirect_offset =3D 0x200 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 2, 0, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 2, 0, 0), .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, .raw_writefn =3D ra= w_write, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) } }, @@ -2835,6 +2853,8 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_TTBR1_EL1, .nv2_redirect_offset =3D 0x210 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 2, 0, 1), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 2, 0, 1), .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, .raw_writefn =3D ra= w_write, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) } }, @@ -2843,6 +2863,8 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_TCR_EL1, .nv2_redirect_offset =3D 0x120 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 2, 0, 2), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 2, 0, 2), .writefn =3D vmsa_tcr_el12_write, .raw_writefn =3D raw_write, .resetvalue =3D 0, @@ -3083,6 +3105,8 @@ static const ARMCPRegInfo lpae_cp_reginfo[] =3D { .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_AMAIR_EL1, .nv2_redirect_offset =3D 0x148 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 10, 3, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 10, 3, 0), .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ { .name =3D "AMAIR1", .cp =3D 15, .crn =3D 10, .crm =3D 3, .opc1 =3D 0= , .opc2 =3D 1, @@ -3608,12 +3632,16 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 0, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_nv1, .nv2_redirect_offset =3D 0x230 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 4, 0, 1), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 4, 0, 1), .fieldoffset =3D offsetof(CPUARMState, elr_el[1]) }, { .name =3D "SPSR_EL1", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_ALIAS, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_nv1, .nv2_redirect_offset =3D 0x160 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 4, 0, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 4, 0, 0), .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_SVC]) }, /* * We rely on the access checks not allowing the guest to write to the @@ -4455,142 +4483,6 @@ static CPAccessResult access_el1nvvct(CPUARMState *= env, const ARMCPRegInfo *ri, } return e2h_access(env, ri, isread); } - -static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) -{ - struct E2HAlias { - uint32_t src_key, dst_key, new_key; - const char *src_name, *dst_name, *new_name; - bool (*feature)(const ARMISARegisters *id); - }; - -#define K(op0, op1, crn, crm, op2) \ - ENCODE_AA64_CP_REG(op0, op1, crn, crm, op2) - - static const struct E2HAlias aliases[] =3D { - { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0), - "SCTLR_EL1", "SCTLR_EL2", "SCTLR_EL12" }, - { K(3, 0, 1, 0, 3), K(3, 4, 1, 0, 3), K(3, 5, 1, 0, 3), - "SCTLR2_EL1", "SCTLR2_EL2", "SCTLR2_EL12", isar_feature_aa64_sct= lr2 }, - { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2), - "CPACR_EL1", "CPTR_EL2", "CPACR_EL12" }, - { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0), - "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" }, - { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1), - "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" }, - { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2), - "TCR_EL1", "TCR_EL2", "TCR_EL12" }, - { K(3, 0, 2, 0, 3), K(3, 4, 2, 0, 3), K(3, 5, 2, 0, 3), - "TCR2_EL1", "TCR2_EL2", "TCR2_EL12", isar_feature_aa64_tcr2 }, - { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0), - "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" }, - { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1), - "ELR_EL1", "ELR_EL2", "ELR_EL12" }, - { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0), - "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" }, - { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1), - "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" }, - { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0), - "ESR_EL1", "ESR_EL2", "ESR_EL12" }, - { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0), - "FAR_EL1", "FAR_EL2", "FAR_EL12" }, - { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0), - "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" }, - { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0), - "AMAIR_EL1", "AMAIR_EL2", "AMAIR_EL12" }, - { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0), - "VBAR_EL1", "VBAR_EL2", "VBAR_EL12" }, - { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1), - "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" }, - { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0), - "CNTKCTL_EL1", "CNTHCTL_EL2", "CNTKCTL_EL12" }, - - /* - * Note that redirection of ZCR is mentioned in the description - * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but - * not in the summary table. - */ - { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0), - "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve }, - { K(3, 0, 1, 2, 6), K(3, 4, 1, 2, 6), K(3, 5, 1, 2, 6), - "SMCR_EL1", "SMCR_EL2", "SMCR_EL12", isar_feature_aa64_sme }, - - { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0), - "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte }, - - { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7), - "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12", - isar_feature_aa64_scxtnum }, - - /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */ - /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */ - }; -#undef K - - size_t i; - - for (i =3D 0; i < ARRAY_SIZE(aliases); i++) { - const struct E2HAlias *a =3D &aliases[i]; - ARMCPRegInfo *src_reg, *dst_reg, *new_reg; - bool ok; - - if (a->feature && !a->feature(&cpu->isar)) { - continue; - } - - src_reg =3D g_hash_table_lookup(cpu->cp_regs, - (gpointer)(uintptr_t)a->src_key); - dst_reg =3D g_hash_table_lookup(cpu->cp_regs, - (gpointer)(uintptr_t)a->dst_key); - g_assert(src_reg !=3D NULL); - g_assert(dst_reg !=3D NULL); - - /* Cross-compare names to detect typos in the keys. */ - g_assert(strcmp(src_reg->name, a->src_name) =3D=3D 0); - g_assert(strcmp(dst_reg->name, a->dst_name) =3D=3D 0); - - /* Create alias before redirection so we dup the right data. */ - new_reg =3D g_memdup(src_reg, sizeof(ARMCPRegInfo)); - - new_reg->name =3D a->new_name; - new_reg->type |=3D ARM_CP_ALIAS; - /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */ - new_reg->access &=3D PL2_RW | PL3_RW; - /* The new_reg op fields are as per new_key, not the target reg */ - new_reg->crn =3D (a->new_key & CP_REG_ARM64_SYSREG_CRN_MASK) - >> CP_REG_ARM64_SYSREG_CRN_SHIFT; - new_reg->crm =3D (a->new_key & CP_REG_ARM64_SYSREG_CRM_MASK) - >> CP_REG_ARM64_SYSREG_CRM_SHIFT; - new_reg->opc0 =3D (a->new_key & CP_REG_ARM64_SYSREG_OP0_MASK) - >> CP_REG_ARM64_SYSREG_OP0_SHIFT; - new_reg->opc1 =3D (a->new_key & CP_REG_ARM64_SYSREG_OP1_MASK) - >> CP_REG_ARM64_SYSREG_OP1_SHIFT; - new_reg->opc2 =3D (a->new_key & CP_REG_ARM64_SYSREG_OP2_MASK) - >> CP_REG_ARM64_SYSREG_OP2_SHIFT; - new_reg->vhe_redir_to_el01 =3D a->src_key; - new_reg->readfn =3D NULL; - new_reg->writefn =3D NULL; - new_reg->accessfn =3D NULL; - new_reg->fieldoffset =3D 0; - - /* - * If the _EL1 register is redirected to memory by FEAT_NV2, - * then it shares the offset with the _EL12 register, - * and which one is redirected depends on HCR_EL2.NV1. - */ - if (new_reg->nv2_redirect_offset) { - assert(new_reg->nv2_redirect_offset & NV2_REDIR_NV1); - new_reg->nv2_redirect_offset &=3D ~NV2_REDIR_NV1; - new_reg->nv2_redirect_offset |=3D NV2_REDIR_NO_NV1; - } - - ok =3D g_hash_table_insert(cpu->cp_regs, - (gpointer)(uintptr_t)a->new_key, new_reg); - g_assert(ok); - - src_reg->vhe_redir_to_el2 =3D a->dst_key; - } -} #endif =20 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo = *ri, @@ -4883,6 +4775,8 @@ static const ARMCPRegInfo zcr_reginfo[] =3D { { .name =3D "ZCR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, .nv2_redirect_offset =3D 0x1e0 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 1, 2, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 1, 2, 0), .access =3D PL1_RW, .type =3D ARM_CP_SVE, .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[1]), .writefn =3D zcr_write, .raw_writefn =3D raw_write }, @@ -5028,6 +4922,8 @@ static const ARMCPRegInfo sme_reginfo[] =3D { { .name =3D "SMCR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 2, .opc2 =3D 6, .nv2_redirect_offset =3D 0x1f0 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 1, 2, 6), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 1, 2, 6), .access =3D PL1_RW, .type =3D ARM_CP_SME, .fieldoffset =3D offsetof(CPUARMState, vfp.smcr_el[1]), .writefn =3D smcr_write, .raw_writefn =3D raw_write }, @@ -5473,6 +5369,8 @@ static const ARMCPRegInfo mte_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 6, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tfsr_el1, .nv2_redirect_offset =3D 0x190 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 5, 6, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 5, 6, 0), .fieldoffset =3D offsetof(CPUARMState, cp15.tfsr_el[1]) }, { .name =3D "TFSR_EL2", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_NV2_REDIRECT, @@ -5648,6 +5546,8 @@ static const ARMCPRegInfo scxtnum_reginfo[] =3D { .access =3D PL1_RW, .accessfn =3D access_scxtnum_el1, .fgt =3D FGT_SCXTNUM_EL1, .nv2_redirect_offset =3D 0x188 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 13, 0, 7), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 13, 0, 7), .fieldoffset =3D offsetof(CPUARMState, scxtnum_el[1]) }, { .name =3D "SCXTNUM_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 7, @@ -5992,6 +5892,8 @@ static const ARMCPRegInfo sctlr2_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 3, .crn =3D 1, .crm =3D 0, .access =3D PL1_RW, .accessfn =3D sctlr2_el1_access, .writefn =3D sctlr2_el1_write, .fgt =3D FGT_SCTLR_EL1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 1, 0, 3), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 1, 0, 3), .nv2_redirect_offset =3D 0x278 | NV2_REDIR_NV1, .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr2_el[1]) }, { .name =3D "SCTLR2_EL2", .state =3D ARM_CP_STATE_AA64, @@ -6052,6 +5954,8 @@ static const ARMCPRegInfo tcr2_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 3, .crn =3D 2, .crm =3D 0, .access =3D PL1_RW, .accessfn =3D tcr2_el1_access, .writefn =3D tcr2_el1_write, .fgt =3D FGT_TCR_EL1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 2, 0, 3), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 2, 0, 3), .nv2_redirect_offset =3D 0x270 | NV2_REDIR_NV1, .fieldoffset =3D offsetof(CPUARMState, cp15.tcr2_el[1]) }, { .name =3D "TCR2_EL2", .state =3D ARM_CP_STATE_AA64, @@ -7151,6 +7055,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) .accessfn =3D access_nv1, .fgt =3D FGT_VBAR_EL1, .nv2_redirect_offset =3D 0x250 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 12, 0, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 12, 0, 0), .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.vbar_s), offsetof(CPUARMState, cp15.vbar_ns) }, .resetvalue =3D 0 }, @@ -7165,6 +7071,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_SCTLR_EL1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 1, 0, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 1, 0, 0), .nv2_redirect_offset =3D 0x110 | NV2_REDIR_NV1, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.sctlr_s), offsetof(CPUARMState, cp15.sctlr_ns) }, @@ -7307,16 +7215,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) } =20 define_pm_cpregs(cpu); - -#ifndef CONFIG_USER_ONLY - /* - * Register redirections and aliases must be done last, - * after the registers from the other extensions have been defined. - */ - if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu= )) { - define_arm_vh_e2h_redirects_aliases(cpu); - } -#endif } =20 /* @@ -7449,6 +7347,8 @@ static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, = ARMCPRegInfo *r) r->crm, r->opc1, r->opc2); =20 assert(!(r->type & ARM_CP_ADD_TLBI_NXS)); /* aa64 only */ + r->vhe_redir_to_el2 =3D 0; + r->vhe_redir_to_el01 =3D 0; =20 switch (r->secure) { case ARM_CP_SECSTATE_NS: @@ -7502,6 +7402,63 @@ static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu,= ARMCPRegInfo *r) ARM_CP_SECSTATE_NS, nxs_key); } =20 + if (!r->vhe_redir_to_el01) { + assert(!r->vhe_redir_to_el2); + } else if (!arm_feature(&cpu->env, ARM_FEATURE_EL2) || + !cpu_isar_feature(aa64_vh, cpu)) { + r->vhe_redir_to_el2 =3D 0; + r->vhe_redir_to_el01 =3D 0; + } else { + /* Create the FOO_EL12 alias. */ + ARMCPRegInfo *r2 =3D alloc_cpreg(r, "2"); + uint32_t key2 =3D r->vhe_redir_to_el01; + + /* + * Clear EL1 redirection on the FOO_EL1 reg; + * Clear EL2 redirection on the FOO_EL12 reg; + * Install redirection from FOO_EL12 back to FOO_EL1. + */ + r->vhe_redir_to_el01 =3D 0; + r2->vhe_redir_to_el2 =3D 0; + r2->vhe_redir_to_el01 =3D key; + + r2->type |=3D ARM_CP_ALIAS | ARM_CP_NO_RAW; + /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */ + r2->access &=3D PL2_RW | PL3_RW; + /* The new_reg op fields are as per new_key, not the target reg */ + r2->crn =3D (key2 & CP_REG_ARM64_SYSREG_CRN_MASK) + >> CP_REG_ARM64_SYSREG_CRN_SHIFT; + r2->crm =3D (key2 & CP_REG_ARM64_SYSREG_CRM_MASK) + >> CP_REG_ARM64_SYSREG_CRM_SHIFT; + r2->opc0 =3D (key2 & CP_REG_ARM64_SYSREG_OP0_MASK) + >> CP_REG_ARM64_SYSREG_OP0_SHIFT; + r2->opc1 =3D (key2 & CP_REG_ARM64_SYSREG_OP1_MASK) + >> CP_REG_ARM64_SYSREG_OP1_SHIFT; + r2->opc2 =3D (key2 & CP_REG_ARM64_SYSREG_OP2_MASK) + >> CP_REG_ARM64_SYSREG_OP2_SHIFT; + + /* Non-redirected access to this register will abort. */ + r2->readfn =3D NULL; + r2->writefn =3D NULL; + r2->raw_readfn =3D NULL; + r2->raw_writefn =3D NULL; + r2->accessfn =3D NULL; + r2->fieldoffset =3D 0; + + /* + * If the _EL1 register is redirected to memory by FEAT_NV2, + * then it shares the offset with the _EL12 register, + * and which one is redirected depends on HCR_EL2.NV1. + */ + if (r2->nv2_redirect_offset) { + assert(r2->nv2_redirect_offset & NV2_REDIR_NV1); + r2->nv2_redirect_offset &=3D ~NV2_REDIR_NV1; + r2->nv2_redirect_offset |=3D NV2_REDIR_NO_NV1; + } + add_cpreg_to_hashtable(cpu, r2, ARM_CP_STATE_AA64, + ARM_CP_SECSTATE_NS, key2); + } + add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA64, ARM_CP_SECSTATE_NS, key); } --=20 2.43.0