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Iglesias" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , "Frederic Konrad" , Sai Pavan Boddu Subject: [PATCH v5 39/47] target/arm/tcg/cpu64: add the cortex-a78ae CPU Date: Fri, 12 Sep 2025 12:00:48 +0200 Message-ID: <20250912100059.103997-40-luc.michel@amd.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250912100059.103997-1-luc.michel@amd.com> References: <20250912100059.103997-1-luc.michel@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB04.amd.com: luc.michel@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099D7:EE_|IA0PR12MB8838:EE_ X-MS-Office365-Filtering-Correlation-Id: 9a6a7b4c-54a4-4f57-8e3b-08ddf1e396ed X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?y/yoYI/TVmyR02c42ZoiaAABLQF12ogB6uC75oE7/hK9ZbIbl2DkBld9xVPF?= =?us-ascii?Q?or/4Quy/qECKn0fg8s9ELsHC0p9wzPKqRws8Jly98/GGP5yJpFfk0thwgI+u?= =?us-ascii?Q?6RwCjRjmMryBn0JVoGQJrCV6iq2JagIdOHGNZmYNcyFDFRPU15JWf/sYZEoh?= =?us-ascii?Q?YAJXV9yImwWb+R8xeN4R8DsxbQwHOQeNPkqIXXZL9xtzOBkJ6md3FtlDd+Ks?= =?us-ascii?Q?LZIV17us1gfV1rzKZskJPC0kAfCmybHUvnGCSjrCWaK2jLIv2B/ztGJY/Lt1?= =?us-ascii?Q?RabLDA/XKDNOoWEyt4AZeWg5VAyhN4iSBvf248Fsg4KmgO65UJfkJ+aICfLP?= =?us-ascii?Q?Jh+5GQCnzvzxUyqwoAV6iOVKqPV3wh4V3acFmdUioMZKND5QmrJETfkeXhhg?= =?us-ascii?Q?6M4A4/4pdGEYyy2Y8umE4KULy1ruVl846MIG7bPa9yS73nPogls1O4zunq7N?= =?us-ascii?Q?QrjgeaHDXPRdluGaYw+/ByHGuf3xkhrpHg96E0WnMbosfHTPjrKVgkIPEshK?= =?us-ascii?Q?+I6HoQXEtgHrupVnwz6UnkcQMRZllmXd47f2HI3A/tsAFhovZ0PMkD7hQWDU?= =?us-ascii?Q?lovTyYkYGOFuAvVwDBbG0yB+/aEr9W2DLLR86QZC1zxhimb/juHsGwaFbPWI?= =?us-ascii?Q?RwrAZAiRx1CWv/mGBtPVhAP0a9VVXVjJVTccPtY3tj5SkJ3lSfw2KsUTb2Yg?= =?us-ascii?Q?cYtdryklpt1jRlDnUVZ0pBICUXqLM/YnnVczsO3iahscqhDO1sc46e/MiG91?= =?us-ascii?Q?gsaC3UHUCE/4cnH7iS4bvCjF4gqaRFDAr50csDZIm1e4Y/vh7shtHueNzP5q?= =?us-ascii?Q?/aAw5yXvlAvdsO28e5IL0qFRHWSDxfDpg0tdhlRreUkAJuM01ao6olQ1R7pt?= =?us-ascii?Q?UbzvbgZ6cRuBcfTFVsHk3qntsedodylxNIG5GIRzgoFaFm6LJmEvlOcLFvff?= =?us-ascii?Q?14Kf1s1cgTnJv/RKSf/IOstTbYnDMcXyX1TuWig7vuWVzjTjPlThCi12lTlb?= =?us-ascii?Q?1OnVUiFWCe5CsluV/qvNW+xz4HmNizW+MSVyBRD9hQOwrucsSoYj9MTgPW2x?= =?us-ascii?Q?04kiil2hBkqdXS4MDZbKi4/wTS0/aBl6HZy6JugmlfwiY6WN8u/xjLJ2pcnF?= =?us-ascii?Q?+Ma2NAZ7EH8CsZJYJzonpYczCUiO1YFLsmBZtIbbR8d+TYyQyJYlIAp3qhV2?= =?us-ascii?Q?RvMnO9rkhYQ5XF9Su5vjJZpjFpf7CT4xboMFlxCv/c1mSGMc1sD+IFm9+9Nh?= =?us-ascii?Q?iYBDmwpwnk+1wmb3P2FSJbUKYklkXELANBuBR/kmaoysKVFkCCRzrcSo+OVn?= =?us-ascii?Q?LvYT6I3S8KbPn0ccFGgv9wfWCG09Mzt/iq+6C8gnM2k+LsjjaF6VbQ0AVnhe?= =?us-ascii?Q?YK7p3GtVgSFNGlZQ5wyJHG45ka6Hc48B/bJWi73Zprh+fbykLZZqwtCZkUUk?= =?us-ascii?Q?hpmZ8gvr5XwJA/v7M7U9u5FpTvm2YCNFFVnObMYMeF8PZPCz1u52My+m7NtQ?= =?us-ascii?Q?lydjN//s3OWEOXHCBDZosFFHNrGZsS9pcyGp?= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:satlexmb08.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Sep 2025 10:03:14.7691 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9a6a7b4c-54a4-4f57-8e3b-08ddf1e396ed X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D7.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8838 Received-SPF: permerror client-ip=2a01:111:f403:2412::624; envelope-from=Luc.Michel@amd.com; helo=NAM10-MW2-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1757671905720116600 Content-Type: text/plain; charset="utf-8" Add support for the ARM Cortex-A78AE CPU. Signed-off-by: Luc Michel Reviewed-by: Peter Maydell --- target/arm/tcg/cpu64.c | 78 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index b8b1981e702..81b95923b4b 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -404,10 +404,83 @@ static void aarch64_a76_initfn(Object *obj) =20 /* From D5.1 AArch64 PMU register summary */ cpu->isar.reset_pmcr_el0 =3D 0x410b3000; } =20 +static void aarch64_a78ae_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; + + cpu->dtb_compatible =3D "arm,cortex-a78ae"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + + /* Ordered by 3.2.4 AArch64 registers by functional group */ + SET_IDREG(isar, CLIDR, 0x82000023); + cpu->ctr =3D 0x9444c004; + cpu->dcz_blocksize =3D 4; + SET_IDREG(isar, ID_AA64DFR0, 0x0000000110305408ull); + SET_IDREG(isar, ID_AA64ISAR0, 0x0010100010211120ull); + SET_IDREG(isar, ID_AA64ISAR1, 0x0000000001200031ull); + SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101125ull); + SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull); + SET_IDREG(isar, ID_AA64MMFR2, 0x0000000100001011ull); + SET_IDREG(isar, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in = later */ + SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull); + SET_IDREG(isar, ID_AFR0, 0x00000000); + SET_IDREG(isar, ID_DFR0, 0x04010088); + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232042); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00010142); + SET_IDREG(isar, ID_ISAR5, 0x01011121); + SET_IDREG(isar, ID_ISAR6, 0x00000010); + SET_IDREG(isar, ID_MMFR0, 0x10201105); + SET_IDREG(isar, ID_MMFR1, 0x40000000); + SET_IDREG(isar, ID_MMFR2, 0x01260000); + SET_IDREG(isar, ID_MMFR3, 0x02122211); + SET_IDREG(isar, ID_MMFR4, 0x00021110); + SET_IDREG(isar, ID_PFR0, 0x10010131); + SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ + SET_IDREG(isar, ID_PFR2, 0x00000011); + cpu->midr =3D 0x410fd423; /* r0p3 */ + cpu->revidr =3D 0; + + /* From 3.2.33 CCSIDR_EL1 */ + /* 64KB L1 dcache */ + cpu->ccsidr[0] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, = 7); + /* 64KB L1 icache */ + cpu->ccsidr[1] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, = 2); + /* 512KB L2 cache */ + cpu->ccsidr[2] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 512 * KiB,= 7); + + /* From 3.2.118 SCTLR_EL3 */ + cpu->reset_sctlr =3D 0x30c50838; + + /* From 3.4.23 ICH_VTR_EL2 */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + /* From 3.4.8 ICC_CTLR_EL3 */ + cpu->gic_pribits =3D 5; + + /* From 3.5.1 AdvSIMD AArch64 register summary */ + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x13211111; + cpu->isar.mvfr2 =3D 0x00000043; + + /* From 5.5.1 AArch64 PMU register summary */ + cpu->isar.reset_pmcr_el0 =3D 0x41223000; +} + static void aarch64_a64fx_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); ARMISARegisters *isar =3D &cpu->isar; =20 @@ -1318,10 +1391,15 @@ void aarch64_max_tcg_initfn(Object *obj) static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a35", .initfn =3D aarch64_a35_initfn }, { .name =3D "cortex-a55", .initfn =3D aarch64_a55_initfn }, { .name =3D "cortex-a72", .initfn =3D aarch64_a72_initfn }, { .name =3D "cortex-a76", .initfn =3D aarch64_a76_initfn }, + /* + * The Cortex-A78AE differs slightly from the plain Cortex-A78. We don= 't + * currently model the latter. + */ + { .name =3D "cortex-a78ae", .initfn =3D aarch64_a78ae_initfn }, { .name =3D "cortex-a710", .initfn =3D aarch64_a710_initfn }, { .name =3D "a64fx", .initfn =3D aarch64_a64fx_initfn }, { .name =3D "neoverse-n1", .initfn =3D aarch64_neoverse_n1_init= fn }, { .name =3D "neoverse-v1", .initfn =3D aarch64_neoverse_v1_init= fn }, { .name =3D "neoverse-n2", .initfn =3D aarch64_neoverse_n2_init= fn }, --=20 2.50.1