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Iglesias" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , "Frederic Konrad" , Sai Pavan Boddu Subject: [PATCH v5 03/47] hw/arm/xlnx-versal: uart: refactor creation Date: Fri, 12 Sep 2025 12:00:12 +0200 Message-ID: <20250912100059.103997-4-luc.michel@amd.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250912100059.103997-1-luc.michel@amd.com> References: <20250912100059.103997-1-luc.michel@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099DE:EE_|MW6PR12MB7070:EE_ X-MS-Office365-Filtering-Correlation-Id: 6abb59ca-4c0b-4969-490c-08ddf1e352df X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|1800799024|82310400026|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?54pFtlyRCQZdPvQz8suEKpliknRIQgZ8uTs211R5Kg7SUFAq6DLVsMw1St/L?= =?us-ascii?Q?0/z29ZcIWctnAKUqyqRX+4pkMrzpl+uQxPY/lLB3qPGh7+8a9EgMA2mE3bYJ?= =?us-ascii?Q?yMFV5C9l9p/HkNlb5acbEDwyjiekpvyFnCgRvcfhJl45vwcfb8ImkRZkCeFk?= =?us-ascii?Q?ffIdsETuuGg4xUnVfhWw+ovRLBVdLhJ2vSEq6h7+51PSzpYtWAWApk/RJaWA?= =?us-ascii?Q?Ypy6mfhqFmr8imZ5UQp4DcODuU7qyZEOi/u1dKzFUErvQSb+6+FAWkguwYOb?= =?us-ascii?Q?2Z+faQCeevvSuDk0Aa9DfGkERQGdx3sXklPB8QbnXigccAjc0pMTIwD8vGW8?= =?us-ascii?Q?jUr7703LwvX5L9ROpNyphkRfyrGPekGBwfTTcHs7jrA3CkzBWXYVsTsOnjkz?= =?us-ascii?Q?h4Nt0d7liFLeYFM0adHTOKwXRtT2MUpOxG11z+XkKSk9SVEgf7Q/Q28kjgIf?= =?us-ascii?Q?l48hFHiMWlMGmBqCLnbBU5sS44e9Pz9NwmdupoF52dmjmjpl5BbZvIIe+o+Q?= =?us-ascii?Q?jIoGlz8aaoSNTP9gB0GED6SWicJwJ+sI4sVMLZBUPtf0Ei3qUyp6BFd/VK+w?= =?us-ascii?Q?09pAq2ffojW7dP4tEBTYHjHrr0nfOt9vqnwXKqB7E5ZfoxnPvDAlU7D74teQ?= =?us-ascii?Q?0Y7Yz0KTZm5ZFdsD6EfUaSBIgQ506hGiu9nFyvF+CuEUmGbcrWa5J+5zE8mL?= =?us-ascii?Q?uZhgRqhpteo6rh1kGtjPXwbhFqJTPKyxnK00ZG9BTbTB1e/F1vA9W/ezUCUq?= =?us-ascii?Q?eL/V/oUyqNaFtCdb9MvUXi2TR+p8gCLbAOSO5PQgYYQGshvEDCA4iEg4nCXI?= =?us-ascii?Q?T9Yw83mhVxRJf2qYqQ2tmo4NvyzrefwXSWmIrHizNYpnoaa/FUPEcs9foQno?= =?us-ascii?Q?0+AskN4CD87pK1DAYTvrXGFZ5ZJrO/zvGUw2iIKmWPg5RYK/VB99uvXI//WC?= =?us-ascii?Q?PXX0gM+Kg6ZI6KKs2vdkcz6N4A14n7G+MqnbpMHRVBhv/upMVHEmE9RpO75t?= =?us-ascii?Q?TdR8w+BE8W+aumlJHZrK9Pu1OysZvfSlu9w22G3S7zQKsl/N+DRimGH1NM6i?= =?us-ascii?Q?ZywqrWMLvUqR6ne8lnim5V3pK2kJr2T99gJhoC2Fxiv/KJpYs9TdukAMK1tv?= =?us-ascii?Q?Qb9Qqy5GrTi7OMf5bARXv8loxC9rnS5dmZ5MwL/IN5HZEu4yIKCDbOlBGy07?= =?us-ascii?Q?zL9XieqAkCpeJIdggjuRuLlMFKtqVPZArnTQT1cGyWZxSA68frT4JyyR3UsL?= =?us-ascii?Q?HKqWsaH0p+U2sf1Ro2rcYRO47RWxX4NjVNaZyUHm9Y+MGgikpyNrtCJGb/pD?= =?us-ascii?Q?Khb6tt4wJYKa6/NLxtPkzRuA7AkKcGG9HFgyutMe3xe+DYuGb22i7tujtFfH?= =?us-ascii?Q?WqL1Gl+s7ggCVSA00vhKT8y+DbzkN6/kJOhRSV8Ntfkt4ohqpskCummZ9Pr8?= =?us-ascii?Q?yAkrNTUSOqhhJzeU/xIjDlOwQotdeP6DWWlwLl23QJ7Kq289JFeb5jWsD1pI?= =?us-ascii?Q?XwWMFBxmaFBuXXoTYEdAZh+qKo1m8uGld5yi?= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:satlexmb07.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Sep 2025 10:01:20.5903 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6abb59ca-4c0b-4969-490c-08ddf1e352df X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DE.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB7070 Received-SPF: permerror client-ip=2a01:111:f403:2409::614; envelope-from=Luc.Michel@amd.com; helo=NAM04-DM6-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1757671360471116600 Content-Type: text/plain; charset="utf-8" Refactor the UARTs creations. The VersalMap struct is now used to describe the SoC and its peripherals. For now it contains the two UARTs mapping information. The creation function now embeds the FDT creation logic as well. The devices are now created dynamically using qdev_new and (qdev|sysbus)_realize_and_unref. This will allow to rely entirely on the VersalMap structure to create the SoC and allow easy addition of new SoCs of the same family (like versal2 coming with next commits). Note that the connection to the CRL is removed for now and will be re-added by next commits. Signed-off-by: Luc Michel Reviewed-by: Francisco Iglesias --- include/hw/arm/xlnx-versal.h | 2 - hw/arm/xlnx-versal-virt.c | 36 +-------- hw/arm/xlnx-versal.c | 144 ++++++++++++++++++++++++++++------- 3 files changed, 119 insertions(+), 63 deletions(-) diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index f2a62b43552..b01ddeb1423 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -16,11 +16,10 @@ #include "hw/sysbus.h" #include "hw/cpu/cluster.h" #include "hw/or-irq.h" #include "hw/sd/sdhci.h" #include "hw/intc/arm_gicv3.h" -#include "hw/char/pl011.h" #include "hw/dma/xlnx-zdma.h" #include "hw/net/cadence_gem.h" #include "hw/rtc/xlnx-zynqmp-rtc.h" #include "qom/object.h" #include "hw/usb/xlnx-usb-subsystem.h" @@ -78,11 +77,10 @@ struct Versal { =20 struct { MemoryRegion mr_ocm; =20 struct { - PL011State uart[XLNX_VERSAL_NR_UARTS]; CadenceGEMState gem[XLNX_VERSAL_NR_GEMS]; OrIRQState gem_irq_orgate[XLNX_VERSAL_NR_GEMS]; XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS]; VersalUsb2 usb; CanBusState *canbus[XLNX_VERSAL_NR_CANFD]; diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index d1c65afa2ac..e1deae11317 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -75,10 +75,11 @@ static void fdt_create(VersalVirt *s) =20 s->phandle.usb =3D qemu_fdt_alloc_phandle(s->fdt); s->phandle.dwc =3D qemu_fdt_alloc_phandle(s->fdt); /* Create /chosen node for load_dtb. */ qemu_fdt_add_subnode(s->fdt, "/chosen"); + qemu_fdt_add_subnode(s->fdt, "/aliases"); =20 /* Header */ qemu_fdt_setprop_cell(s->fdt, "/", "interrupt-parent", s->phandle.gic); qemu_fdt_setprop_cell(s->fdt, "/", "#size-cells", 0x2); qemu_fdt_setprop_cell(s->fdt, "/", "#address-cells", 0x2); @@ -206,44 +207,10 @@ static void fdt_add_usb_xhci_nodes(VersalVirt *s) qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.dwc); qemu_fdt_setprop_string(s->fdt, name, "maximum-speed", "high-speed"); g_free(name); } =20 -static void fdt_add_uart_nodes(VersalVirt *s) -{ - uint64_t addrs[] =3D { MM_UART1, MM_UART0 }; - unsigned int irqs[] =3D { VERSAL_UART1_IRQ_0, VERSAL_UART0_IRQ_0 }; - const char compat[] =3D "arm,pl011\0arm,sbsa-uart"; - const char clocknames[] =3D "uartclk\0apb_pclk"; - int i; - - for (i =3D 0; i < ARRAY_SIZE(addrs); i++) { - char *name =3D g_strdup_printf("/uart@%" PRIx64, addrs[i]); - qemu_fdt_add_subnode(s->fdt, name); - qemu_fdt_setprop_cell(s->fdt, name, "current-speed", 115200); - qemu_fdt_setprop_cells(s->fdt, name, "clocks", - s->phandle.clk_125Mhz, s->phandle.clk_125Mh= z); - qemu_fdt_setprop(s->fdt, name, "clock-names", - clocknames, sizeof(clocknames)); - - qemu_fdt_setprop_cells(s->fdt, name, "interrupts", - GIC_FDT_IRQ_TYPE_SPI, irqs[i], - GIC_FDT_IRQ_FLAGS_LEVEL_HI); - qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", - 2, addrs[i], 2, 0x1000); - qemu_fdt_setprop(s->fdt, name, "compatible", - compat, sizeof(compat)); - qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0); - - if (addrs[i] =3D=3D MM_UART0) { - /* Select UART0. */ - qemu_fdt_setprop_string(s->fdt, "/chosen", "stdout-path", name= ); - } - g_free(name); - } -} - static void fdt_add_canfd_nodes(VersalVirt *s) { uint64_t addrs[] =3D { MM_CANFD1, MM_CANFD0 }; uint32_t size[] =3D { MM_CANFD1_SIZE, MM_CANFD0_SIZE }; unsigned int irqs[] =3D { VERSAL_CANFD1_IRQ_0, VERSAL_CANFD0_IRQ_0 }; @@ -703,11 +670,10 @@ static void versal_virt_init(MachineState *machine) versal_set_fdt(&s->soc, s->fdt); sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal); create_virtio_regions(s); =20 fdt_add_gem_nodes(s); - fdt_add_uart_nodes(s); fdt_add_canfd_nodes(s); fdt_add_gic_nodes(s); fdt_add_timer_nodes(s); fdt_add_zdma_nodes(s); fdt_add_usb_xhci_nodes(s); diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index fda8fdf786a..87468cbc291 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -24,18 +24,96 @@ #include "qemu/log.h" #include "target/arm/cpu-qom.h" #include "target/arm/gtimer.h" #include "system/device_tree.h" #include "hw/arm/fdt.h" +#include "hw/char/pl011.h" =20 #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") #define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f") #define GEM_REVISION 0x40070106 =20 #define VERSAL_NUM_PMC_APB_IRQS 18 #define NUM_OSPI_IRQ_LINES 3 =20 +typedef struct VersalSimplePeriphMap { + uint64_t addr; + int irq; +} VersalSimplePeriphMap; + +typedef struct VersalMap { + VersalSimplePeriphMap uart[2]; + size_t num_uart; +} VersalMap; + +static const VersalMap VERSAL_MAP =3D { + .uart[0] =3D { 0xff000000, 18 }, + .uart[1] =3D { 0xff010000, 19 }, + .num_uart =3D 2, +}; + +static const VersalMap *VERSION_TO_MAP[] =3D { + [VERSAL_VER_VERSAL] =3D &VERSAL_MAP, +}; + +static inline VersalVersion versal_get_version(Versal *s) +{ + return XLNX_VERSAL_BASE_GET_CLASS(s)->version; +} + +static inline const VersalMap *versal_get_map(Versal *s) +{ + return VERSION_TO_MAP[versal_get_version(s)]; +} + + +static qemu_irq versal_get_irq(Versal *s, int irq_idx) +{ + return qdev_get_gpio_in(DEVICE(&s->fpd.apu.gic), irq_idx); +} + +static void versal_sysbus_connect_irq(Versal *s, SysBusDevice *sbd, + int sbd_idx, int irq_idx) +{ + qemu_irq irq =3D versal_get_irq(s, irq_idx); + + if (irq =3D=3D NULL) { + return; + } + + sysbus_connect_irq(sbd, sbd_idx, irq); +} + +static inline char *versal_fdt_add_subnode(Versal *s, const char *path, + uint64_t at, const char *compat, + size_t compat_sz) +{ + char *p; + + p =3D g_strdup_printf("%s@%" PRIx64, path, at); + qemu_fdt_add_subnode(s->cfg.fdt, p); + + if (!strncmp(compat, "memory", compat_sz)) { + qemu_fdt_setprop(s->cfg.fdt, p, "device_type", compat, compat_sz); + } else { + qemu_fdt_setprop(s->cfg.fdt, p, "compatible", compat, compat_sz); + } + + return p; +} + +static inline char *versal_fdt_add_simple_subnode(Versal *s, const char *p= ath, + uint64_t addr, uint64_t = len, + const char *compat, + size_t compat_sz) +{ + char *p =3D versal_fdt_add_subnode(s, path, addr, compat, compat_sz); + + qemu_fdt_setprop_sized_cells(s->cfg.fdt, p, "reg", 2, addr, 2, len); + return p; +} + static void versal_create_apu_cpus(Versal *s) { int i; =20 object_initialize_child(OBJECT(s), "apu-cluster", &s->fpd.apu.cluster, @@ -165,32 +243,48 @@ static void versal_create_rpu_cpus(Versal *s) } =20 qdev_realize(DEVICE(&s->lpd.rpu.cluster), NULL, &error_fatal); } =20 -static void versal_create_uarts(Versal *s, qemu_irq *pic) +static void versal_create_uart(Versal *s, + const VersalSimplePeriphMap *map, + int chardev_idx) { - int i; + DeviceState *dev; + MemoryRegion *mr; + g_autofree char *node; + g_autofree char *alias; + const char compatible[] =3D "arm,pl011\0arm,sbsa-uart"; + const char clocknames[] =3D "uartclk\0apb_pclk"; =20 - for (i =3D 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) { - static const int irqs[] =3D { VERSAL_UART0_IRQ_0, VERSAL_UART1_IRQ= _0}; - static const uint64_t addrs[] =3D { MM_UART0, MM_UART1 }; - char *name =3D g_strdup_printf("uart%d", i); - DeviceState *dev; - MemoryRegion *mr; + dev =3D qdev_new(TYPE_PL011); + object_property_add_child(OBJECT(s), "uart[*]", OBJECT(dev)); + qdev_prop_set_chr(dev, "chardev", serial_hd(chardev_idx)); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); =20 - object_initialize_child(OBJECT(s), name, &s->lpd.iou.uart[i], - TYPE_PL011); - dev =3D DEVICE(&s->lpd.iou.uart[i]); - qdev_prop_set_chr(dev, "chardev", serial_hd(i)); - sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); + memory_region_add_subregion(&s->mr_ps, map->addr, mr); =20 - mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); - memory_region_add_subregion(&s->mr_ps, addrs[i], mr); + versal_sysbus_connect_irq(s, SYS_BUS_DEVICE(dev), 0, map->irq); =20 - sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]); - g_free(name); + node =3D versal_fdt_add_simple_subnode(s, "/uart", map->addr, 0x1000, + compatible, sizeof(compatible)); + qemu_fdt_setprop_cell(s->cfg.fdt, node, "current-speed", 115200); + qemu_fdt_setprop_cells(s->cfg.fdt, node, "clocks", + s->phandle.clk_125mhz, s->phandle.clk_125mhz); + qemu_fdt_setprop(s->cfg.fdt, node, "clock-names", clocknames, + sizeof(clocknames)); + qemu_fdt_setprop_cells(s->cfg.fdt, node, "interrupts", + GIC_FDT_IRQ_TYPE_SPI, map->irq, + GIC_FDT_IRQ_FLAGS_LEVEL_HI); + qemu_fdt_setprop(s->cfg.fdt, node, "u-boot,dm-pre-reloc", NULL, 0); + + alias =3D g_strdup_printf("serial%d", chardev_idx); + qemu_fdt_setprop_string(s->cfg.fdt, "/aliases", alias, node); + + if (chardev_idx =3D=3D 0) { + qemu_fdt_setprop_string(s->cfg.fdt, "/chosen", "stdout-path", node= ); } } =20 static void versal_create_canfds(Versal *s, qemu_irq *pic) { @@ -781,18 +875,10 @@ static void versal_create_crl(Versal *s, qemu_irq *pi= c) object_property_set_link(OBJECT(&s->lpd.crl), name, OBJECT(&s->lpd.iou.adma[i]), &error_abort); } =20 - for (i =3D 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) { - g_autofree gchar *name =3D g_strdup_printf("uart[%d]", i); - - object_property_set_link(OBJECT(&s->lpd.crl), - name, OBJECT(&s->lpd.iou.uart[i]), - &error_abort); - } - object_property_set_link(OBJECT(&s->lpd.crl), "usb", OBJECT(&s->lpd.iou.usb), &error_abort); =20 sysbus_realize(sbd, &error_fatal); @@ -940,10 +1026,12 @@ static uint32_t fdt_add_clk_node(Versal *s, const ch= ar *name, =20 static void versal_realize(DeviceState *dev, Error **errp) { Versal *s =3D XLNX_VERSAL_BASE(dev); qemu_irq pic[XLNX_VERSAL_NR_IRQS]; + const VersalMap *map =3D versal_get_map(s); + size_t i; =20 if (s->cfg.fdt =3D=3D NULL) { int fdt_size; =20 s->cfg.fdt =3D create_device_tree(&fdt_size); @@ -953,11 +1041,15 @@ static void versal_realize(DeviceState *dev, Error *= *errp) s->phandle.clk_125mhz =3D fdt_add_clk_node(s, "/clk125", 125 * 1000 * = 1000); =20 versal_create_apu_cpus(s); versal_create_apu_gic(s, pic); versal_create_rpu_cpus(s); - versal_create_uarts(s, pic); + + for (i =3D 0; i < map->num_uart; i++) { + versal_create_uart(s, &map->uart[i], i); + } + versal_create_canfds(s, pic); versal_create_usbs(s, pic); versal_create_gems(s, pic); versal_create_admas(s, pic); versal_create_sds(s, pic); --=20 2.50.1