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Iglesias" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , "Frederic Konrad" , Sai Pavan Boddu Subject: [PATCH v5 36/47] hw/misc/xlnx-versal-crl: add the versal2 version Date: Fri, 12 Sep 2025 12:00:45 +0200 Message-ID: <20250912100059.103997-37-luc.michel@amd.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250912100059.103997-1-luc.michel@amd.com> References: <20250912100059.103997-1-luc.michel@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099DB:EE_|SA1PR12MB8987:EE_ X-MS-Office365-Filtering-Correlation-Id: 013733b2-fc64-43b9-f06d-08ddf1e39639 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|1800799024|36860700013|376014; X-Microsoft-Antispam-Message-Info: =?utf-8?B?YVEzV0tWOGZYa2xDZ3VudDdYT2kwOXNINC8rM3Q3bFV1bjRRV3pYVUs2Rzhy?= =?utf-8?B?WG9iZGlKeHNoRlFTVEF5bUhVeWQveXVQakpHQjFmMnZDLzhDZzhFejFCRk1V?= =?utf-8?B?bkZKZW1lVmRISGNuN3FlOEVwbzFrTVpBdXdiZTNZUkh1MkxDOVBDZWFBcWxz?= =?utf-8?B?d28rMG80cmFXZmNoZlhZMjZEdlM1Y2pJYXlGMVZIR044WkpYWCtaaXcxLzNN?= =?utf-8?B?M2ZmQXQ1RGlEajBYOFpVRU1KN2ZQYUVXZUVQdXNwMUxKaGgreVFKNmJVaW9O?= =?utf-8?B?VFNwNGRrRGxSZkplblFKZ2l2bUlZQ1FlRFNqRXp3eGYwQ1JlQzZDSWRnMk5s?= =?utf-8?B?SWpFRnhwRXdsc2U1MTZSK1B3MlYrQjNqa2w0N1NUTklpVzVlY0Z0dE1LMklz?= =?utf-8?B?aFluckVBVHpoRE1qTkdiRVRYbkFhZVZERDk0NEFQbUxHc3BlMDZWWEU1Nkwr?= =?utf-8?B?OE5oVFRsNmt6WFNHYnYvd3RETmZtNm5lR2pSSHp4OEh0MVVtZjc3SElkamZy?= =?utf-8?B?UHdoSzAraU9Jc29BSHJKVUNjRXZCM0IyaTI4bUhna2E2WjhGK2xlWGwwSUNE?= =?utf-8?B?c0I1bHVTdWFuMzBCVFVvTmtucGMrVmRLZW9zQnBCd1QydVk2Y09Nc0NwUGVX?= =?utf-8?B?TU5tN3R4QXF5MjAvV09jaG5ZV2NMNXQvOHlKWHBwOUhBWkV4TWQzZWtRRE9B?= =?utf-8?B?c0JUQnI0dHFiZEZwa0syRmZSVG1lU3hva252RDJsaDNFYm5YbG5XU0txVWtK?= =?utf-8?B?cjBXcXJuU1JVMWlOd3JvSFUwL0JTL2dKVzZpNGE3b2V2bHIzSGdzcUNjelV4?= =?utf-8?B?VFFjU0E3VG9BTmxsRnlLREQvNGZ4NXo2TEhOZ2Z6YmdTSEgzQmZMZlIvQ01O?= =?utf-8?B?S3BJQ2ZhWjdSVmRIRE12dFRJdDNuNVZUNDI4ay9ZRElYeDhCcDBaNHBKMXl2?= =?utf-8?B?OGt6cUpJWEE2NldIUFNDU0xYTGptL3FPTlNEYzY3TGFiVEZVbGx5eWQ3Ynhw?= =?utf-8?B?aWhkR1hhQjhnemFOTXdQYS9QM1JSNG9TVzdPNm1IdGd5NCtYRFZWUHpFZmZW?= =?utf-8?B?QWZEc1M2eS9FVUFZN0EweTg0T2N4T3phekpkTlVKR0JJRXBTalYwcjVTQnlr?= =?utf-8?B?NWVReVFqbzg2MTAwNlNBUFB1TGVuWlM4WTNMR3Q0b0NrMHJEWVJqVnZZUmtJ?= =?utf-8?B?bzlGVENVdG1Odm5TNVZicU9aUDNFWVNUSndkbDF1NTdsQ2ZaUU1aMWFxd2pS?= =?utf-8?B?ZGs3enRiYnhacHJGckJMUnExT2JrSUFuRXdiUjJ0WVJwcUQzRWM1SGNNMys5?= =?utf-8?B?eCtyWTJIaDZTeE03VlJUb0FTSVRuSFFsQWZicmgvdnNtV0dvaVc5eG9tQTh6?= =?utf-8?B?TzhOTFNWTm56OGtaSmt3MnNEY3ArK3g2K1hjNlRFSHljYW5vV3NBdWJLV2xJ?= =?utf-8?B?ajUvckViNjUxVkVBa3BJenBqQWdwWC9CbHVJTGFvaCtQYndTMTFxTGx5RFV3?= =?utf-8?B?MXI4eDN2YzZuR2lBaE8zZWY0OUF4MGFJVzhubkZKYWdOQzhOMlNwdWlxcEEv?= =?utf-8?B?WUtrNHkyYVVaMHhPR2NzYUxaMEI1WmVJUDhNTmh4bGlmSXFUeDFYK1VubTRS?= =?utf-8?B?RHFJZjB2bWYydG51YUsvRFBFY1ZpSTcrdHE3TVFNY3dOa09jTkFYekZOUmhr?= =?utf-8?B?clh3bVRSR1lyekJCcWNBNjg3RkszdGxiT2xsWnIxSTdEK1NPUzgveE5OK2hP?= =?utf-8?B?c0ZXenVOWFR1YldPN1FnUWFHcUQvM1pTVk4yNWNrWkZzWEVZMENEdVh2dUxR?= =?utf-8?B?Q2xRWkM4U25NQXRiRlVvTGxQNUZkQXpKeXoyYW5YVjlDUFE3cnZxQVNmOGdt?= =?utf-8?B?cHFhN1l2YkdBb3FGdWpnc2pZSXlkcEFRQ2hzcnZpT1Eyelo3QlJmUUtsWnpC?= =?utf-8?B?Wm9nSndMQmJsTlNWZFlsRGMwMVRFVDh5VDl2OEJDbGFwSU5YSDRoUFgyWGdH?= =?utf-8?B?RHZWa0dTblFNbTVQbjNmbTRqaWNQajYrUVFXSTE5Ynp0aW1tc05qbEZPTEJN?= =?utf-8?Q?h6V9MG?= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:satlexmb07.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Sep 2025 10:03:13.5920 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 013733b2-fc64-43b9-f06d-08ddf1e39639 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DB.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8987 Received-SPF: permerror client-ip=2a01:111:f403:200a::628; envelope-from=Luc.Michel@amd.com; helo=NAM12-MW2-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1757672088072116600 Add the versal2 version of the CRL device. For the implemented part, it is similar to the versal version but drives reset line of more devices. Signed-off-by: Luc Michel Reviewed-by: Francisco Iglesias Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/arm/xlnx-versal-version.h | 1 + include/hw/misc/xlnx-versal-crl.h | 329 ++++++++++++++++++++++ hw/misc/xlnx-versal-crl.c | 392 +++++++++++++++++++++++++++ 3 files changed, 722 insertions(+) diff --git a/include/hw/arm/xlnx-versal-version.h b/include/hw/arm/xlnx-ver= sal-version.h index c4307d1304a..5b6b6e57a57 100644 --- a/include/hw/arm/xlnx-versal-version.h +++ b/include/hw/arm/xlnx-versal-version.h @@ -8,8 +8,9 @@ #ifndef HW_ARM_XLNX_VERSAL_VERSION_H #define HW_ARM_XLNX_VERSAL_VERSION_H =20 typedef enum VersalVersion { VERSAL_VER_VERSAL, + VERSAL_VER_VERSAL2, } VersalVersion; =20 #endif diff --git a/include/hw/misc/xlnx-versal-crl.h b/include/hw/misc/xlnx-versa= l-crl.h index 7e50a95ad3c..f6b8694ebea 100644 --- a/include/hw/misc/xlnx-versal-crl.h +++ b/include/hw/misc/xlnx-versal-crl.h @@ -15,14 +15,16 @@ #include "target/arm/cpu-qom.h" #include "hw/arm/xlnx-versal-version.h" =20 #define TYPE_XLNX_VERSAL_CRL_BASE "xlnx-versal-crl-base" #define TYPE_XLNX_VERSAL_CRL "xlnx-versal-crl" +#define TYPE_XLNX_VERSAL2_CRL "xlnx-versal2-crl" =20 OBJECT_DECLARE_TYPE(XlnxVersalCRLBase, XlnxVersalCRLBaseClass, XLNX_VERSAL_CRL_BASE) OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCRL, XLNX_VERSAL_CRL) +OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersal2CRL, XLNX_VERSAL2_CRL) =20 REG32(ERR_CTRL, 0x0) FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1) REG32(IR_STATUS, 0x4) FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1) @@ -218,10 +220,318 @@ REG32(PSM_RST_MODE, 0x370) FIELD(PSM_RST_MODE, WAKEUP, 2, 1) FIELD(PSM_RST_MODE, RST_MODE, 0, 2) =20 #define CRL_R_MAX (R_PSM_RST_MODE + 1) =20 +REG32(VERSAL2_ERR_CTRL, 0x0) +REG32(VERSAL2_WPROT, 0x1c) + FIELD(VERSAL2_WPROT, ACTIVE, 0, 1) +REG32(VERSAL2_RPLL_CTRL, 0x40) + FIELD(VERSAL2_RPLL_CTRL, POST_SRC, 24, 3) + FIELD(VERSAL2_RPLL_CTRL, PRE_SRC, 20, 3) + FIELD(VERSAL2_RPLL_CTRL, CLKOUTDIV, 16, 2) + FIELD(VERSAL2_RPLL_CTRL, FBDIV, 8, 8) + FIELD(VERSAL2_RPLL_CTRL, BYPASS, 3, 1) + FIELD(VERSAL2_RPLL_CTRL, RESET, 0, 1) +REG32(VERSAL2_RPLL_CFG, 0x44) + FIELD(VERSAL2_RPLL_CFG, LOCK_DLY, 25, 7) + FIELD(VERSAL2_RPLL_CFG, LOCK_CNT, 13, 10) + FIELD(VERSAL2_RPLL_CFG, LFHF, 10, 2) + FIELD(VERSAL2_RPLL_CFG, CP, 5, 4) + FIELD(VERSAL2_RPLL_CFG, RES, 0, 4) +REG32(VERSAL2_FLXPLL_CTRL, 0x50) + FIELD(VERSAL2_FLXPLL_CTRL, POST_SRC, 24, 3) + FIELD(VERSAL2_FLXPLL_CTRL, PRE_SRC, 20, 3) + FIELD(VERSAL2_FLXPLL_CTRL, CLKOUTDIV, 16, 2) + FIELD(VERSAL2_FLXPLL_CTRL, FBDIV, 8, 8) + FIELD(VERSAL2_FLXPLL_CTRL, BYPASS, 3, 1) + FIELD(VERSAL2_FLXPLL_CTRL, RESET, 0, 1) +REG32(VERSAL2_FLXPLL_CFG, 0x54) + FIELD(VERSAL2_FLXPLL_CFG, LOCK_DLY, 25, 7) + FIELD(VERSAL2_FLXPLL_CFG, LOCK_CNT, 13, 10) + FIELD(VERSAL2_FLXPLL_CFG, LFHF, 10, 2) + FIELD(VERSAL2_FLXPLL_CFG, CP, 5, 4) + FIELD(VERSAL2_FLXPLL_CFG, RES, 0, 4) +REG32(VERSAL2_PLL_STATUS, 0x60) + FIELD(VERSAL2_PLL_STATUS, FLXPLL_STABLE, 3, 1) + FIELD(VERSAL2_PLL_STATUS, RPLL_STABLE, 2, 1) + FIELD(VERSAL2_PLL_STATUS, FLXPLL_LOCK, 1, 1) + FIELD(VERSAL2_PLL_STATUS, RPLL_LOCK, 0, 1) +REG32(VERSAL2_RPLL_TO_XPD_CTRL, 0x100) + FIELD(VERSAL2_RPLL_TO_XPD_CTRL, DIVISOR0, 8, 10) +REG32(VERSAL2_LPX_TOP_SWITCH_CTRL, 0x104) + FIELD(VERSAL2_LPX_TOP_SWITCH_CTRL, CLKACT_ADMA, 26, 1) + FIELD(VERSAL2_LPX_TOP_SWITCH_CTRL, CLKACT, 25, 1) + FIELD(VERSAL2_LPX_TOP_SWITCH_CTRL, DIVISOR0, 8, 10) + FIELD(VERSAL2_LPX_TOP_SWITCH_CTRL, SRCSEL, 0, 3) +REG32(VERSAL2_LPX_LSBUS_CLK_CTRL, 0x108) + FIELD(VERSAL2_LPX_LSBUS_CLK_CTRL, CLKACT, 25, 1) + FIELD(VERSAL2_LPX_LSBUS_CLK_CTRL, DIVISOR0, 8, 10) + FIELD(VERSAL2_LPX_LSBUS_CLK_CTRL, SRCSEL, 0, 3) +REG32(VERSAL2_RPU_CLK_CTRL, 0x10c) + FIELD(VERSAL2_RPU_CLK_CTRL, CLKACT, 25, 1) + FIELD(VERSAL2_RPU_CLK_CTRL, CLKACT_CLUSTERE, 24, 1) + FIELD(VERSAL2_RPU_CLK_CTRL, CLKACT_CLUSTERD, 23, 1) + FIELD(VERSAL2_RPU_CLK_CTRL, CLKACT_CLUSTERC, 22, 1) + FIELD(VERSAL2_RPU_CLK_CTRL, CLKACT_CLUSTERB, 21, 1) + FIELD(VERSAL2_RPU_CLK_CTRL, CLKACT_CLUSTERA, 20, 1) + FIELD(VERSAL2_RPU_CLK_CTRL, DIVISOR0, 8, 10) + FIELD(VERSAL2_RPU_CLK_CTRL, SRCSEL, 0, 3) +REG32(VERSAL2_OCM_CLK_CTRL, 0x120) + FIELD(VERSAL2_OCM_CLK_CTRL, CLKACT_OCM3, 24, 1) + FIELD(VERSAL2_OCM_CLK_CTRL, CLKACT_OCM2, 23, 1) + FIELD(VERSAL2_OCM_CLK_CTRL, CLKACT_OCM1, 22, 1) + FIELD(VERSAL2_OCM_CLK_CTRL, CLKACT_OCM0, 21, 1) +REG32(VERSAL2_IOU_SWITCH_CLK_CTRL, 0x124) + FIELD(VERSAL2_IOU_SWITCH_CLK_CTRL, CLKACT, 25, 1) + FIELD(VERSAL2_IOU_SWITCH_CLK_CTRL, DIVISOR0, 8, 10) + FIELD(VERSAL2_IOU_SWITCH_CLK_CTRL, SRCSEL, 0, 3) +REG32(VERSAL2_GEM0_REF_CTRL, 0x128) + FIELD(VERSAL2_GEM0_REF_CTRL, CLKACT_RX, 27, 1) + FIELD(VERSAL2_GEM0_REF_CTRL, CLKACT_TX, 26, 1) + FIELD(VERSAL2_GEM0_REF_CTRL, CLKACT, 25, 1) + FIELD(VERSAL2_GEM0_REF_CTRL, DIVISOR0, 8, 10) + FIELD(VERSAL2_GEM0_REF_CTRL, SRCSEL, 0, 3) +REG32(VERSAL2_GEM1_REF_CTRL, 0x12c) + FIELD(VERSAL2_GEM1_REF_CTRL, CLKACT_RX, 27, 1) + FIELD(VERSAL2_GEM1_REF_CTRL, CLKACT_TX, 26, 1) + FIELD(VERSAL2_GEM1_REF_CTRL, CLKACT, 25, 1) + FIELD(VERSAL2_GEM1_REF_CTRL, DIVISOR0, 8, 10) + FIELD(VERSAL2_GEM1_REF_CTRL, SRCSEL, 0, 3) +REG32(VERSAL2_GEM_TSU_REF_CLK_CTRL, 0x130) + FIELD(VERSAL2_GEM_TSU_REF_CLK_CTRL, CLKACT, 25, 1) + FIELD(VERSAL2_GEM_TSU_REF_CLK_CTRL, DIVISOR0, 8, 10) + FIELD(VERSAL2_GEM_TSU_REF_CLK_CTRL, SRCSEL, 0, 3) +REG32(VERSAL2_USB0_BUS_REF_CLK_CTRL, 0x134) + FIELD(VERSAL2_USB0_BUS_REF_CLK_CTRL, CLKACT, 25, 1) + FIELD(VERSAL2_USB0_BUS_REF_CLK_CTRL, DIVISOR0, 8, 10) + FIELD(VERSAL2_USB0_BUS_REF_CLK_CTRL, SRCSEL, 0, 3) +REG32(VERSAL2_USB1_BUS_REF_CLK_CTRL, 0x138) + FIELD(VERSAL2_USB1_BUS_REF_CLK_CTRL, CLKACT, 25, 1) + FIELD(VERSAL2_USB1_BUS_REF_CLK_CTRL, DIVISOR0, 8, 10) + FIELD(VERSAL2_USB1_BUS_REF_CLK_CTRL, SRCSEL, 0, 3) +REG32(VERSAL2_UART0_REF_CLK_CTRL, 0x13c) + FIELD(VERSAL2_UART0_REF_CLK_CTRL, CLKACT, 25, 1) + FIELD(VERSAL2_UART0_REF_CLK_CTRL, DIVISOR0, 8, 10) + FIELD(VERSAL2_UART0_REF_CLK_CTRL, SRCSEL, 0, 3) +REG32(VERSAL2_UART1_REF_CLK_CTRL, 0x140) + FIELD(VERSAL2_UART1_REF_CLK_CTRL, CLKACT, 25, 1) + FIELD(VERSAL2_UART1_REF_CLK_CTRL, DIVISOR0, 8, 10) + FIELD(VERSAL2_UART1_REF_CLK_CTRL, SRCSEL, 0, 3) +REG32(VERSAL2_SPI0_REF_CLK_CTRL, 0x144) + FIELD(VERSAL2_SPI0_REF_CLK_CTRL, CLKACT, 25, 1) + FIELD(VERSAL2_SPI0_REF_CLK_CTRL, DIVISOR0, 8, 10) + FIELD(VERSAL2_SPI0_REF_CLK_CTRL, SRCSEL, 0, 3) +REG32(VERSAL2_SPI1_REF_CLK_CTRL, 0x148) + FIELD(VERSAL2_SPI1_REF_CLK_CTRL, CLKACT, 25, 1) + FIELD(VERSAL2_SPI1_REF_CLK_CTRL, DIVISOR0, 8, 10) + FIELD(VERSAL2_SPI1_REF_CLK_CTRL, SRCSEL, 0, 3) +REG32(VERSAL2_CAN0_REF_2X_CTRL, 0x14c) + FIELD(VERSAL2_CAN0_REF_2X_CTRL, CLKACT, 25, 1) + FIELD(VERSAL2_CAN0_REF_2X_CTRL, DIVISOR0, 8, 10) + FIELD(VERSAL2_CAN0_REF_2X_CTRL, SRCSEL, 0, 3) +REG32(VERSAL2_CAN1_REF_2X_CTRL, 0x150) + FIELD(VERSAL2_CAN1_REF_2X_CTRL, CLKACT, 25, 1) + FIELD(VERSAL2_CAN1_REF_2X_CTRL, DIVISOR0, 8, 10) + FIELD(VERSAL2_CAN1_REF_2X_CTRL, SRCSEL, 0, 3) +REG32(VERSAL2_CAN2_REF_2X_CTRL, 0x154) + FIELD(VERSAL2_CAN2_REF_2X_CTRL, CLKACT, 25, 1) + FIELD(VERSAL2_CAN2_REF_2X_CTRL, DIVISOR0, 8, 10) + FIELD(VERSAL2_CAN2_REF_2X_CTRL, SRCSEL, 0, 3) +REG32(VERSAL2_CAN3_REF_2X_CTRL, 0x158) + FIELD(VERSAL2_CAN3_REF_2X_CTRL, CLKACT, 25, 1) + FIELD(VERSAL2_CAN3_REF_2X_CTRL, DIVISOR0, 8, 10) + FIELD(VERSAL2_CAN3_REF_2X_CTRL, SRCSEL, 0, 3) +REG32(VERSAL2_I3C0_REF_CTRL, 0x15c) + FIELD(VERSAL2_I3C0_REF_CTRL, CLKACT, 25, 1) + FIELD(VERSAL2_I3C0_REF_CTRL, DIVISOR0, 8, 10) + FIELD(VERSAL2_I3C0_REF_CTRL, SRCSEL, 0, 3) +REG32(VERSAL2_I3C1_REF_CTRL, 0x160) + FIELD(VERSAL2_I3C1_REF_CTRL, CLKACT, 25, 1) + FIELD(VERSAL2_I3C1_REF_CTRL, DIVISOR0, 8, 10) + FIELD(VERSAL2_I3C1_REF_CTRL, SRCSEL, 0, 3) +REG32(VERSAL2_I3C2_REF_CTRL, 0x164) + FIELD(VERSAL2_I3C2_REF_CTRL, CLKACT, 25, 1) + FIELD(VERSAL2_I3C2_REF_CTRL, DIVISOR0, 8, 10) + FIELD(VERSAL2_I3C2_REF_CTRL, SRCSEL, 0, 3) +REG32(VERSAL2_I3C3_REF_CTRL, 0x168) + FIELD(VERSAL2_I3C3_REF_CTRL, CLKACT, 25, 1) + FIELD(VERSAL2_I3C3_REF_CTRL, DIVISOR0, 8, 10) + FIELD(VERSAL2_I3C3_REF_CTRL, SRCSEL, 0, 3) +REG32(VERSAL2_I3C4_REF_CTRL, 0x16c) + FIELD(VERSAL2_I3C4_REF_CTRL, CLKACT, 25, 1) + FIELD(VERSAL2_I3C4_REF_CTRL, DIVISOR0, 8, 10) + FIELD(VERSAL2_I3C4_REF_CTRL, SRCSEL, 0, 3) +REG32(VERSAL2_I3C5_REF_CTRL, 0x170) + FIELD(VERSAL2_I3C5_REF_CTRL, CLKACT, 25, 1) + FIELD(VERSAL2_I3C5_REF_CTRL, DIVISOR0, 8, 10) + FIELD(VERSAL2_I3C5_REF_CTRL, SRCSEL, 0, 3) +REG32(VERSAL2_I3C6_REF_CTRL, 0x174) + FIELD(VERSAL2_I3C6_REF_CTRL, CLKACT, 25, 1) + FIELD(VERSAL2_I3C6_REF_CTRL, DIVISOR0, 8, 10) + FIELD(VERSAL2_I3C6_REF_CTRL, SRCSEL, 0, 3) +REG32(VERSAL2_I3C7_REF_CTRL, 0x178) + FIELD(VERSAL2_I3C7_REF_CTRL, CLKACT, 25, 1) + FIELD(VERSAL2_I3C7_REF_CTRL, DIVISOR0, 8, 10) + FIELD(VERSAL2_I3C7_REF_CTRL, SRCSEL, 0, 3) +REG32(VERSAL2_DBG_LPX_CTRL, 0x17c) + FIELD(VERSAL2_DBG_LPX_CTRL, CLKACT, 25, 1) + FIELD(VERSAL2_DBG_LPX_CTRL, DIVISOR0, 8, 10) + FIELD(VERSAL2_DBG_LPX_CTRL, SRCSEL, 0, 3) +REG32(VERSAL2_TIMESTAMP_REF_CTRL, 0x180) + FIELD(VERSAL2_TIMESTAMP_REF_CTRL, CLKACT, 25, 1) + FIELD(VERSAL2_TIMESTAMP_REF_CTRL, DIVISOR0, 8, 10) + FIELD(VERSAL2_TIMESTAMP_REF_CTRL, SRCSEL, 0, 3) +REG32(VERSAL2_SAFETY_CHK, 0x184) +REG32(VERSAL2_ASU_CLK_CTRL, 0x188) + FIELD(VERSAL2_ASU_CLK_CTRL, DIVISOR0, 8, 10) + FIELD(VERSAL2_ASU_CLK_CTRL, SRCSEL, 0, 3) +REG32(VERSAL2_DBG_TSTMP_CLK_CTRL, 0x18c) + FIELD(VERSAL2_DBG_TSTMP_CLK_CTRL, CLKACT, 25, 1) + FIELD(VERSAL2_DBG_TSTMP_CLK_CTRL, DIVISOR0, 8, 10) + FIELD(VERSAL2_DBG_TSTMP_CLK_CTRL, SRCSEL, 0, 3) +REG32(VERSAL2_MMI_TOPSW_CLK_CTRL, 0x190) + FIELD(VERSAL2_MMI_TOPSW_CLK_CTRL, CLKACT, 25, 1) + FIELD(VERSAL2_MMI_TOPSW_CLK_CTRL, DIVISOR0, 8, 10) + FIELD(VERSAL2_MMI_TOPSW_CLK_CTRL, SRCSEL, 0, 3) +REG32(VERSAL2_WWDT_PLL_CLK_CTRL, 0x194) + FIELD(VERSAL2_WWDT_PLL_CLK_CTRL, DIVISOR0, 8, 10) + FIELD(VERSAL2_WWDT_PLL_CLK_CTRL, SRCSEL, 0, 3) +REG32(VERSAL2_RCLK_CTRL, 0x1a0) + FIELD(VERSAL2_RCLK_CTRL, CLKACT, 8, 6) + FIELD(VERSAL2_RCLK_CTRL, SELECT, 0, 6) +REG32(VERSAL2_RST_RPU_A, 0x310) + FIELD(VERSAL2_RST_RPU_A, TOPRESET, 16, 1) + FIELD(VERSAL2_RST_RPU_A, CORE1_POR, 9, 1) + FIELD(VERSAL2_RST_RPU_A, CORE0_POR, 8, 1) + FIELD(VERSAL2_RST_RPU_A, CORE1_RESET, 1, 1) + FIELD(VERSAL2_RST_RPU_A, CORE0_RESET, 0, 1) +REG32(VERSAL2_RST_RPU_B, 0x314) + FIELD(VERSAL2_RST_RPU_B, TOPRESET, 16, 1) + FIELD(VERSAL2_RST_RPU_B, CORE1_POR, 9, 1) + FIELD(VERSAL2_RST_RPU_B, CORE0_POR, 8, 1) + FIELD(VERSAL2_RST_RPU_B, CORE1_RESET, 1, 1) + FIELD(VERSAL2_RST_RPU_B, CORE0_RESET, 0, 1) +REG32(VERSAL2_RST_RPU_C, 0x318) + FIELD(VERSAL2_RST_RPU_C, TOPRESET, 16, 1) + FIELD(VERSAL2_RST_RPU_C, CORE1_POR, 9, 1) + FIELD(VERSAL2_RST_RPU_C, CORE0_POR, 8, 1) + FIELD(VERSAL2_RST_RPU_C, CORE1_RESET, 1, 1) + FIELD(VERSAL2_RST_RPU_C, CORE0_RESET, 0, 1) +REG32(VERSAL2_RST_RPU_D, 0x31c) + FIELD(VERSAL2_RST_RPU_D, TOPRESET, 16, 1) + FIELD(VERSAL2_RST_RPU_D, CORE1_POR, 9, 1) + FIELD(VERSAL2_RST_RPU_D, CORE0_POR, 8, 1) + FIELD(VERSAL2_RST_RPU_D, CORE1_RESET, 1, 1) + FIELD(VERSAL2_RST_RPU_D, CORE0_RESET, 0, 1) +REG32(VERSAL2_RST_RPU_E, 0x320) + FIELD(VERSAL2_RST_RPU_E, TOPRESET, 16, 1) + FIELD(VERSAL2_RST_RPU_E, CORE1_POR, 9, 1) + FIELD(VERSAL2_RST_RPU_E, CORE0_POR, 8, 1) + FIELD(VERSAL2_RST_RPU_E, CORE1_RESET, 1, 1) + FIELD(VERSAL2_RST_RPU_E, CORE0_RESET, 0, 1) +REG32(VERSAL2_RST_RPU_GD_0, 0x324) + FIELD(VERSAL2_RST_RPU_GD_0, RESET, 1, 1) + FIELD(VERSAL2_RST_RPU_GD_0, TOP_RESET, 0, 1) +REG32(VERSAL2_RST_RPU_GD_1, 0x328) + FIELD(VERSAL2_RST_RPU_GD_1, RESET, 1, 1) + FIELD(VERSAL2_RST_RPU_GD_1, TOP_RESET, 0, 1) +REG32(VERSAL2_RST_ASU_GD, 0x32c) + FIELD(VERSAL2_RST_ASU_GD, RESET, 1, 1) + FIELD(VERSAL2_RST_ASU_GD, TOP_RESET, 0, 1) +REG32(VERSAL2_RST_ADMA, 0x334) + FIELD(VERSAL2_RST_ADMA, RESET, 0, 1) +REG32(VERSAL2_RST_SDMA, 0x338) + FIELD(VERSAL2_RST_SDMA, RESET, 0, 1) +REG32(VERSAL2_RST_GEM0, 0x33c) + FIELD(VERSAL2_RST_GEM0, RESET, 0, 1) +REG32(VERSAL2_RST_GEM1, 0x340) + FIELD(VERSAL2_RST_GEM1, RESET, 0, 1) +REG32(VERSAL2_RST_USB0, 0x348) + FIELD(VERSAL2_RST_USB0, RESET, 0, 1) +REG32(VERSAL2_RST_USB1, 0x34c) + FIELD(VERSAL2_RST_USB1, RESET, 0, 1) +REG32(VERSAL2_RST_UART0, 0x350) + FIELD(VERSAL2_RST_UART0, RESET, 0, 1) +REG32(VERSAL2_RST_UART1, 0x354) + FIELD(VERSAL2_RST_UART1, RESET, 0, 1) +REG32(VERSAL2_RST_SPI0, 0x358) + FIELD(VERSAL2_RST_SPI0, RESET, 0, 1) +REG32(VERSAL2_RST_SPI1, 0x35c) + FIELD(VERSAL2_RST_SPI1, RESET, 0, 1) +REG32(VERSAL2_RST_CAN0, 0x360) + FIELD(VERSAL2_RST_CAN0, RESET, 0, 1) +REG32(VERSAL2_RST_CAN1, 0x364) + FIELD(VERSAL2_RST_CAN1, RESET, 0, 1) +REG32(VERSAL2_RST_CAN2, 0x368) + FIELD(VERSAL2_RST_CAN2, RESET, 0, 1) +REG32(VERSAL2_RST_CAN3, 0x36c) + FIELD(VERSAL2_RST_CAN3, RESET, 0, 1) +REG32(VERSAL2_RST_I3C0, 0x374) + FIELD(VERSAL2_RST_I3C0, RESET, 0, 1) +REG32(VERSAL2_RST_I3C1, 0x378) + FIELD(VERSAL2_RST_I3C1, RESET, 0, 1) +REG32(VERSAL2_RST_I3C2, 0x37c) + FIELD(VERSAL2_RST_I3C2, RESET, 0, 1) +REG32(VERSAL2_RST_I3C3, 0x380) + FIELD(VERSAL2_RST_I3C3, RESET, 0, 1) +REG32(VERSAL2_RST_I3C4, 0x384) + FIELD(VERSAL2_RST_I3C4, RESET, 0, 1) +REG32(VERSAL2_RST_I3C5, 0x388) + FIELD(VERSAL2_RST_I3C5, RESET, 0, 1) +REG32(VERSAL2_RST_I3C6, 0x38c) + FIELD(VERSAL2_RST_I3C6, RESET, 0, 1) +REG32(VERSAL2_RST_I3C7, 0x390) + FIELD(VERSAL2_RST_I3C7, RESET, 0, 1) +REG32(VERSAL2_RST_DBG_LPX, 0x398) + FIELD(VERSAL2_RST_DBG_LPX, RESET_HSDP, 1, 1) + FIELD(VERSAL2_RST_DBG_LPX, RESET, 0, 1) +REG32(VERSAL2_RST_GPIO, 0x39c) + FIELD(VERSAL2_RST_GPIO, RESET, 0, 1) +REG32(VERSAL2_RST_TTC, 0x3a0) + FIELD(VERSAL2_RST_TTC, TTC7_RESET, 7, 1) + FIELD(VERSAL2_RST_TTC, TTC6_RESET, 6, 1) + FIELD(VERSAL2_RST_TTC, TTC5_RESET, 5, 1) + FIELD(VERSAL2_RST_TTC, TTC4_RESET, 4, 1) + FIELD(VERSAL2_RST_TTC, TTC3_RESET, 3, 1) + FIELD(VERSAL2_RST_TTC, TTC2_RESET, 2, 1) + FIELD(VERSAL2_RST_TTC, TTC1_RESET, 1, 1) + FIELD(VERSAL2_RST_TTC, TTC0_RESET, 0, 1) +REG32(VERSAL2_RST_TIMESTAMP, 0x3a4) + FIELD(VERSAL2_RST_TIMESTAMP, RESET, 0, 1) +REG32(VERSAL2_RST_SWDT0, 0x3a8) + FIELD(VERSAL2_RST_SWDT0, RESET, 0, 1) +REG32(VERSAL2_RST_SWDT1, 0x3ac) + FIELD(VERSAL2_RST_SWDT1, RESET, 0, 1) +REG32(VERSAL2_RST_SWDT2, 0x3b0) + FIELD(VERSAL2_RST_SWDT2, RESET, 0, 1) +REG32(VERSAL2_RST_SWDT3, 0x3b4) + FIELD(VERSAL2_RST_SWDT3, RESET, 0, 1) +REG32(VERSAL2_RST_SWDT4, 0x3b8) + FIELD(VERSAL2_RST_SWDT4, RESET, 0, 1) +REG32(VERSAL2_RST_IPI, 0x3bc) + FIELD(VERSAL2_RST_IPI, RESET, 0, 1) +REG32(VERSAL2_RST_SYSMON, 0x3c0) + FIELD(VERSAL2_RST_SYSMON, CFG_RST, 0, 1) +REG32(VERSAL2_ASU_MB_RST_MODE, 0x3c4) + FIELD(VERSAL2_ASU_MB_RST_MODE, WAKEUP, 2, 1) + FIELD(VERSAL2_ASU_MB_RST_MODE, RST_MODE, 0, 2) +REG32(VERSAL2_FPX_TOPSW_MUX_CTRL, 0x3c8) + FIELD(VERSAL2_FPX_TOPSW_MUX_CTRL, SELECT, 0, 1) +REG32(VERSAL2_RST_FPX, 0x3d0) + FIELD(VERSAL2_RST_FPX, SRST, 1, 1) + FIELD(VERSAL2_RST_FPX, POR, 0, 1) +REG32(VERSAL2_RST_MMI, 0x3d4) + FIELD(VERSAL2_RST_MMI, POR, 0, 1) +REG32(VERSAL2_RST_OCM, 0x3d8) + FIELD(VERSAL2_RST_OCM, RESET_OCM3, 3, 1) + FIELD(VERSAL2_RST_OCM, RESET_OCM2, 2, 1) + FIELD(VERSAL2_RST_OCM, RESET_OCM1, 1, 1) + FIELD(VERSAL2_RST_OCM, RESET_OCM0, 0, 1) + +#define VERSAL2_CRL_R_MAX (R_VERSAL2_RST_OCM + 1) + struct XlnxVersalCRLBase { SysBusDevice parent_obj; =20 RegisterInfoArray *reg_array; uint32_t *regs; @@ -247,15 +557,34 @@ struct XlnxVersalCRL { =20 uint32_t regs[CRL_R_MAX]; RegisterInfo regs_info[CRL_R_MAX]; }; =20 +struct XlnxVersal2CRL { + XlnxVersalCRLBase parent_obj; + + struct { + DeviceState *rpu[10]; + DeviceState *adma[8]; + DeviceState *sdma[8]; + DeviceState *uart[2]; + DeviceState *gem[2]; + DeviceState *usb[2]; + DeviceState *can[4]; + } cfg; + + RegisterInfo regs_info[VERSAL2_CRL_R_MAX]; + uint32_t regs[VERSAL2_CRL_R_MAX]; +}; + static inline const char *xlnx_versal_crl_class_name(VersalVersion ver) { switch (ver) { case VERSAL_VER_VERSAL: return TYPE_XLNX_VERSAL_CRL; + case VERSAL_VER_VERSAL2: + return TYPE_XLNX_VERSAL2_CRL; default: g_assert_not_reached(); } } =20 diff --git a/hw/misc/xlnx-versal-crl.c b/hw/misc/xlnx-versal-crl.c index 6225a92e0bd..10e6af002ba 100644 --- a/hw/misc/xlnx-versal-crl.c +++ b/hw/misc/xlnx-versal-crl.c @@ -81,10 +81,55 @@ static DeviceState **versal_decode_periph_rst(XlnxVersa= lCRLBase *s, return xvc->cfg.gem + idx; =20 case A_RST_USB0: return xvc->cfg.usb; =20 + default: + /* invalid or unimplemented */ + g_assert_not_reached(); + } +} + +static DeviceState **versal2_decode_periph_rst(XlnxVersalCRLBase *s, + hwaddr addr, size_t *count) +{ + size_t idx; + XlnxVersal2CRL *xvc =3D XLNX_VERSAL2_CRL(s); + + *count =3D 1; + + switch (addr) { + case A_VERSAL2_RST_RPU_A ... A_VERSAL2_RST_RPU_E: + idx =3D (addr - A_VERSAL2_RST_RPU_A) / sizeof(uint32_t); + idx *=3D 2; /* two RPUs per RST_RPU_x registers */ + return xvc->cfg.rpu + idx; + + case A_VERSAL2_RST_ADMA: + /* A single register fans out to all DMA reset inputs */ + *count =3D ARRAY_SIZE(xvc->cfg.adma); + return xvc->cfg.adma; + + case A_VERSAL2_RST_SDMA: + *count =3D ARRAY_SIZE(xvc->cfg.sdma); + return xvc->cfg.sdma; + + case A_VERSAL2_RST_UART0 ... A_VERSAL2_RST_UART1: + idx =3D (addr - A_VERSAL2_RST_UART0) / sizeof(uint32_t); + return xvc->cfg.uart + idx; + + case A_VERSAL2_RST_GEM0 ... A_VERSAL2_RST_GEM1: + idx =3D (addr - A_VERSAL2_RST_GEM0) / sizeof(uint32_t); + return xvc->cfg.gem + idx; + + case A_VERSAL2_RST_USB0 ... A_VERSAL2_RST_USB1: + idx =3D (addr - A_VERSAL2_RST_USB0) / sizeof(uint32_t); + return xvc->cfg.usb + idx; + + case A_VERSAL2_RST_CAN0 ... A_VERSAL2_RST_CAN3: + idx =3D (addr - A_VERSAL2_RST_CAN0) / sizeof(uint32_t); + return xvc->cfg.can + idx; + default: /* invalid or unimplemented */ return NULL; } } @@ -305,20 +350,270 @@ static const RegisterAccessInfo crl_regs_info[] =3D { .reset =3D 0x1, .rsvd =3D 0xf8, } }; =20 +static const RegisterAccessInfo versal2_crl_regs_info[] =3D { + { .name =3D "ERR_CTRL", .addr =3D A_VERSAL2_ERR_CTRL, + .reset =3D 0x1, + },{ .name =3D "WPROT", .addr =3D A_VERSAL2_WPROT, + },{ .name =3D "RPLL_CTRL", .addr =3D A_VERSAL2_RPLL_CTRL, + .reset =3D 0x24809, + .rsvd =3D 0xf88c00f6, + },{ .name =3D "RPLL_CFG", .addr =3D A_VERSAL2_RPLL_CFG, + .reset =3D 0x7e5dcc6c, + .rsvd =3D 0x1801210, + },{ .name =3D "FLXPLL_CTRL", .addr =3D A_VERSAL2_FLXPLL_CTRL, + .reset =3D 0x24809, + .rsvd =3D 0xf88c00f6, + },{ .name =3D "FLXPLL_CFG", .addr =3D A_VERSAL2_FLXPLL_CFG, + .reset =3D 0x7e5dcc6c, + .rsvd =3D 0x1801210, + },{ .name =3D "PLL_STATUS", .addr =3D A_VERSAL2_PLL_STATUS, + .reset =3D 0xf, + .rsvd =3D 0xf0, + .ro =3D 0xf, + },{ .name =3D "RPLL_TO_XPD_CTRL", .addr =3D A_VERSAL2_RPLL_TO_XPD_CTR= L, + .reset =3D 0x2000100, + .rsvd =3D 0xfdfc00ff, + },{ .name =3D "LPX_TOP_SWITCH_CTRL", .addr =3D A_VERSAL2_LPX_TOP_SWIT= CH_CTRL, + .reset =3D 0xe000300, + .rsvd =3D 0xf1fc00f8, + },{ .name =3D "LPX_LSBUS_CLK_CTRL", .addr =3D A_VERSAL2_LPX_LSBUS_CLK= _CTRL, + .reset =3D 0x2000800, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "RPU_CLK_CTRL", .addr =3D A_VERSAL2_RPU_CLK_CTRL, + .reset =3D 0x3f00300, + .rsvd =3D 0xfc0c00f8, + },{ .name =3D "OCM_CLK_CTRL", .addr =3D A_VERSAL2_OCM_CLK_CTRL, + .reset =3D 0x1e00000, + .rsvd =3D 0xfe1fffff, + },{ .name =3D "IOU_SWITCH_CLK_CTRL", .addr =3D A_VERSAL2_IOU_SWITCH_C= LK_CTRL, + .reset =3D 0x2000500, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "GEM0_REF_CTRL", .addr =3D A_VERSAL2_GEM0_REF_CTRL, + .reset =3D 0xe000a00, + .rsvd =3D 0xf1fc00f8, + },{ .name =3D "GEM1_REF_CTRL", .addr =3D A_VERSAL2_GEM1_REF_CTRL, + .reset =3D 0xe000a00, + .rsvd =3D 0xf1fc00f8, + },{ .name =3D "GEM_TSU_REF_CLK_CTRL", .addr =3D A_VERSAL2_GEM_TSU_REF= _CLK_CTRL, + .reset =3D 0x300, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "USB0_BUS_REF_CLK_CTRL", + .addr =3D A_VERSAL2_USB0_BUS_REF_CLK_CTRL, + .reset =3D 0x2001900, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "USB1_BUS_REF_CLK_CTRL", + .addr =3D A_VERSAL2_USB1_BUS_REF_CLK_CTRL, + .reset =3D 0x2001900, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "UART0_REF_CLK_CTRL", .addr =3D A_VERSAL2_UART0_REF_CLK= _CTRL, + .reset =3D 0xc00, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "UART1_REF_CLK_CTRL", .addr =3D A_VERSAL2_UART1_REF_CLK= _CTRL, + .reset =3D 0xc00, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "SPI0_REF_CLK_CTRL", .addr =3D A_VERSAL2_SPI0_REF_CLK_C= TRL, + .reset =3D 0x600, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "SPI1_REF_CLK_CTRL", .addr =3D A_VERSAL2_SPI1_REF_CLK_C= TRL, + .reset =3D 0x600, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "CAN0_REF_2X_CTRL", .addr =3D A_VERSAL2_CAN0_REF_2X_CTR= L, + .reset =3D 0xc00, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "CAN1_REF_2X_CTRL", .addr =3D A_VERSAL2_CAN1_REF_2X_CTR= L, + .reset =3D 0xc00, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "CAN2_REF_2X_CTRL", .addr =3D A_VERSAL2_CAN2_REF_2X_CTR= L, + .reset =3D 0xc00, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "CAN3_REF_2X_CTRL", .addr =3D A_VERSAL2_CAN3_REF_2X_CTR= L, + .reset =3D 0xc00, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "I3C0_REF_CTRL", .addr =3D A_VERSAL2_I3C0_REF_CTRL, + .reset =3D 0x2000c00, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "I3C1_REF_CTRL", .addr =3D A_VERSAL2_I3C1_REF_CTRL, + .reset =3D 0x2000c00, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "I3C2_REF_CTRL", .addr =3D A_VERSAL2_I3C2_REF_CTRL, + .reset =3D 0x2000c00, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "I3C3_REF_CTRL", .addr =3D A_VERSAL2_I3C3_REF_CTRL, + .reset =3D 0x2000c00, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "I3C4_REF_CTRL", .addr =3D A_VERSAL2_I3C4_REF_CTRL, + .reset =3D 0x2000c00, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "I3C5_REF_CTRL", .addr =3D A_VERSAL2_I3C5_REF_CTRL, + .reset =3D 0x2000c00, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "I3C6_REF_CTRL", .addr =3D A_VERSAL2_I3C6_REF_CTRL, + .reset =3D 0x2000c00, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "I3C7_REF_CTRL", .addr =3D A_VERSAL2_I3C7_REF_CTRL, + .reset =3D 0x2000c00, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "DBG_LPX_CTRL", .addr =3D A_VERSAL2_DBG_LPX_CTRL, + .reset =3D 0x300, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "TIMESTAMP_REF_CTRL", .addr =3D A_VERSAL2_TIMESTAMP_REF= _CTRL, + .reset =3D 0x2000c00, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "SAFETY_CHK", .addr =3D A_VERSAL2_SAFETY_CHK, + },{ .name =3D "ASU_CLK_CTRL", .addr =3D A_VERSAL2_ASU_CLK_CTRL, + .reset =3D 0x2000f04, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "DBG_TSTMP_CLK_CTRL", .addr =3D A_VERSAL2_DBG_TSTMP_CLK= _CTRL, + .reset =3D 0x300, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "MMI_TOPSW_CLK_CTRL", .addr =3D A_VERSAL2_MMI_TOPSW_CLK= _CTRL, + .reset =3D 0x2000300, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "WWDT_PLL_CLK_CTRL", .addr =3D A_VERSAL2_WWDT_PLL_CLK_C= TRL, + .reset =3D 0xc00, + .rsvd =3D 0xfffc00f8, + },{ .name =3D "RCLK_CTRL", .addr =3D A_VERSAL2_RCLK_CTRL, + .rsvd =3D 0xc040, + },{ .name =3D "RST_RPU_A", .addr =3D A_VERSAL2_RST_RPU_A, + .reset =3D 0x10303, + .rsvd =3D 0xfffefcfc, + .pre_write =3D crl_rst_cpu_prew, + },{ .name =3D "RST_RPU_B", .addr =3D A_VERSAL2_RST_RPU_B, + .reset =3D 0x10303, + .rsvd =3D 0xfffefcfc, + .pre_write =3D crl_rst_cpu_prew, + },{ .name =3D "RST_RPU_C", .addr =3D A_VERSAL2_RST_RPU_C, + .reset =3D 0x10303, + .rsvd =3D 0xfffefcfc, + .pre_write =3D crl_rst_cpu_prew, + },{ .name =3D "RST_RPU_D", .addr =3D A_VERSAL2_RST_RPU_D, + .reset =3D 0x10303, + .rsvd =3D 0xfffefcfc, + .pre_write =3D crl_rst_cpu_prew, + },{ .name =3D "RST_RPU_E", .addr =3D A_VERSAL2_RST_RPU_E, + .reset =3D 0x10303, + .rsvd =3D 0xfffefcfc, + .pre_write =3D crl_rst_cpu_prew, + },{ .name =3D "RST_RPU_GD_0", .addr =3D A_VERSAL2_RST_RPU_GD_0, + .reset =3D 0x3, + },{ .name =3D "RST_RPU_GD_1", .addr =3D A_VERSAL2_RST_RPU_GD_1, + .reset =3D 0x3, + },{ .name =3D "RST_ASU_GD", .addr =3D A_VERSAL2_RST_ASU_GD, + .reset =3D 0x3, + },{ .name =3D "RST_ADMA", .addr =3D A_VERSAL2_RST_ADMA, + .reset =3D 0x1, + .pre_write =3D crl_rst_dev_prew, + },{ .name =3D "RST_SDMA", .addr =3D A_VERSAL2_RST_SDMA, + .pre_write =3D crl_rst_dev_prew, + .reset =3D 0x1, + },{ .name =3D "RST_GEM0", .addr =3D A_VERSAL2_RST_GEM0, + .reset =3D 0x1, + .pre_write =3D crl_rst_dev_prew, + },{ .name =3D "RST_GEM1", .addr =3D A_VERSAL2_RST_GEM1, + .reset =3D 0x1, + .pre_write =3D crl_rst_dev_prew, + },{ .name =3D "RST_USB0", .addr =3D A_VERSAL2_RST_USB0, + .reset =3D 0x1, + .pre_write =3D crl_rst_dev_prew, + },{ .name =3D "RST_USB1", .addr =3D A_VERSAL2_RST_USB1, + .reset =3D 0x1, + .pre_write =3D crl_rst_dev_prew, + },{ .name =3D "RST_UART0", .addr =3D A_VERSAL2_RST_UART0, + .reset =3D 0x1, + .pre_write =3D crl_rst_dev_prew, + },{ .name =3D "RST_UART1", .addr =3D A_VERSAL2_RST_UART1, + .reset =3D 0x1, + .pre_write =3D crl_rst_dev_prew, + },{ .name =3D "RST_SPI0", .addr =3D A_VERSAL2_RST_SPI0, + .reset =3D 0x1, + },{ .name =3D "RST_SPI1", .addr =3D A_VERSAL2_RST_SPI1, + .reset =3D 0x1, + },{ .name =3D "RST_CAN0", .addr =3D A_VERSAL2_RST_CAN0, + .reset =3D 0x1, + .pre_write =3D crl_rst_dev_prew, + },{ .name =3D "RST_CAN1", .addr =3D A_VERSAL2_RST_CAN1, + .reset =3D 0x1, + .pre_write =3D crl_rst_dev_prew, + },{ .name =3D "RST_CAN2", .addr =3D A_VERSAL2_RST_CAN2, + .reset =3D 0x1, + .pre_write =3D crl_rst_dev_prew, + },{ .name =3D "RST_CAN3", .addr =3D A_VERSAL2_RST_CAN3, + .reset =3D 0x1, + .pre_write =3D crl_rst_dev_prew, + },{ .name =3D "RST_I3C0", .addr =3D A_VERSAL2_RST_I3C0, + .reset =3D 0x1, + },{ .name =3D "RST_I3C1", .addr =3D A_VERSAL2_RST_I3C1, + .reset =3D 0x1, + },{ .name =3D "RST_I3C2", .addr =3D A_VERSAL2_RST_I3C2, + .reset =3D 0x1, + },{ .name =3D "RST_I3C3", .addr =3D A_VERSAL2_RST_I3C3, + .reset =3D 0x1, + },{ .name =3D "RST_I3C4", .addr =3D A_VERSAL2_RST_I3C4, + .reset =3D 0x1, + },{ .name =3D "RST_I3C5", .addr =3D A_VERSAL2_RST_I3C5, + .reset =3D 0x1, + },{ .name =3D "RST_I3C6", .addr =3D A_VERSAL2_RST_I3C6, + .reset =3D 0x1, + },{ .name =3D "RST_I3C7", .addr =3D A_VERSAL2_RST_I3C7, + .reset =3D 0x1, + },{ .name =3D "RST_DBG_LPX", .addr =3D A_VERSAL2_RST_DBG_LPX, + .reset =3D 0x3, + .rsvd =3D 0xfc, + },{ .name =3D "RST_GPIO", .addr =3D A_VERSAL2_RST_GPIO, + .reset =3D 0x1, + },{ .name =3D "RST_TTC", .addr =3D A_VERSAL2_RST_TTC, + .reset =3D 0xff, + },{ .name =3D "RST_TIMESTAMP", .addr =3D A_VERSAL2_RST_TIMESTAMP, + .reset =3D 0x1, + },{ .name =3D "RST_SWDT0", .addr =3D A_VERSAL2_RST_SWDT0, + .reset =3D 0x1, + },{ .name =3D "RST_SWDT1", .addr =3D A_VERSAL2_RST_SWDT1, + .reset =3D 0x1, + },{ .name =3D "RST_SWDT2", .addr =3D A_VERSAL2_RST_SWDT2, + .reset =3D 0x1, + },{ .name =3D "RST_SWDT3", .addr =3D A_VERSAL2_RST_SWDT3, + .reset =3D 0x1, + },{ .name =3D "RST_SWDT4", .addr =3D A_VERSAL2_RST_SWDT4, + .reset =3D 0x1, + },{ .name =3D "RST_IPI", .addr =3D A_VERSAL2_RST_IPI, + },{ .name =3D "RST_SYSMON", .addr =3D A_VERSAL2_RST_SYSMON, + },{ .name =3D "ASU_MB_RST_MODE", .addr =3D A_VERSAL2_ASU_MB_RST_MODE, + .reset =3D 0x1, + .rsvd =3D 0xf8, + },{ .name =3D "FPX_TOPSW_MUX_CTRL", .addr =3D A_VERSAL2_FPX_TOPSW_MUX= _CTRL, + .reset =3D 0x1, + },{ .name =3D "RST_FPX", .addr =3D A_VERSAL2_RST_FPX, + .reset =3D 0x3, + },{ .name =3D "RST_MMI", .addr =3D A_VERSAL2_RST_MMI, + .reset =3D 0x1, + },{ .name =3D "RST_OCM", .addr =3D A_VERSAL2_RST_OCM, + } +}; + static void versal_crl_reset_enter(Object *obj, ResetType type) { XlnxVersalCRL *s =3D XLNX_VERSAL_CRL(obj); unsigned int i; =20 for (i =3D 0; i < ARRAY_SIZE(s->regs_info); ++i) { register_reset(&s->regs_info[i]); } } =20 +static void versal2_crl_reset_enter(Object *obj, ResetType type) +{ + XlnxVersal2CRL *s =3D XLNX_VERSAL2_CRL(obj); + size_t i; + + for (i =3D 0; i < VERSAL2_CRL_R_MAX; ++i) { + register_reset(&s->regs_info[i]); + } +} + static void versal_crl_reset_hold(Object *obj, ResetType type) { XlnxVersalCRL *s =3D XLNX_VERSAL_CRL(obj); =20 crl_update_irq(s); @@ -386,10 +681,77 @@ static void versal_crl_init(Object *obj) qdev_prop_allow_set_link_before_realize, OBJ_PROP_LINK_STRONG); } } =20 +static void versal2_crl_init(Object *obj) +{ + XlnxVersal2CRL *s =3D XLNX_VERSAL2_CRL(obj); + XlnxVersalCRLBase *xvcb =3D XLNX_VERSAL_CRL_BASE(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + size_t i; + + xvcb->reg_array =3D register_init_block32(DEVICE(obj), versal2_crl_reg= s_info, + ARRAY_SIZE(versal2_crl_regs_in= fo), + s->regs_info, s->regs, + &crl_ops, + XLNX_VERSAL_CRL_ERR_DEBUG, + VERSAL2_CRL_R_MAX * 4); + xvcb->regs =3D s->regs; + + sysbus_init_mmio(sbd, &xvcb->reg_array->mem); + + for (i =3D 0; i < ARRAY_SIZE(s->cfg.rpu); ++i) { + object_property_add_link(obj, "rpu[*]", TYPE_ARM_CPU, + (Object **)&s->cfg.rpu[i], + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_STRONG); + } + + for (i =3D 0; i < ARRAY_SIZE(s->cfg.adma); ++i) { + object_property_add_link(obj, "adma[*]", TYPE_DEVICE, + (Object **)&s->cfg.adma[i], + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_STRONG); + } + + for (i =3D 0; i < ARRAY_SIZE(s->cfg.sdma); ++i) { + object_property_add_link(obj, "sdma[*]", TYPE_DEVICE, + (Object **)&s->cfg.sdma[i], + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_STRONG); + } + + for (i =3D 0; i < ARRAY_SIZE(s->cfg.uart); ++i) { + object_property_add_link(obj, "uart[*]", TYPE_DEVICE, + (Object **)&s->cfg.uart[i], + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_STRONG); + } + + for (i =3D 0; i < ARRAY_SIZE(s->cfg.gem); ++i) { + object_property_add_link(obj, "gem[*]", TYPE_DEVICE, + (Object **)&s->cfg.gem[i], + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_STRONG); + } + + for (i =3D 0; i < ARRAY_SIZE(s->cfg.usb); ++i) { + object_property_add_link(obj, "usb[*]", TYPE_DEVICE, + (Object **)&s->cfg.usb[i], + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_STRONG); + } + + for (i =3D 0; i < ARRAY_SIZE(s->cfg.can); ++i) { + object_property_add_link(obj, "can[*]", TYPE_DEVICE, + (Object **)&s->cfg.can[i], + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_STRONG); + } +} + static void crl_finalize(Object *obj) { XlnxVersalCRLBase *s =3D XLNX_VERSAL_CRL_BASE(obj); register_finalize_block(s->reg_array); } @@ -402,10 +764,20 @@ static const VMStateDescription vmstate_versal_crl = =3D { VMSTATE_UINT32_ARRAY(regs, XlnxVersalCRL, CRL_R_MAX), VMSTATE_END_OF_LIST(), } }; =20 +static const VMStateDescription vmstate_versal2_crl =3D { + .name =3D TYPE_XLNX_VERSAL2_CRL, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, XlnxVersal2CRL, VERSAL2_CRL_R_MAX), + VMSTATE_END_OF_LIST(), + } +}; + static void versal_crl_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); XlnxVersalCRLBaseClass *xvcc =3D XLNX_VERSAL_CRL_BASE_CLASS(klass); ResettableClass *rc =3D RESETTABLE_CLASS(klass); @@ -414,10 +786,21 @@ static void versal_crl_class_init(ObjectClass *klass,= const void *data) rc->phases.enter =3D versal_crl_reset_enter; rc->phases.hold =3D versal_crl_reset_hold; xvcc->decode_periph_rst =3D versal_decode_periph_rst; } =20 +static void versal2_crl_class_init(ObjectClass *klass, const void *data) +{ + XlnxVersalCRLBaseClass *xvcc =3D XLNX_VERSAL_CRL_BASE_CLASS(klass); + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + dc->vmsd =3D &vmstate_versal2_crl; + rc->phases.enter =3D versal2_crl_reset_enter; + xvcc->decode_periph_rst =3D versal2_decode_periph_rst; +} + static const TypeInfo crl_base_info =3D { .name =3D TYPE_XLNX_VERSAL_CRL_BASE, .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(XlnxVersalCRLBase), .class_size =3D sizeof(XlnxVersalCRLBaseClass), @@ -431,12 +814,21 @@ static const TypeInfo versal_crl_info =3D { .instance_size =3D sizeof(XlnxVersalCRL), .instance_init =3D versal_crl_init, .class_init =3D versal_crl_class_init, }; =20 +static const TypeInfo versal2_crl_info =3D { + .name =3D TYPE_XLNX_VERSAL2_CRL, + .parent =3D TYPE_XLNX_VERSAL_CRL_BASE, + .instance_size =3D sizeof(XlnxVersal2CRL), + .instance_init =3D versal2_crl_init, + .class_init =3D versal2_crl_class_init, +}; + static void crl_register_types(void) { type_register_static(&crl_base_info); type_register_static(&versal_crl_info); + type_register_static(&versal2_crl_info); } =20 type_init(crl_register_types) --=20 2.50.1