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Iglesias" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , "Frederic Konrad" , Sai Pavan Boddu Subject: [PATCH v5 34/47] hw/arm/xlnx-versal: use hw/arm/bsa.h for timer IRQ indices Date: Fri, 12 Sep 2025 12:00:43 +0200 Message-ID: <20250912100059.103997-35-luc.michel@amd.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250912100059.103997-1-luc.michel@amd.com> References: <20250912100059.103997-1-luc.michel@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB05.amd.com: luc.michel@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0001709B:EE_|CH3PR12MB8727:EE_ X-MS-Office365-Filtering-Correlation-Id: d0e670b5-01bb-4cbd-9226-08ddf1e39481 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|82310400026|376014|36860700013; X-Microsoft-Antispam-Message-Info: =?utf-8?B?eWQ1LzFIRG11RXFUdkgvN0JvdGhBbTBsVVMySWxHRmpMSHdmTVpMVTJxdVJF?= =?utf-8?B?Z090YUczbmUwOVRQOXU0Mm5NVkRwTmw0WGxweWFxclFqbm5MK2w5K2JIRXhl?= =?utf-8?B?aWt5ZzVPVXNnN2F5S2pkTHZ1ZjhaUWFkMUI0YjJNdXFXb2NVSTFsT1c3T3NM?= =?utf-8?B?SmJNOW5mZGV2RlNUTVZJdG1DNlFXMTZ5UHRwTEZqQjdvUFRVSUFjaHZ6Tk9E?= =?utf-8?B?YkltWUp0N0owV1ZqaFA2cUlMSCtUbzZSelh2Z0VXVVg1dWZxUEwrSEJibjQy?= =?utf-8?B?RlZWMkprYTk1dHBPS0VqbGVBMGhUMkk3cDlDQnFaTTRBd0xUNjVRTk9QUmE5?= =?utf-8?B?V0orREt0Y3pNR2VDaHFNaHZuN3NUMmU0c0xxd1pxYVF3NEhPVS9XMXZ6Nkc5?= =?utf-8?B?aUpNZ3hjeDFDWldXcEN0RDdkMlFiSlk2djhqZms5K1UvaTNUM2hlajYwY3Zy?= =?utf-8?B?OG4vZVdkclByVkhnUzNadW5UckdHSU9lZVpnakwwWHRTdlArdHRDK0tuK1h2?= =?utf-8?B?cFpQMXBkM2dZeWs4M25ISk5PVVFMYXVEb201aElNNmgzTHp4a2hMUXA4YUtC?= =?utf-8?B?V3AwME0vbDlTd2xiVStPYXloSmovUUZiYkxEaTJDekZVMHc1WEQ5LzY2UTJH?= =?utf-8?B?eHRlMXIxL2hlUWY5NitBWm1xMncvUzV5M2lMVklLNEppZkNiNmRRdGFrSi9J?= =?utf-8?B?N09YdmlReDQzb1kzdDNEYWZJb2JCVXAvNUVld00wK0VQM29FSnZiMWwwd3Jm?= =?utf-8?B?VmZBUlhQK0pWb0c0VUVsZHh4T2JtV1MwWWRGWnVrL0NDNkV2UUhJWUlWeFhn?= =?utf-8?B?WGxLdVoyZkhqSC9QaFNrQTI3NEFxeGRROHBqS0ZDZFFkN3NFYXlOaE1JOTFv?= =?utf-8?B?ZHlCblhKNHZLMlJqWHlRbUdmRUplYW5ORzl4T0NnTklnOTlBVlF4NlZnQTJs?= =?utf-8?B?Q2FPeFhNcllURnhaeDNCaE5oR1pEYjRocWxpU3ZJWFc3bFZHY0YyYUcxRHNF?= =?utf-8?B?disyUlVOMEdsRWY3VzZVdHdvU2Z1dVZja3QrQ1pGOG14L0dnMUtTVGE2NExj?= =?utf-8?B?U2xQb1QyaytFdGlrNlYrc21jbDYrdnlwdHlGQklNeVRqbEExN2hPdFMySStz?= =?utf-8?B?UVFYMmhCejlwUGFyY3JpZ2pCeFBkTERGeTN5c1A3RmsrQXBYZlFtbmZMYk1J?= =?utf-8?B?RGZBZ3d2MDh1TDBFeStPT0F6czRDdHBTc29XKzFadWtPNllFaW54ZlFuc2oz?= =?utf-8?B?LzR2c3EzTTkrT3dNSGQ3U0RkdTY4RmUzYWtDSkx5T2lsc0lwdEVxMFJDQUMx?= =?utf-8?B?YmF0dFB1UllwWlQ4NGtnOS92NGs3b0E5UlN1eVpleXVneXRzcFNuYWFqeFVu?= =?utf-8?B?ZkNQbFlRRXlWNFg3K0g0ZGZqdjk2eUJrT3U2djhNYXhQYjFuNnN0M2YycTQr?= =?utf-8?B?T2huWk1MdVVianNHd2N6MWFZZTQ5UHVQa1E2M2pZdGZRUWNVRjRPTVh6d3lI?= =?utf-8?B?SUVGdzVYek0rM2NWd08wNXJPeDl5L3dMK0Z0R0ZZK25mYVdGdG0xRnFzY2lW?= =?utf-8?B?VXczZ1YxMXQwQi9DbWI3Z2dZMStNbVRoT1pNbUhzemtaVjYzdDlnSU93YnRj?= =?utf-8?B?NHBJa0Z5TTJxbG1FOUI0MFFnR0hNazB3SWFZdGprRWNlcVZQMjV6Y3dtNTho?= =?utf-8?B?YThkbjd6c0QwdmhJcitrWEZZU3cwckpWUndMWGVMTkhuZzVhRE9kT2lGbGdJ?= =?utf-8?B?aGRHMDJJTXdkMFFXMWljaW04K1JKU2V2N21kZytBWlZ0U3NGeUM1N1N6RnRV?= =?utf-8?B?ODhYM2xJWkFIYldHZGpJdm9JWURyMzR3NVVGMUNWWDh1d2orNkJIbnZMOVli?= =?utf-8?B?OThFaTZEOWx6bGptTUJvQmRSaVZJeG1uSE5yVXd1dE1pUUtpcXBEcnFkMU1p?= =?utf-8?B?dVR4d2xpa2N4dm8ySEI2RmhQZlY3eFhNS24veklRMW85UmpuS0ZpcXk1U3FY?= =?utf-8?B?am9nbld3TC8wRFhmcmRqTEtKUVVJT2FxU2gveWVwSDhQaTUrZ0xjeW5POXJH?= =?utf-8?Q?c8aKXJ?= X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Signed-off-by: Luc Michel Reviewed-by: Francisco Iglesias Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/arm/xlnx-versal.h | 6 ------ hw/arm/xlnx-versal.c | 28 +++++++++++++++++----------- 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index 7bdf6dab629..da0260b83de 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -85,16 +85,10 @@ int versal_get_num_can(VersalVersion version); int versal_get_num_sdhci(VersalVersion version); =20 /* Memory-map and IRQ definitions. Copied a subset from * auto-generated files. */ =20 -#define VERSAL_GIC_MAINT_IRQ 9 -#define VERSAL_TIMER_VIRT_IRQ 11 -#define VERSAL_TIMER_S_EL1_IRQ 13 -#define VERSAL_TIMER_NS_EL1_IRQ 14 -#define VERSAL_TIMER_NS_EL2_IRQ 10 - #define VERSAL_CRL_IRQ 10 #define VERSAL_UART0_IRQ_0 18 #define VERSAL_UART1_IRQ_0 19 #define VERSAL_CANFD0_IRQ_0 20 #define VERSAL_CANFD1_IRQ_0 21 diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 02119d13533..3ccd8a88205 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -47,10 +47,11 @@ #include "hw/intc/arm_gicv3_its_common.h" #include "hw/intc/arm_gic.h" #include "hw/core/split-irq.h" #include "target/arm/cpu.h" #include "hw/cpu/cluster.h" +#include "hw/arm/bsa.h" =20 #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") #define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f") #define GEM_REVISION 0x40070106 =20 @@ -671,11 +672,12 @@ static DeviceState *versal_create_gic(Versal *s, } =20 qemu_fdt_setprop_cell(s->cfg.fdt, node, "phandle", s->phandle.gic); qemu_fdt_setprop_cell(s->cfg.fdt, node, "#interrupt-cells", 3); qemu_fdt_setprop_cells(s->cfg.fdt, node, "interrupts", - GIC_FDT_IRQ_TYPE_PPI, VERSAL_GIC_MAINT_IRQ, + GIC_FDT_IRQ_TYPE_PPI, + INTID_TO_PPI(ARCH_GIC_MAINT_IRQ), GIC_FDT_IRQ_FLAGS_LEVEL_HI); qemu_fdt_setprop(s->cfg.fdt, node, "interrupt-controller", NULL, 0= ); } =20 versal_create_gic_its(s, map, dev, mr, node); @@ -696,14 +698,14 @@ static void connect_gic_to_cpu(const VersalCpuCluster= Map *map, /* * Mapping from the output timer irq lines from the CPU to the * GIC PPI inputs. */ const int timer_irq[] =3D { - [GTIMER_PHYS] =3D VERSAL_TIMER_NS_EL1_IRQ, - [GTIMER_VIRT] =3D VERSAL_TIMER_VIRT_IRQ, - [GTIMER_HYP] =3D VERSAL_TIMER_NS_EL2_IRQ, - [GTIMER_SEC] =3D VERSAL_TIMER_S_EL1_IRQ, + [GTIMER_PHYS] =3D INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), + [GTIMER_VIRT] =3D INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), + [GTIMER_HYP] =3D INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), + [GTIMER_SEC] =3D INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), }; =20 has_gtimer =3D arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_GENERIC_TIM= ER); =20 if (has_gtimer) { @@ -714,13 +716,13 @@ static void connect_gic_to_cpu(const VersalCpuCluster= Map *map, } } =20 if (map->gic.version =3D=3D 3) { qemu_irq maint_irq; + int maint_idx =3D ppibase + INTID_TO_PPI(ARCH_GIC_MAINT_IRQ); =20 - maint_irq =3D qdev_get_gpio_in(gic, - ppibase + VERSAL_GIC_MAINT_IRQ); + maint_irq =3D qdev_get_gpio_in(gic, maint_idx); qdev_connect_gpio_out_named(cpu, "gicv3-maintenance-interrupt", 0, maint_irq); } =20 sysbus_connect_irq(sbd, idx, qdev_get_gpio_in(cpu, ARM_CPU_IRQ)); @@ -840,17 +842,21 @@ static void versal_create_cpu_cluster(Versal *s, cons= t VersalCpuClusterMap *map) =20 has_gtimer =3D arm_feature(&ARM_CPU(cpus[0])->env, ARM_FEATURE_GENERIC= _TIMER); if (map->dtb_expose && has_gtimer) { qemu_fdt_add_subnode(s->cfg.fdt, "/timer"); qemu_fdt_setprop_cells(s->cfg.fdt, "/timer", "interrupts", - GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_S_EL1_IR= Q, + GIC_FDT_IRQ_TYPE_PPI, + INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), GIC_FDT_IRQ_FLAGS_LEVEL_HI, - GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_NS_EL1_I= RQ, + GIC_FDT_IRQ_TYPE_PPI, + INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), GIC_FDT_IRQ_FLAGS_LEVEL_HI, - GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_VIRT_IRQ, + GIC_FDT_IRQ_TYPE_PPI, + INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), GIC_FDT_IRQ_FLAGS_LEVEL_HI, - GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_NS_EL2_I= RQ, + GIC_FDT_IRQ_TYPE_PPI, + INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), GIC_FDT_IRQ_FLAGS_LEVEL_HI); qemu_fdt_setprop(s->cfg.fdt, "/timer", "compatible", compatible, sizeof(compatible)); } } --=20 2.50.1