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Iglesias" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , "Frederic Konrad" , Sai Pavan Boddu Subject: [PATCH v5 31/47] hw/misc/xlnx-versal-crl: split into base/concrete classes Date: Fri, 12 Sep 2025 12:00:40 +0200 Message-ID: <20250912100059.103997-32-luc.michel@amd.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250912100059.103997-1-luc.michel@amd.com> References: <20250912100059.103997-1-luc.michel@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB04.amd.com: luc.michel@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099DB:EE_|MN2PR12MB4336:EE_ X-MS-Office365-Filtering-Correlation-Id: be39645f-f5fc-4e39-8185-08ddf1e394bf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|376014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?p8kgX9ql/8a7XzBJSgA+AX0pN0bdujUmwSVp4vrbDGkHXaRD2DqQbZosRMSS?= =?us-ascii?Q?SMRU6Z+ZV5m1OxfxSAtEo6IpJ8iSMpEKcysLnHmsOZ7J6TpCdSzcM1nioLxF?= =?us-ascii?Q?UQGTzeZKmQDw6F0DsLY/jPSlkwGvO0WnPyfi9uAXI7OsrSCui7geBpwGvIwP?= =?us-ascii?Q?S/b1AsfcvTt6w9yqmY1RKky98SFhfpdKRi8vjOBLkg9zf9nh4fFT64RtOFot?= =?us-ascii?Q?rgwV+bHEhwcU79u+nXMZyZwXrO7/iDRuU+0rTxqpAd/U7zd10MvY5DC95IwE?= =?us-ascii?Q?iOjWEI92ReHcSdUNSDr9KpODe9ZiYu3OpS7pgKxzsdTP4IaDhkTkT1O9RI7U?= =?us-ascii?Q?LqJzNPa+IctHRhxONMxL9d73olP5xFM3QjPJ97U2ls6wsWAfdlFuN1dR/u2d?= =?us-ascii?Q?2vw6dNdTQ51k+t3KLjI8GZ/N6o0WN21qLMYzleoO79z2N4gkVyX6fEMlpvjX?= =?us-ascii?Q?GgfPTolYQG7bd62HsRyrybGmaj+TUXEkZdF6TxLE33Ygvpaj/I5AsCfaGMmq?= =?us-ascii?Q?blMjz7Toh/6XXHSoNbiISrW/RJsmKsWkRtXw5oIr3alNYP4A1CLzZ++35/0v?= =?us-ascii?Q?/P8uXez9AVVBvWByJ/72fKCbpwfbCmuctCiAqxTyAKk37QzYsxI7WuIjClu8?= =?us-ascii?Q?vx1hp1EyFz1IxX56QoTZfKmk4WSOuyB3OWFkZv+sFWyw6WsUQE2MZ5LjUQ72?= =?us-ascii?Q?fIbC0e0X0x+GVciIHAEmwhbT2DXZao04LffNvVlUZhtsuPy1dPfN11CHjbs6?= =?us-ascii?Q?jZqzjl7MK4xaBOoIuxyt1ZXIvDxcA3JbGTO44q1fpQtVaIz07RCSCgVE+xlX?= =?us-ascii?Q?yLx/zRth6eDmkLb2XG2z6ZHdtGGfhTjLl5PoNisXoJWCnLATX61pa7X8kNwu?= =?us-ascii?Q?raM9S1UDnFxJ4DZlQRsZPy35ebCZFPMmsahS286JEzvr4j/GYzLV8mNSlWBY?= =?us-ascii?Q?yPMRsUepcg3AnJUSHurFOR1yZ3YhQ4ephP9598VJ2/HCYnD/a73mskHyqlb7?= =?us-ascii?Q?WO2jePtyPdMW1UANXiEZEMiL57YwMDUKdLRt0Et17QSo3em6bXKAH/+/Qs3y?= =?us-ascii?Q?YWIwD3fEGWoDZf8cSORWHn9tUFNtPUt/sdkMD4A42kLV9oFjSyKet1AmhQXt?= =?us-ascii?Q?W7pBE15o6wKKJrF5C7/p6l1jdGcD4SL7M4SboqUgyu8fEjtn8Mwy2ggsd2TW?= =?us-ascii?Q?M0OLpw16Fyr9tZThzWRh/jRPCTuAFSDnzxVHR9RsaNkyNWNIqpzJGvEV6Eum?= =?us-ascii?Q?ZhAG5NukdFKuEyrwW5f1wCoXtq7vexB92/935fYiB8cbDsXOAxsB+feASZ7p?= =?us-ascii?Q?Px+P2nelnEgPzlZN3ZqnvcI7F8SwSCCFDCkNDbYNGx/AC67YYAD/qlGez1A7?= =?us-ascii?Q?doTogbPZf5WKaovqxXFA3Jxvtx3M8nAJyavIoJvlusa9t3Dxmc9+jbZjv6c6?= =?us-ascii?Q?Om8SaGVp25EIZXpBxsnD0RzfseLp8Gj35oSMk9kHEn90/YeZya3rbV1h2J4c?= =?us-ascii?Q?d9aj22bNQFR4v/PTEfAcAuXXHfoOUHgJP7oH?= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:satlexmb07.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(82310400026)(376014)(36860700013)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Sep 2025 10:03:11.1123 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: be39645f-f5fc-4e39-8185-08ddf1e394bf X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DB.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4336 Received-SPF: permerror client-ip=2a01:111:f403:2415::613; envelope-from=Luc.Michel@amd.com; helo=NAM11-DM6-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1757672262331116600 Content-Type: text/plain; charset="utf-8" Split the TYPE_XLNX_VERSAL_CRL type into base and concrete classes. This is in preparation for the versal2 version of the CRL. Signed-off-by: Luc Michel Reviewed-by: Francisco Iglesias --- include/hw/misc/xlnx-versal-crl.h | 31 ++++++++++++++++++-- hw/misc/xlnx-versal-crl.c | 48 +++++++++++++++++++------------ 2 files changed, 58 insertions(+), 21 deletions(-) diff --git a/include/hw/misc/xlnx-versal-crl.h b/include/hw/misc/xlnx-versa= l-crl.h index dba6d3585d1..2b39d203a67 100644 --- a/include/hw/misc/xlnx-versal-crl.h +++ b/include/hw/misc/xlnx-versal-crl.h @@ -1,21 +1,27 @@ /* * QEMU model of the Clock-Reset-LPD (CRL). * * Copyright (c) 2022 Xilinx Inc. + * Copyright (c) 2025 Advanced Micro Devices, Inc. * SPDX-License-Identifier: GPL-2.0-or-later * * Written by Edgar E. Iglesias */ #ifndef HW_MISC_XLNX_VERSAL_CRL_H #define HW_MISC_XLNX_VERSAL_CRL_H =20 #include "hw/sysbus.h" #include "hw/register.h" #include "target/arm/cpu-qom.h" +#include "hw/arm/xlnx-versal-version.h" =20 +#define TYPE_XLNX_VERSAL_CRL_BASE "xlnx-versal-crl-base" #define TYPE_XLNX_VERSAL_CRL "xlnx-versal-crl" + +OBJECT_DECLARE_TYPE(XlnxVersalCRLBase, XlnxVersalCRLBaseClass, + XLNX_VERSAL_CRL_BASE) OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCRL, XLNX_VERSAL_CRL) =20 REG32(ERR_CTRL, 0x0) FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1) REG32(IR_STATUS, 0x4) @@ -214,22 +220,43 @@ REG32(PSM_RST_MODE, 0x370) =20 #define CRL_R_MAX (R_PSM_RST_MODE + 1) =20 #define RPU_MAX_CPU 2 =20 -struct XlnxVersalCRL { +struct XlnxVersalCRLBase { SysBusDevice parent_obj; + + RegisterInfoArray *reg_array; + uint32_t *regs; +}; + +struct XlnxVersalCRLBaseClass { + SysBusDeviceClass parent_class; +}; + +struct XlnxVersalCRL { + XlnxVersalCRLBase parent_obj; qemu_irq irq; =20 struct { ARMCPU *cpu_r5[RPU_MAX_CPU]; DeviceState *adma[8]; DeviceState *uart[2]; DeviceState *gem[2]; DeviceState *usb; } cfg; =20 - RegisterInfoArray *reg_array; uint32_t regs[CRL_R_MAX]; RegisterInfo regs_info[CRL_R_MAX]; }; + +static inline const char *xlnx_versal_crl_class_name(VersalVersion ver) +{ + switch (ver) { + case VERSAL_VER_VERSAL: + return TYPE_XLNX_VERSAL_CRL; + default: + g_assert_not_reached(); + } +} + #endif diff --git a/hw/misc/xlnx-versal-crl.c b/hw/misc/xlnx-versal-crl.c index f288545967a..be89e0da40d 100644 --- a/hw/misc/xlnx-versal-crl.c +++ b/hw/misc/xlnx-versal-crl.c @@ -296,21 +296,21 @@ static const RegisterAccessInfo crl_regs_info[] =3D { .reset =3D 0x1, .rsvd =3D 0xf8, } }; =20 -static void crl_reset_enter(Object *obj, ResetType type) +static void versal_crl_reset_enter(Object *obj, ResetType type) { XlnxVersalCRL *s =3D XLNX_VERSAL_CRL(obj); unsigned int i; =20 for (i =3D 0; i < ARRAY_SIZE(s->regs_info); ++i) { register_reset(&s->regs_info[i]); } } =20 -static void crl_reset_hold(Object *obj, ResetType type) +static void versal_crl_reset_hold(Object *obj, ResetType type) { XlnxVersalCRL *s =3D XLNX_VERSAL_CRL(obj); =20 crl_update_irq(s); } @@ -323,24 +323,26 @@ static const MemoryRegionOps crl_ops =3D { .min_access_size =3D 4, .max_access_size =3D 4, }, }; =20 -static void crl_init(Object *obj) +static void versal_crl_init(Object *obj) { XlnxVersalCRL *s =3D XLNX_VERSAL_CRL(obj); + XlnxVersalCRLBase *xvcb =3D XLNX_VERSAL_CRL_BASE(obj); SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); int i; =20 - s->reg_array =3D + xvcb->reg_array =3D register_init_block32(DEVICE(obj), crl_regs_info, ARRAY_SIZE(crl_regs_info), s->regs_info, s->regs, &crl_ops, XLNX_VERSAL_CRL_ERR_DEBUG, CRL_R_MAX * 4); - sysbus_init_mmio(sbd, &s->reg_array->mem); + xvcb->regs =3D s->regs; + sysbus_init_mmio(sbd, &xvcb->reg_array->mem); sysbus_init_irq(sbd, &s->irq); =20 for (i =3D 0; i < ARRAY_SIZE(s->cfg.cpu_r5); ++i) { object_property_add_link(obj, "cpu_r5[*]", TYPE_ARM_CPU, (Object **)&s->cfg.cpu_r5[i], @@ -375,45 +377,53 @@ static void crl_init(Object *obj) OBJ_PROP_LINK_STRONG); } =20 static void crl_finalize(Object *obj) { - XlnxVersalCRL *s =3D XLNX_VERSAL_CRL(obj); + XlnxVersalCRLBase *s =3D XLNX_VERSAL_CRL_BASE(obj); register_finalize_block(s->reg_array); } =20 -static const VMStateDescription vmstate_crl =3D { +static const VMStateDescription vmstate_versal_crl =3D { .name =3D TYPE_XLNX_VERSAL_CRL, .version_id =3D 1, .minimum_version_id =3D 1, .fields =3D (const VMStateField[]) { VMSTATE_UINT32_ARRAY(regs, XlnxVersalCRL, CRL_R_MAX), VMSTATE_END_OF_LIST(), } }; =20 -static void crl_class_init(ObjectClass *klass, const void *data) +static void versal_crl_class_init(ObjectClass *klass, const void *data) { - ResettableClass *rc =3D RESETTABLE_CLASS(klass); DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); =20 - dc->vmsd =3D &vmstate_crl; - - rc->phases.enter =3D crl_reset_enter; - rc->phases.hold =3D crl_reset_hold; + dc->vmsd =3D &vmstate_versal_crl; + rc->phases.enter =3D versal_crl_reset_enter; + rc->phases.hold =3D versal_crl_reset_hold; } =20 -static const TypeInfo crl_info =3D { - .name =3D TYPE_XLNX_VERSAL_CRL, +static const TypeInfo crl_base_info =3D { + .name =3D TYPE_XLNX_VERSAL_CRL_BASE, .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(XlnxVersalCRL), - .class_init =3D crl_class_init, - .instance_init =3D crl_init, + .instance_size =3D sizeof(XlnxVersalCRLBase), + .class_size =3D sizeof(XlnxVersalCRLBaseClass), .instance_finalize =3D crl_finalize, + .abstract =3D true, +}; + +static const TypeInfo versal_crl_info =3D { + .name =3D TYPE_XLNX_VERSAL_CRL, + .parent =3D TYPE_XLNX_VERSAL_CRL_BASE, + .instance_size =3D sizeof(XlnxVersalCRL), + .instance_init =3D versal_crl_init, + .class_init =3D versal_crl_class_init, }; =20 static void crl_register_types(void) { - type_register_static(&crl_info); + type_register_static(&crl_base_info); + type_register_static(&versal_crl_info); } =20 type_init(crl_register_types) --=20 2.50.1