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Iglesias" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , "Frederic Konrad" , Sai Pavan Boddu Subject: [PATCH v5 25/47] hw/arm/xlnx-versal: add support for GICv2 Date: Fri, 12 Sep 2025 12:00:34 +0200 Message-ID: <20250912100059.103997-26-luc.michel@amd.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250912100059.103997-1-luc.michel@amd.com> References: <20250912100059.103997-1-luc.michel@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB05.amd.com: luc.michel@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0001709B:EE_|SJ0PR12MB6710:EE_ X-MS-Office365-Filtering-Correlation-Id: 6a4ef4d7-8573-48b9-efd2-08ddf1e39138 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|82310400026|376014|1800799024|30052699003; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Ail3KYb0hXsWWA4iTYuFVukAGlG+mzIwF7XLCO/mvy43sy60h9cAQKzBltMU?= =?us-ascii?Q?g7cT7EPZs7B4RIlerrFbC+bx+dHt+JUOqneykM+RxKLmdM9360yu491jfSRf?= =?us-ascii?Q?gcUEOQcN+X2tIP+46kBm/maKfK5HrXKTkJ8yqnQukwOb5p2dfhOJb1OPN0Wq?= =?us-ascii?Q?4wI14oIkJIl0tlEPF/1c5rS99xgHf3vDdUQ1QhBMYCsFoNkbLfekMTj51yUO?= =?us-ascii?Q?vQaOoXHA5bMmpazybwLwAL2kB925dVPHTr6qcCsGpPL25D1A/YcHabM/enpz?= =?us-ascii?Q?pqfutCa7/tM3b1t0hHDgn2eCVj6nH+eQF1ZBZh3UVg3G2Mn9CBYmUoGhbU6J?= =?us-ascii?Q?xywm3Q9FdonGkLp8w893lkz892AcrxLQyttipvZaA5LlbV+UOWcIO2ah0afL?= =?us-ascii?Q?PEh4SXeXQcFTiN5zOq8r5r8H7fuUcbryWUBfdrtMVv0TVuNclcAOkNAQARZz?= =?us-ascii?Q?ocM9Jk7H+ogjO7p4tH+5nggNqxsT2xDPw4HbsQsQwDZpsXT8/vYGv1p1tFUs?= =?us-ascii?Q?J+sjWAXKha4qSoD5BsM3vU1Dgfq9+qudf6sRxCXAKKnPpavwglgWP9WkiRuG?= =?us-ascii?Q?sxyuAOYOabG4RrouXopFzLfPWiK+t4YEcJHyx8QfwUZZ9sTG/rrcIkcPh5x9?= =?us-ascii?Q?P8KDaQlf/8f/5MUMx8CozX/B2NMulVp5HVoqDNKCsJUhcmuMRukJNoL9u3Wi?= =?us-ascii?Q?bMq4YqgEb3mv55k3NpGrrqBJE4pqB+anE5g8wriOqpyKQz7rdY1Yk5GR46wv?= =?us-ascii?Q?46h7htNgaWmPM54Rhr1V2PfghuBSUN8B5ARmOLEvrvleFvqz/YIy4ksHXStU?= =?us-ascii?Q?N+dnrZxoo42Mvk0RXzOvHWg5wYOj+/PdrEMNNlmtWNmE6CZA/xHvUNxJjSHz?= =?us-ascii?Q?4EuiqAW3m0Qm8QK68bcd6Hsz/9vac//yhmPELlWzLmahHlOCQi6MIUOr194a?= =?us-ascii?Q?KH8T287lMiNh6YUMmBcoEBxnOMMQ4qS0/7sobikKWfl27oHOP4WZ4g741SHv?= =?us-ascii?Q?SbJdjCAU+3vfYHB0BkL4jhut7GIdevANyfMAn1lN6BbvAmff9H6PduJgA65q?= =?us-ascii?Q?dch7S1znoO2KIccy8xX47PGiiesQmU/TvsEM45LlQANvlJxvRBjP9y2r4Zus?= =?us-ascii?Q?YAdBefU73apjQhOIAxaGPP4fC1H5lzdJAKmWERo/xpnS13tqDaJTIH765yfs?= =?us-ascii?Q?wV2gThbewhOZmn9VsUgWoQtb7Z9qqCpBh4qV8qyUVzTRDfHpPQiZHZFf7d1r?= =?us-ascii?Q?jG44k5ycKNLUW5xKYBNLnjFGW70jRIj2gzWwYthu+ldQfPPf5ipo2KvqEOW9?= =?us-ascii?Q?Xg1dsR2knU+CHhhN2J5ug/GK1Ibs+s0pomanD4A7jsvRh00VEBDvFIw7uOO3?= =?us-ascii?Q?dxJC8XecgsClTuk4+PqgwiKuigQrMO/uIerYjU3i6Q+srkwM3nJDnRBpEsoD?= =?us-ascii?Q?SQB62fGlA2Nr/T+IXne99UFXSPUByMpO7STzVMbzn6HvuTdl0kWjsP+fh/iT?= =?us-ascii?Q?YqM4puTA1nHVsm/api8iW88z8Jk7ft1oXmB4?= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:satlexmb08.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(36860700013)(82310400026)(376014)(1800799024)(30052699003); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Sep 2025 10:03:05.1974 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6a4ef4d7-8573-48b9-efd2-08ddf1e39138 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001709B.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6710 Received-SPF: permerror client-ip=2a01:111:f403:2416::628; envelope-from=Luc.Michel@amd.com; helo=NAM11-CO1-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1757672250193116600 Content-Type: text/plain; charset="utf-8" Add support for GICv2 instantiation in the Versal SoC. This is in preparation for the RPU refactoring. Signed-off-by: Luc Michel Reviewed-by: Francisco Iglesias --- hw/arm/xlnx-versal.c | 82 +++++++++++++++++++++++++++++++++----------- 1 file changed, 62 insertions(+), 20 deletions(-) diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 1c79a3aa047..d5dbbe10a6d 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -43,10 +43,11 @@ #include "hw/misc/xlnx-versal-cframe-reg.h" #include "hw/or-irq.h" #include "hw/misc/xlnx-versal-crl.h" #include "hw/intc/arm_gicv3_common.h" #include "hw/intc/arm_gicv3_its_common.h" +#include "hw/intc/arm_gic.h" #include "hw/core/split-irq.h" =20 #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") #define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f") #define GEM_REVISION 0x40070106 @@ -72,10 +73,11 @@ typedef struct VersalSimplePeriphMap { =20 typedef struct VersalGicMap { int version; uint64_t dist; uint64_t redist; + uint64_t cpu_iface; uint64_t its; size_t num_irq; bool has_its; } VersalGicMap; =20 @@ -501,10 +503,14 @@ static void versal_create_gic_its(Versal *s, DeviceState *dev; SysBusDevice *sbd; g_autofree char *node_pat =3D NULL, *node =3D NULL; const char compatible[] =3D "arm,gic-v3-its"; =20 + if (map->gic.version !=3D 3) { + return; + } + if (!map->gic.has_its) { return; } =20 dev =3D qdev_new(TYPE_ARM_GICV3_ITS); @@ -540,49 +546,85 @@ static DeviceState *versal_create_gic(Versal *s, int first_cpu_idx, size_t num_cpu) { DeviceState *dev; SysBusDevice *sbd; - QList *redist_region_count; g_autofree char *node =3D NULL; g_autofree char *name =3D NULL; - const char compatible[] =3D "arm,gic-v3"; + const char gicv3_compat[] =3D "arm,gic-v3"; + const char gicv2_compat[] =3D "arm,cortex-a15-gic"; + + switch (map->gic.version) { + case 2: + dev =3D qdev_new(gic_class_name()); + break; + + case 3: + dev =3D qdev_new(gicv3_class_name()); + break; + + default: + g_assert_not_reached(); + } =20 - dev =3D qdev_new(gicv3_class_name()); name =3D g_strdup_printf("%s-gic[*]", map->name); object_property_add_child(OBJECT(s), name, OBJECT(dev)); sbd =3D SYS_BUS_DEVICE(dev); - qdev_prop_set_uint32(dev, "revision", 3); + qdev_prop_set_uint32(dev, "revision", map->gic.version); qdev_prop_set_uint32(dev, "num-cpu", num_cpu); qdev_prop_set_uint32(dev, "num-irq", map->gic.num_irq + 32); - - redist_region_count =3D qlist_new(); - qlist_append_int(redist_region_count, num_cpu); - qdev_prop_set_array(dev, "redist-region-count", redist_region_count); - qdev_prop_set_bit(dev, "has-security-extensions", true); - qdev_prop_set_bit(dev, "has-lpi", map->gic.has_its); - object_property_set_link(OBJECT(dev), "sysmem", OBJECT(mr), &error_abo= rt); qdev_prop_set_uint32(dev, "first-cpu-index", first_cpu_idx); =20 + if (map->gic.version =3D=3D 3) { + QList *redist_region_count; + + redist_region_count =3D qlist_new(); + qlist_append_int(redist_region_count, num_cpu); + qdev_prop_set_array(dev, "redist-region-count", redist_region_coun= t); + qdev_prop_set_bit(dev, "has-lpi", map->gic.has_its); + object_property_set_link(OBJECT(dev), "sysmem", OBJECT(mr), + &error_abort); + + } + sysbus_realize_and_unref(sbd, &error_fatal); =20 memory_region_add_subregion(mr, map->gic.dist, sysbus_mmio_get_region(sbd, 0)); - memory_region_add_subregion(mr, map->gic.redist, - sysbus_mmio_get_region(sbd, 1)); + + if (map->gic.version =3D=3D 3) { + memory_region_add_subregion(mr, map->gic.redist, + sysbus_mmio_get_region(sbd, 1)); + } else { + memory_region_add_subregion(mr, map->gic.cpu_iface, + sysbus_mmio_get_region(sbd, 1)); + } =20 if (map->dtb_expose) { - node =3D versal_fdt_add_subnode(s, "/gic", map->gic.dist, compatib= le, - sizeof(compatible)); + if (map->gic.version =3D=3D 3) { + node =3D versal_fdt_add_subnode(s, "/gic", map->gic.dist, + gicv3_compat, + sizeof(gicv3_compat)); + qemu_fdt_setprop_sized_cells(s->cfg.fdt, node, "reg", + 2, map->gic.dist, + 2, 0x10000, + 2, map->gic.redist, + 2, GICV3_REDIST_SIZE * num_cpu); + } else { + node =3D versal_fdt_add_subnode(s, "/gic", map->gic.dist, + gicv2_compat, + sizeof(gicv2_compat)); + qemu_fdt_setprop_sized_cells(s->cfg.fdt, node, "reg", + 2, map->gic.dist, + 2, 0x1000, + 2, map->gic.cpu_iface, + 2, 0x1000); + } + qemu_fdt_setprop_cell(s->cfg.fdt, node, "phandle", s->phandle.gic); qemu_fdt_setprop_cell(s->cfg.fdt, node, "#interrupt-cells", 3); - qemu_fdt_setprop_sized_cells(s->cfg.fdt, node, "reg", - 2, map->gic.dist, - 2, 0x10000, - 2, map->gic.redist, - 2, GICV3_REDIST_SIZE * num_cpu); qemu_fdt_setprop_cells(s->cfg.fdt, node, "interrupts", GIC_FDT_IRQ_TYPE_PPI, VERSAL_GIC_MAINT_IRQ, GIC_FDT_IRQ_FLAGS_LEVEL_HI); qemu_fdt_setprop(s->cfg.fdt, node, "interrupt-controller", NULL, 0= ); } --=20 2.50.1