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Iglesias" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Alistair Francis" , Frederic Konrad , Sai Pavan Boddu , Luc Michel Subject: [PATCH v5 23/47] hw/intc/arm_gicv3: Introduce a 'first-cpu-index' property Date: Fri, 12 Sep 2025 12:00:32 +0200 Message-ID: <20250912100059.103997-24-luc.michel@amd.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250912100059.103997-1-luc.michel@amd.com> References: <20250912100059.103997-1-luc.michel@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB04.amd.com: luc.michel@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099DF:EE_|DM6PR12MB4482:EE_ X-MS-Office365-Filtering-Correlation-Id: af1fb954-faa6-4f10-63e7-08ddf1e38dbe X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|1800799024|376014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?X0VapExJY7u6wknGPEBeJhA4YhQt6ijxWeyGblHXs6s6ZQjTUnbkX2eD8BAy?= =?us-ascii?Q?UJPvbBEO9BL4st+S4QOR9SNDVewdN6f9PnOCR4E5vePl2TTTWM/Ddl3Hn43M?= =?us-ascii?Q?zMi/JgKr8Mr4T0a+2fK1esBNfRBwCXs++fodhYkCJd5xyis8Xx1WXYvC6hOZ?= =?us-ascii?Q?diYlsskUQz5vevC7t5Gl+JTgyTebqlTxGwNAujl26QQgPnXv5VwRpAykJ+im?= =?us-ascii?Q?bowB/tjHKh/goHSP0ToSeMmp1L/yP4MYCg4TNLDN4XiGiTsy2ap3GxggnCmG?= =?us-ascii?Q?/4xyi2/qEH1ltdpDM9EwVmg0XihXHVawu7Y2aiCyfsBpBjAoKsuDJlaNwisf?= =?us-ascii?Q?xSt6dDyH2PDA/q+k4+tckk9bKjCpu5Khwrq9t4nAg5pRXRItqTt5btL/lbN+?= =?us-ascii?Q?Wd0ENYAXJXJF92m2PAf43w0d664S99ZKOIIDT9GmRWkNRLz3+wQO3ok2I96O?= =?us-ascii?Q?86d6yY3z0+D8dFO1vt68mi3OL2TXPh3ZzjOkRjeu4VppHo2YHixPaWle8cRl?= =?us-ascii?Q?R8M54npKE0GOGh9R/NYfN+LzTEB3Yzuu/Ak5ti5xNfss6x2ZtYwPXIzAKG54?= =?us-ascii?Q?30TeEGJKVljec7xyfhcftcEcSW8Og4Mpp/vDO8wlrdlkBcV0VY5lmfdx/LUg?= =?us-ascii?Q?+yD+5cvebROg0H8aX2bdXuwePlau371dqRZkxAcTOF09nxf/ODYXg5pvIz5c?= =?us-ascii?Q?q3l14t7HDlsJ8vB370LNPicbH0Orw4LWHMLAdOdjqg4ZhP1mx6/1j5buhuPI?= =?us-ascii?Q?uDhvM+gQ9dJJyJiVLxHxJIQ+FOkUDnKo9r5ltfcnoJiru4LHk2hHnMfK6Nkm?= =?us-ascii?Q?c40EfRz9KJynudT1dYMindCWUEeC/PIxgmJQDjtqkQzQWb/QwwAvka0LuisF?= =?us-ascii?Q?o1BSeqqYr/uqlLMb2J8IMnc4mkRGwVIsiAcjROAXQcVhRe9MtKyDJrjc2J9i?= =?us-ascii?Q?a3SmD1MujC+2zg+HfwLTsgAHlLH/F+NZaMIHjVmQl4lRXj9JsonJey0HaT30?= =?us-ascii?Q?2CKoqJL4JoeMICox2u+Y7UBhTLyP9q+h2DLolh35S9WJMklOSsJDkaXnPIXC?= =?us-ascii?Q?MhCKvUJrzm7OsHjXQgRIlPdX2iuvC0jPD0HJZW84lOU9DfZYVOWPhp0YzSa9?= =?us-ascii?Q?ykNTqX8yFuZiAeBIGz8NjxuwgQXkRc3PGJ7ElKeInQmwpFDHxyKxkgnL216D?= =?us-ascii?Q?TjCR+XYakAAM5/aHlQZYbdHNOO4EVfdqWOVFE18snBE86cf5djKgN7dB+n5S?= =?us-ascii?Q?0PiW6Z+/BzFaoOiUhAdOiy7ciQVPbJehQ1pI9hp95cJBnr4YJfI2xJfDK/ts?= =?us-ascii?Q?jj0MZttdQ2Mutz3xuIh/9fkJ9TSX7IW/H4dqsss54QMG4no4au1ZTgTTdsB9?= =?us-ascii?Q?MnSB5pjh0/VahQ4ERIuce/knDyUqTw1vDBO/DDdjMCIitC+b8JK1wdXwpaQg?= =?us-ascii?Q?2DFFpC0bW4xn2h36a2koClkdsKk0y8tUQwF7YFhmIdyjroWbDe68SmMxpDR0?= =?us-ascii?Q?WJGnInYYdfT/69FsV3VQfrz4I70k9Wukwsse?= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:satlexmb07.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(82310400026)(1800799024)(376014)(36860700013); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Sep 2025 10:02:59.3621 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: af1fb954-faa6-4f10-63e7-08ddf1e38dbe X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DF.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4482 Received-SPF: permerror client-ip=2a01:111:f403:2406::604; envelope-from=Luc.Michel@amd.com; helo=NAM02-SN1-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1757672411246116600 Content-Type: text/plain; charset="utf-8" From: Francisco Iglesias Introduce a 'first-cpu-index' property for specifying the first QEMU CPU connected to the GICv3. This makes it possible to have multiple instances of the GICv3 connected to different CPU clusters. For KVM, mark this property has unsupported. It probably does not make much sense as it is intented to be used to model non-SMP systems. Signed-off-by: Luc Michel Signed-off-by: Francisco Iglesias Reviewed-by: Sai Pavan Boddu Reviewed-by: Peter Maydell --- include/hw/intc/arm_gicv3_common.h | 1 + hw/intc/arm_gicv3_common.c | 3 ++- hw/intc/arm_gicv3_cpuif.c | 2 +- hw/intc/arm_gicv3_kvm.c | 6 ++++++ 4 files changed, 10 insertions(+), 2 deletions(-) diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3= _common.h index 572d971d22c..38aa1961c50 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -227,10 +227,11 @@ struct GICv3State { MemoryRegion iomem_dist; /* Distributor */ GICv3RedistRegion *redist_regions; /* Redistributor Regions */ uint32_t *redist_region_count; /* redistributor count within each regi= on */ uint32_t nb_redist_regions; /* number of redist regions */ =20 + uint32_t first_cpu_idx; uint32_t num_cpu; uint32_t num_irq; uint32_t revision; uint32_t maint_irq; bool lpi_enable; diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index e438d8c042d..2d0df6da86c 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -434,11 +434,11 @@ static void arm_gicv3_common_realize(DeviceState *dev= , Error **errp) } =20 s->cpu =3D g_new0(GICv3CPUState, s->num_cpu); =20 for (i =3D 0; i < s->num_cpu; i++) { - CPUState *cpu =3D qemu_get_cpu(i); + CPUState *cpu =3D qemu_get_cpu(s->first_cpu_idx + i); uint64_t cpu_affid; =20 s->cpu[i].cpu =3D cpu; s->cpu[i].gic =3D s; /* Store GICv3CPUState in CPUARMState gicv3state pointer */ @@ -620,10 +620,11 @@ static const Property arm_gicv3_common_properties[] = =3D { DEFINE_PROP_BOOL("force-8-bit-prio", GICv3State, force_8bit_prio, 0), DEFINE_PROP_ARRAY("redist-region-count", GICv3State, nb_redist_regions, redist_region_count, qdev_prop_uint32, uint32_t), DEFINE_PROP_LINK("sysmem", GICv3State, dma, TYPE_MEMORY_REGION, MemoryRegion *), + DEFINE_PROP_UINT32("first-cpu-index", GICv3State, first_cpu_idx, 0), }; =20 static void arm_gicv3_common_class_init(ObjectClass *klass, const void *da= ta) { DeviceClass *dc =3D DEVICE_CLASS(klass); diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 4b4cf091570..1af7690b958 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -3022,11 +3022,11 @@ void gicv3_init_cpuif(GICv3State *s) * registers with the CPU */ int i; =20 for (i =3D 0; i < s->num_cpu; i++) { - ARMCPU *cpu =3D ARM_CPU(qemu_get_cpu(i)); + ARMCPU *cpu =3D ARM_CPU(qemu_get_cpu(s->first_cpu_idx + i)); GICv3CPUState *cs =3D &s->cpu[i]; =20 /* * If the CPU doesn't define a GICv3 configuration, probably becau= se * in real hardware it doesn't have one, then we use default values diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 0cd14d78a75..9829e2146da 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -819,10 +819,16 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, E= rror **errp) if (s->nmi_support) { error_setg(errp, "NMI is not supported with the in-kernel GIC"); return; } =20 + if (s->first_cpu_idx !=3D 0) { + error_setg(errp, "Non-zero first-cpu-idx is unsupported with the " + "in-kernel GIC"); + return; + } + gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL); =20 for (i =3D 0; i < s->num_cpu; i++) { ARMCPU *cpu =3D ARM_CPU(qemu_get_cpu(i)); =20 --=20 2.50.1