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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1757605329; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=r8h3MgtbMTqUsRt1flHwZEd6IggG3JyO4fSCSwJOw1M=; b=DiUNJQek45lhJKmwBFCg7IgR+5abLq+pUZSKxvlYjZBGzwfiKc61Jgwgh6HouM4tEEZNAi oHbuoJmDBElPngG1hw0SAVbWOK0EBjJXtNxfAf4mQE+I9CqMEbHWqxXuLqEIuxGOuV+RSw 4K2pJQFP5C1ojSR3ZroH2oH9OTAKSSQ= X-MC-Unique: LEFm89AXMzWvS3H15V4sKA-1 X-Mimecast-MFC-AGG-ID: LEFm89AXMzWvS3H15V4sKA_1757605326 From: Cornelia Huck To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Eric Auger , Sebastian Ott , Cornelia Huck Subject: [PATCH v3] arm/kvm: report registers we failed to set Date: Thu, 11 Sep 2025 17:41:59 +0200 Message-ID: <20250911154159.158046-1-cohuck@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" If we fail migration because of a mismatch of some registers between source and destination, the error message is not very informative: qemu-system-aarch64: error while loading state for instance 0x0 ofdevice 'c= pu' qemu-system-aarch64: Failed to put registers after init: Invalid argument At least try to give the user a hint which registers had a problem, even if they cannot really do anything about it right now. Sample output: Could not set register op0:3 op1:0 crn:0 crm:0 op2:0 to c00fac31 (is 413fd0= c1) We could be even more helpful once we support writable ID registers, at which point the user might actually be able to configure something that is migratable. Suggested-by: Eric Auger Reviewed-by: Sebastian Ott Signed-off-by: Cornelia Huck --- Changes v2->v3: * added Sebastian's R-b (thanks!) * use PRIx64 -- this leads to some overlong lines, but I think breaking up would be worse Changes RFC->v2: * cover different register types * less macro magic * less memory leaks --- target/arm/kvm.c | 86 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 667234485547..c1ec6654ca67 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -900,6 +900,58 @@ bool write_kvmstate_to_list(ARMCPU *cpu) return ok; } =20 +/* pretty-print a KVM register */ +#define CP_REG_ARM64_SYSREG_OP(_reg, _op) \ + ((uint8_t)((_reg & CP_REG_ARM64_SYSREG_ ## _op ## _MASK) >> \ + CP_REG_ARM64_SYSREG_ ## _op ## _SHIFT)) + +static gchar *kvm_print_sve_register_name(uint64_t regidx) +{ + uint16_t sve_reg =3D regidx & 0x000000000000ffff; + + if (regidx =3D=3D KVM_REG_ARM64_SVE_VLS) { + return g_strdup_printf("SVE VLS"); + } + /* zreg, preg, ffr */ + switch (sve_reg & 0xfc00) { + case 0: + return g_strdup_printf("SVE zreg n:%d slice:%d", + (sve_reg & 0x03e0) >> 5, sve_reg & 0x001f); + case 0x04: + return g_strdup_printf("SVE preg n:%d slice:%d", + (sve_reg & 0x01e0) >> 5, sve_reg & 0x001f); + case 0x06: + return g_strdup_printf("SVE ffr slice:%d", sve_reg & 0x001f); + default: + return g_strdup_printf("SVE ???"); + } +} + +static gchar *kvm_print_register_name(uint64_t regidx) +{ + switch ((regidx & KVM_REG_ARM_COPROC_MASK)) { + case KVM_REG_ARM_CORE: + return g_strdup_printf("core reg %"PRIx64, regidx); + case KVM_REG_ARM_DEMUX: + return g_strdup_printf("demuxed reg %"PRIx64, regidx); + case KVM_REG_ARM64_SYSREG: + return g_strdup_printf("op0:%d op1:%d crn:%d crm:%d op2:%d", + CP_REG_ARM64_SYSREG_OP(regidx, OP0), + CP_REG_ARM64_SYSREG_OP(regidx, OP1), + CP_REG_ARM64_SYSREG_OP(regidx, CRN), + CP_REG_ARM64_SYSREG_OP(regidx, CRM), + CP_REG_ARM64_SYSREG_OP(regidx, OP2)); + case KVM_REG_ARM_FW: + return g_strdup_printf("fw reg %d", (int)(regidx & 0xffff)); + case KVM_REG_ARM64_SVE: + return kvm_print_sve_register_name(regidx); + case KVM_REG_ARM_FW_FEAT_BMAP: + return g_strdup_printf("fw feat reg %d", (int)(regidx & 0xffff= )); + default: + return g_strdup_printf("%"PRIx64, regidx); + } +} + bool write_list_to_kvmstate(ARMCPU *cpu, int level) { CPUState *cs =3D CPU(cpu); @@ -927,11 +979,45 @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level) g_assert_not_reached(); } if (ret) { + gchar *reg_str =3D kvm_print_register_name(regidx); + /* We might fail for "unknown register" and also for * "you tried to set a register which is constant with * a different value from what it actually contains". */ ok =3D false; + switch (ret) { + case -ENOENT: + error_report("Could not set register %s: unknown to KVM", + reg_str); + break; + case -EINVAL: + if ((regidx & KVM_REG_SIZE_MASK) =3D=3D KVM_REG_SIZE_U32) { + if (!kvm_get_one_reg(cs, regidx, &v32)) { + error_report("Could not set register %s to %x (is = %x)", + reg_str, (uint32_t)cpu->cpreg_values[= i], + v32); + } else { + error_report("Could not set register %s to %x", + reg_str, (uint32_t)cpu->cpreg_values[= i]); + } + } else /* U64 */ { + uint64_t v64; + + if (!kvm_get_one_reg(cs, regidx, &v64)) { + error_report("Could not set register %s to %"PRIx6= 4" (is %"PRIx64")", + reg_str, cpu->cpreg_values[i], v64); + } else { + error_report("Could not set register %s to %"PRIx6= 4, + reg_str, cpu->cpreg_values[i]); + } + } + break; + default: + error_report("Could not set register %s: %s", + reg_str, strerror(-ret)); + } + g_free(reg_str); } } return ok; --=20 2.50.1