From nobody Sun Sep 28 17:46:57 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1757575650; cv=none; d=zohomail.com; s=zohoarc; b=eVOtAuo3JM0JYsj/tLnaC8tHe47qWRm3vaUvOC785NfdvCeyqaxRSwQnHzm63VBUMLxB8mOF3li3bcsPmEG4X8SJskjFBdUmnb747M35pYrMvWKu+RISzy5GhOhNxtQJGGPop/LX1HxBnJiwGuij7CmpuJBCPlsEK7HsCBXUVfk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1757575650; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=l7fwbJlxWvEUMLS3eBzD9Lyz8E6SFJrLoRwVo6kPWKg=; b=dbQGp1PSPikrO7QdUcupsYoqPWmFM3BTS8Uck6FYQ3VsMoNQwmMVgp7MuFL0H5a+9AWRfbuLizqAWjcgZYi5hRcw5G1FXq36YeyPzxR///v3UZVlZkL7RuATxCRxnOLkWtHFJ8nY70oFCFyec3oLE4KAkWxLVLRW6Bg3Ec+Y3jU= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1757575650443279.16356558568907; Thu, 11 Sep 2025 00:27:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uwbhg-0000ep-L7; Thu, 11 Sep 2025 03:26:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uwbgh-0007nV-6R; Thu, 11 Sep 2025 03:25:47 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uwbgf-0000j4-4J; Thu, 11 Sep 2025 03:25:46 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 11 Sep 2025 15:24:55 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 11 Sep 2025 15:24:55 +0800 To: Paolo Bonzini , Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "Michael S. Tsirkin" , "Marcel Apfelbaum" , "open list:ARM TCG CPUs" , "open list:All patches CC here" CC: , , , , Subject: [PATCH v2 08/14] hw/arm/aspeed_ast2600: Add PCIe RC support (RC_H only) Date: Thu, 11 Sep 2025 15:24:32 +0800 Message-ID: <20250911072452.314553-9-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250911072452.314553-1-jamin_lin@aspeedtech.com> References: <20250911072452.314553-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1757575651382116600 Wire up the PCIe Root Complex in the AST2600 SoC model. According to the AST2600 firmware driver, only the RC_H controller is supported. RC_H uses PCIe PHY1 at 0x1e6ed200 and the PCIe config (H2X) register block at 0x1e770000. The RC_H MMIO window is mapped at 0x70000000=E2=80=930x80000000. RC_L is not modeled. The RC_H interrupt is wired to IRQ 168. Only RC_H is realized and connected to the SoC interrupt controller. The SoC integration initializes PCIe PHY1, instantiates a single RC instance, wires its MMIO regions, and connects its interrupt. An alias region is added to map the RC MMIO space into the guest physical address space. This provides enough functionality for firmware and guest drivers to discover and use the AST2600 RC_H Root Complex while leaving RC_L unimplemented. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast2600.c | 69 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 66 insertions(+), 3 deletions(-) diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index d12707f0ab..d521a1b4f0 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -48,11 +48,13 @@ static const hwaddr aspeed_soc_ast2600_memmap[] =3D { [ASPEED_DEV_XDMA] =3D 0x1E6E7000, [ASPEED_DEV_ADC] =3D 0x1E6E9000, [ASPEED_DEV_DP] =3D 0x1E6EB000, + [ASPEED_DEV_PCIE_PHY1] =3D 0x1E6ED200, [ASPEED_DEV_SBC] =3D 0x1E6F2000, [ASPEED_DEV_EMMC_BC] =3D 0x1E6f5000, [ASPEED_DEV_VIDEO] =3D 0x1E700000, [ASPEED_DEV_SDHCI] =3D 0x1E740000, [ASPEED_DEV_EMMC] =3D 0x1E750000, + [ASPEED_DEV_PCIE0] =3D 0x1E770000, [ASPEED_DEV_GPIO] =3D 0x1E780000, [ASPEED_DEV_GPIO_1_8V] =3D 0x1E780800, [ASPEED_DEV_RTC] =3D 0x1E781000, @@ -79,6 +81,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] =3D { [ASPEED_DEV_FSI1] =3D 0x1E79B000, [ASPEED_DEV_FSI2] =3D 0x1E79B100, [ASPEED_DEV_I3C] =3D 0x1E7A0000, + [ASPEED_DEV_PCIE_MMIO1] =3D 0x70000000, [ASPEED_DEV_SDRAM] =3D 0x80000000, }; =20 @@ -127,6 +130,7 @@ static const int aspeed_soc_ast2600_irqmap[] =3D { [ASPEED_DEV_LPC] =3D 35, [ASPEED_DEV_IBT] =3D 143, [ASPEED_DEV_I2C] =3D 110, /* 110 -> 125 */ + [ASPEED_DEV_PCIE0] =3D 168, [ASPEED_DEV_PECI] =3D 38, [ASPEED_DEV_ETH1] =3D 2, [ASPEED_DEV_ETH2] =3D 3, @@ -191,6 +195,10 @@ static void aspeed_soc_ast2600_init(Object *obj) snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); object_initialize_child(obj, "i2c", &s->i2c, typename); =20 + object_initialize_child(obj, "pcie-cfg", &s->pcie[0], TYPE_ASPEED_PCIE= _CFG); + object_initialize_child(obj, "pcie-phy[*]", &s->pcie_phy[0], + TYPE_ASPEED_PCIE_PHY); + object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); =20 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); @@ -292,7 +300,9 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) AspeedSoCState *s =3D ASPEED_SOC(dev); AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); qemu_irq irq; - g_autofree char *sram_name =3D NULL; + g_autofree char *name =3D NULL; + MemoryRegion *mmio_alias; + MemoryRegion *mmio_mr; =20 /* Default boot region (SPI memory or ROMs) */ memory_region_init(&s->spi_boot_container, OBJECT(s), @@ -362,8 +372,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) } =20 /* SRAM */ - sram_name =3D g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_i= ndex); - if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_s= ize, + name =3D g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); + if (!memory_region_init_ram(&s->sram, OBJECT(s), name, sc->sram_size, errp)) { return; } @@ -438,6 +448,59 @@ static void aspeed_soc_ast2600_realize(DeviceState *de= v, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, aspeed_soc_get_irq(s, ASPEED_DEV_PECI)); =20 + /* + * PCIe Root Complex (RC) + * + * H2X register space (single block 0x00-0xFF): + * 0x00-0x7F : shared by RC_L (PCIe0) and RC_H (PCIe1) + * 0x80-0xBF : RC_L only + * 0xC0-0xFF : RC_H only + * + * Model scope / limitations: + * - Firmware supports RC_H only; this QEMU model does not support R= C_L. + * - RC_H uses PHY1 and the MMIO window [0x70000000, 0x80000000] + * (aka MMIO1). + * + * Indexing convention (this model): + * - Expose a single logical instance at index 0. + * - pcie[0] -> hardware RC_H (PCIe1) + * - phy[0] -> hardware PHY1 + * - mmio.0 -> guest address range MMIO1: 0x70000000-0x80000000 + * - RC_L / PCIe0 is not created and mapped. + */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie_phy[0]), errp)) { + return; + } + aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->pcie_phy[0]), 0, + sc->memmap[ASPEED_DEV_PCIE_PHY1]); + + object_property_set_int(OBJECT(&s->pcie[0]), "dram-base", + sc->memmap[ASPEED_DEV_SDRAM], + &error_abort); + object_property_set_link(OBJECT(&s->pcie[0]), "dram", OBJECT(s->dram_m= r), + &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie[0]), errp)) { + return; + } + aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->pcie[0]), 0, + sc->memmap[ASPEED_DEV_PCIE0]); + + irq =3D qdev_get_gpio_in(DEVICE(&a->a7mpcore), + sc->irqmap[ASPEED_DEV_PCIE0]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie[0].rc), 0, irq); + + name =3D g_strdup_printf("aspeed.pcie-mmio.0"); + + mmio_alias =3D g_new0(MemoryRegion, 1); + mmio_mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->pcie[0].rc), 1); + + memory_region_init_alias(mmio_alias, OBJECT(&s->pcie[0].rc), name, + mmio_mr, sc->memmap[ASPEED_DEV_PCIE_MMIO1], + 0x10000000); + memory_region_add_subregion(s->memory, + sc->memmap[ASPEED_DEV_PCIE_MMIO1], + mmio_alias); + /* FMC, The number of CS is set at the board level */ object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), &error_abort); --=20 2.43.0