From nobody Sun Sep 28 17:46:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1757575675; cv=none; d=zohomail.com; s=zohoarc; b=cit63YMuMJZPtOAjMaYAiymdoiAszWwkpEpk/pQOnwSP5u+4XIzvwudBohAsJN21odUgnXklF/Z0HtgLgSKM1ql2iYeZDuyNKrvx+6EjbVzGjrkMu7S0T7h2F1rEaf7Ro+5xkR+MWs9pbX1I6c3eOAp0wsOUFjwzo9MZKMz17EM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1757575675; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=b4RopfQRVZ7Hji/h/D102txxy+1egNC7pjnf5qkrZO8=; b=HCaij6fHPtehB1HFOIFu1AT8gEUqXwVFNRdR92TQPEHKyveGHMAE12tWLUTqnZBFstJsM3DnkMU4F345sKTDY0YMvewEGv02pGCKA/biBJBF6YrJC2Zh50VC0ORCxiPlL6Bl7aBc33Cm44YhGYXsAEFR6WVyAZ35YWL3hBRms2c= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1757575675007226.22646651445064; Thu, 11 Sep 2025 00:27:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uwbgo-0007pE-MW; Thu, 11 Sep 2025 03:26:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uwbgT-0007gW-Dz; Thu, 11 Sep 2025 03:25:35 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uwbgQ-0000j4-Qh; Thu, 11 Sep 2025 03:25:33 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 11 Sep 2025 15:24:54 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 11 Sep 2025 15:24:54 +0800 To: Paolo Bonzini , Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "Michael S. Tsirkin" , "Marcel Apfelbaum" , "open list:ARM TCG CPUs" , "open list:All patches CC here" CC: , , , , Subject: [PATCH v2 05/14] hw/pci-host/aspeed: Add AST2600 PCIe Root Port and make address configurable Date: Thu, 11 Sep 2025 15:24:29 +0800 Message-ID: <20250911072452.314553-6-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250911072452.314553-1-jamin_lin@aspeedtech.com> References: <20250911072452.314553-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1757575675488116600 Content-Type: text/plain; charset="utf-8" Introduce an ASPEED PCIe Root Port and wire it under the RC. The root port is modeled as TYPE_ASPEED_PCIE_ROOT_PORT (subclass of TYPE_PCIE_ROOT_PORT). Key changes: - Add TYPE_ASPEED_PCIE_ROOT_PORT (PCIESlot-based) with vendor/device IDs and AER capability offset. - Extend AspeedPCIERcState to embed a root_port instance and a configurable rp_addr. - Add "rp-addr" property to the RC to place the root port at a specific devfn on the root bus. - Set the root port's "chassis" property to ensure a unique chassis per RC. - Extend AspeedPCIECfgClass with rc_rp_addr defaulting to PCI_DEVFN(8,0). Rationale: - AST2600 places the root port at 80:08.0 (bus 0x80, dev 8, fn 0). - AST2700 must place the root port at 00:00.0, and it supports three RCs. Each root port must therefore be uniquely identifiable; uses the PCIe "chassis" ID for that. - Providing a configurable "rp-addr" lets platforms select the correct devfn per SoC family, while the "chassis" property ensures uniqueness across multiple RC instances on AST2700. Signed-off-by: Jamin Lin --- include/hw/pci-host/aspeed_pcie.h | 11 +++++++ hw/pci-host/aspeed_pcie.c | 48 +++++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+) diff --git a/include/hw/pci-host/aspeed_pcie.h b/include/hw/pci-host/aspeed= _pcie.h index e7c231e847..4026d5b4c5 100644 --- a/include/hw/pci-host/aspeed_pcie.h +++ b/include/hw/pci-host/aspeed_pcie.h @@ -22,6 +22,7 @@ #include "hw/sysbus.h" #include "hw/pci/pci_bridge.h" #include "hw/pci/pcie_host.h" +#include "hw/pci/pcie_port.h" #include "qom/object.h" =20 typedef struct AspeedPCIECfgTxDesc { @@ -42,6 +43,13 @@ typedef struct AspeedPCIERegMap { AspeedPCIERcRegs rc; } AspeedPCIERegMap; =20 +#define TYPE_ASPEED_PCIE_ROOT_PORT "aspeed.pcie-root-port" +OBJECT_DECLARE_SIMPLE_TYPE(AspeedPCIERootPortState, ASPEED_PCIE_ROOT_PORT) + +typedef struct AspeedPCIERootPortState { + PCIESlot parent_obj; +} AspeedPCIERootPortState; + #define TYPE_ASPEED_PCIE_ROOT_DEVICE "aspeed.pcie-root-device" OBJECT_DECLARE_SIMPLE_TYPE(AspeedPCIERootDeviceState, ASPEED_PCIE_ROOT_DEV= ICE); =20 @@ -60,12 +68,14 @@ struct AspeedPCIERcState { MemoryRegion mmio; MemoryRegion io; =20 + uint32_t rp_addr; uint32_t bus_nr; char name[16]; bool has_rd; qemu_irq irq; =20 AspeedPCIERootDeviceState root_device; + AspeedPCIERootPortState root_port; }; =20 /* Bridge between AHB bus and PCIe RC. */ @@ -88,6 +98,7 @@ struct AspeedPCIECfgClass { const AspeedPCIERegMap *reg_map; const MemoryRegionOps *reg_ops; =20 + uint32_t rc_rp_addr; uint64_t rc_bus_nr; uint64_t nr_regs; bool rc_has_rd; diff --git a/hw/pci-host/aspeed_pcie.c b/hw/pci-host/aspeed_pcie.c index fa8854fe7a..3f04f0d379 100644 --- a/hw/pci-host/aspeed_pcie.c +++ b/hw/pci-host/aspeed_pcie.c @@ -23,6 +23,7 @@ #include "hw/registerfields.h" #include "hw/irq.h" #include "hw/pci/pci_host.h" +#include "hw/pci/pcie_port.h" #include "hw/pci-host/aspeed_pcie.h" #include "hw/pci/msi.h" #include "trace.h" @@ -65,6 +66,32 @@ static const TypeInfo aspeed_pcie_root_device_info =3D { }, }; =20 +/* + * PCIe Root Port + */ + +static void aspeed_pcie_root_port_class_init(ObjectClass *klass, + const void *data) +{ + PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); + DeviceClass *dc =3D DEVICE_CLASS(klass); + PCIERootPortClass *rpc =3D PCIE_ROOT_PORT_CLASS(klass); + + dc->desc =3D "ASPEED PCIe Root Port"; + k->vendor_id =3D PCI_VENDOR_ID_ASPEED; + k->device_id =3D 0x1150; + dc->user_creatable =3D true; + + rpc->aer_offset =3D 0x100; +} + +static const TypeInfo aspeed_pcie_root_port_info =3D { + .name =3D TYPE_ASPEED_PCIE_ROOT_PORT, + .parent =3D TYPE_PCIE_ROOT_PORT, + .instance_size =3D sizeof(AspeedPCIERootPortState), + .class_init =3D aspeed_pcie_root_port_class_init, +}; + /* * PCIe Root Complex (RC) */ @@ -144,6 +171,11 @@ static void aspeed_pcie_rc_realize(DeviceState *dev, E= rror **errp) qdev_prop_set_bit(DEVICE(&rc->root_device), "multifunction", false= ); qdev_realize(DEVICE(&rc->root_device), BUS(pci->bus), &error_fatal= ); } + + /* setup root port */ + qdev_prop_set_int32(DEVICE(&rc->root_port), "addr", rc->rp_addr); + qdev_prop_set_uint16(DEVICE(&rc->root_port), "chassis", cfg->id); + qdev_realize(DEVICE(&rc->root_port), BUS(pci->bus), &error_fatal); } =20 static const char *aspeed_pcie_rc_root_bus_path(PCIHostState *host_bridge, @@ -158,9 +190,19 @@ static const char *aspeed_pcie_rc_root_bus_path(PCIHos= tState *host_bridge, return rc->name; } =20 +static void aspeed_pcie_rc_instance_init(Object *obj) +{ + AspeedPCIERcState *rc =3D ASPEED_PCIE_RC(obj); + AspeedPCIERootPortState *root_port =3D &rc->root_port; + + object_initialize_child(obj, "root_port", root_port, + TYPE_ASPEED_PCIE_ROOT_PORT); +} + static const Property aspeed_pcie_rc_props[] =3D { DEFINE_PROP_UINT32("bus-nr", AspeedPCIERcState, bus_nr, 0), DEFINE_PROP_BOOL("has-rd", AspeedPCIERcState, has_rd, 0), + DEFINE_PROP_UINT32("rp-addr", AspeedPCIERcState, rp_addr, 0), }; =20 static void aspeed_pcie_rc_class_init(ObjectClass *klass, const void *data) @@ -183,6 +225,7 @@ static const TypeInfo aspeed_pcie_rc_info =3D { .name =3D TYPE_ASPEED_PCIE_RC, .parent =3D TYPE_PCIE_HOST_BRIDGE, .instance_size =3D sizeof(AspeedPCIERcState), + .instance_init =3D aspeed_pcie_rc_instance_init, .class_init =3D aspeed_pcie_rc_class_init, }; =20 @@ -456,6 +499,9 @@ static void aspeed_pcie_cfg_realize(DeviceState *dev, E= rror **errp) object_property_set_bool(OBJECT(&s->rc), "has-rd", apc->rc_has_rd, &error_abort); + object_property_set_int(OBJECT(&s->rc), "rp-addr", + apc->rc_rp_addr, + &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->rc), errp)) { return; } @@ -489,6 +535,7 @@ static void aspeed_pcie_cfg_class_init(ObjectClass *kla= ss, const void *data) apc->nr_regs =3D 0x100 >> 2; apc->rc_bus_nr =3D 0x80; apc->rc_has_rd =3D true; + apc->rc_rp_addr =3D PCI_DEVFN(8, 0); } =20 static const TypeInfo aspeed_pcie_cfg_info =3D { @@ -627,6 +674,7 @@ static void aspeed_pcie_register_types(void) { type_register_static(&aspeed_pcie_rc_info); type_register_static(&aspeed_pcie_root_device_info); + type_register_static(&aspeed_pcie_root_port_info); type_register_static(&aspeed_pcie_cfg_info); type_register_static(&aspeed_pcie_phy_info); } --=20 2.43.0