From nobody Sun Sep 28 17:46:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1757575592; cv=none; d=zohomail.com; s=zohoarc; b=VNEzvYIUDYy+qQ+Rrxeu32Glv37D8ZI9891BI+2drjc9PQPI5BU/4JwKNcT2o7erpN5bMP9PzDLaoyi3QhTZgtQrjeUSzLtaIAni01lbzeusH91QOqAaXQE15H5Zpe5TXCkdW7Q9+zyfg4QLHK04MDGARLFaGv5RJI/XVZNYSu8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1757575592; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=Gydm83kkVoMykC4bTNhsklD9u6RPYoNgLMRjkI1JVOs=; b=fI9Azy2oPbAP8Z+NhDXKPaHM26UdN3Ed+WOwwAqwuNpeeADTJPTGsiZNiitkRwZaiox1zzZK7B9KCnCVp7wKEp2Rav3cTmJiX6+QcsSglsYRk9pVajUJKb566UXFQnPaTy8b5gynEHusFw+8CenJ93mlhDTx1cKOOxwGRYWsngc= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1757575592441503.7152079692131; Thu, 11 Sep 2025 00:26:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uwbgC-0007e4-K0; Thu, 11 Sep 2025 03:25:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uwbgA-0007cf-0t; Thu, 11 Sep 2025 03:25:14 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uwbg7-0000j4-Ci; Thu, 11 Sep 2025 03:25:13 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 11 Sep 2025 15:24:53 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 11 Sep 2025 15:24:53 +0800 To: Paolo Bonzini , Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "Michael S. Tsirkin" , "Marcel Apfelbaum" , "open list:ARM TCG CPUs" , "open list:All patches CC here" CC: , , , , Subject: [PATCH v2 02/14] hw/pci-host/aspeed: Add AST2600 PCIe PHY model Date: Thu, 11 Sep 2025 15:24:26 +0800 Message-ID: <20250911072452.314553-3-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250911072452.314553-1-jamin_lin@aspeedtech.com> References: <20250911072452.314553-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1757575594833116600 This patch introduces an initial ASPEED PCIe PHY/host controller model to support the AST2600 SoC. It provides a simple register block with MMIO read/write callbacks, integration into the build system, and trace events for debugging. Key changes: 1. PCIe PHY MMIO read/write callbacks Implemented aspeed_pcie_phy_read() and aspeed_pcie_phy_write() to handle 32-bit register accesses. 2. Build system and Kconfig integration Added CONFIG_PCI_EXPRESS_ASPEED in hw/pci-host/Kconfig and meson rules. Updated ASPEED_SOC in hw/arm/Kconfig to imply PCI_DEVICES and select PCI_EXPRESS_ASPEED. 3. Trace events for debug New tracepoints aspeed_pcie_phy_read and aspeed_pcie_phy_write allow monitoring MMIO accesses. 4. Register space and defaults (AST2600 reference) Expose a 0x100 register space, as documented in the AST2600 datasheet. On reset, set default values: PEHR_ID: Vendor ID =3D ASPEED, Device ID =3D 0x1150 PEHR_CLASS_CODE =3D 0x06040006 PEHR_DATALINK =3D 0xD7040022 PEHR_LINK: bit[5] set to 1 to indicate link up. This provides a skeleton device for the AST2600 platform. It enables firmware to detect the PCIe link as up by default and allows future extension. Signed-off-by: Jamin Lin --- include/hw/pci-host/aspeed_pcie.h | 44 +++++++++ hw/pci-host/aspeed_pcie.c | 159 ++++++++++++++++++++++++++++++ hw/arm/Kconfig | 3 + hw/pci-host/Kconfig | 4 + hw/pci-host/meson.build | 1 + hw/pci-host/trace-events | 4 + 6 files changed, 215 insertions(+) create mode 100644 include/hw/pci-host/aspeed_pcie.h create mode 100644 hw/pci-host/aspeed_pcie.c diff --git a/include/hw/pci-host/aspeed_pcie.h b/include/hw/pci-host/aspeed= _pcie.h new file mode 100644 index 0000000000..faf87073ab --- /dev/null +++ b/include/hw/pci-host/aspeed_pcie.h @@ -0,0 +1,44 @@ +/* + * ASPEED PCIe Host Controller + * + * Copyright (C) 2025 ASPEED Technology Inc. + * Copyright (c) 2022 C=C3=A9dric Le Goater + * + * Jamin Lin + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This file is based on C=C3=A9dric Le Goater's patch: + * "pci: Add Aspeed host bridge (WIP)" + * https://github.com/legoater/qemu/commit/d1b97b0c7844219d847122410dc1898= 54f9d26df + * + * Modifications have been made to support the ASPEED AST2600 and AST2700 + * platforms. + */ + +#ifndef ASPEED_PCIE_H +#define ASPEED_PCIE_H + +#include "hw/sysbus.h" +#include "hw/pci/pci_bridge.h" +#include "hw/pci/pcie_host.h" +#include "qom/object.h" + +#define TYPE_ASPEED_PCIE_PHY "aspeed.pcie-phy" +OBJECT_DECLARE_TYPE(AspeedPCIEPhyState, AspeedPCIEPhyClass, ASPEED_PCIE_PH= Y); + +struct AspeedPCIEPhyState { + SysBusDevice parent_obj; + + MemoryRegion mmio; + uint32_t *regs; + uint32_t id; +}; + +struct AspeedPCIEPhyClass { + SysBusDeviceClass parent_class; + + uint64_t nr_regs; +}; + +#endif /* ASPEED_PCIE_H */ diff --git a/hw/pci-host/aspeed_pcie.c b/hw/pci-host/aspeed_pcie.c new file mode 100644 index 0000000000..5584449b17 --- /dev/null +++ b/hw/pci-host/aspeed_pcie.c @@ -0,0 +1,159 @@ +/* + * ASPEED PCIe Host Controller + * + * Copyright (C) 2025 ASPEED Technology Inc. + * Copyright (c) 2022 C=C3=A9dric Le Goater + * + * Jamin Lin + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This file is based on C=C3=A9dric Le Goater's patch: + * "pci: Add Aspeed host bridge (WIP)" + * https://github.com/legoater/qemu/commit/d1b97b0c7844219d847122410dc1898= 54f9d26df + * + * Modifications have been made to support the ASPEED AST2600 and AST2700 + * platforms. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "hw/qdev-properties.h" +#include "hw/registerfields.h" +#include "hw/irq.h" +#include "hw/pci/pci_host.h" +#include "hw/pci-host/aspeed_pcie.h" +#include "hw/pci/msi.h" +#include "trace.h" + +/* + * PCIe PHY + * + * PCIe Host Controller (PCIEH) + */ + +/* AST2600 */ +REG32(PEHR_ID, 0x00) + FIELD(PEHR_ID, DEV, 16, 16) +REG32(PEHR_CLASS_CODE, 0x04) +REG32(PEHR_DATALINK, 0x10) +REG32(PEHR_PROTECT, 0x7C) + FIELD(PEHR_PROTECT, LOCK, 0, 8) +REG32(PEHR_LINK, 0xC0) + FIELD(PEHR_LINK, STS, 5, 1) + +#define ASPEED_PCIE_PHY_UNLOCK 0xA8 + +static uint64_t aspeed_pcie_phy_read(void *opaque, hwaddr addr, + unsigned int size) +{ + AspeedPCIEPhyState *s =3D ASPEED_PCIE_PHY(opaque); + uint32_t reg =3D addr >> 2; + uint32_t value =3D 0; + + value =3D s->regs[reg]; + + trace_aspeed_pcie_phy_read(s->id, addr, value); + + return value; +} + +static void aspeed_pcie_phy_write(void *opaque, hwaddr addr, uint64_t data, + unsigned int size) +{ + AspeedPCIEPhyState *s =3D ASPEED_PCIE_PHY(opaque); + uint32_t reg =3D addr >> 2; + + trace_aspeed_pcie_phy_write(s->id, addr, data); + + switch (reg) { + case R_PEHR_PROTECT: + data &=3D R_PEHR_PROTECT_LOCK_MASK; + s->regs[reg] =3D !!(data =3D=3D ASPEED_PCIE_PHY_UNLOCK); + break; + default: + s->regs[reg] =3D data; + break; + } +} + +static const MemoryRegionOps aspeed_pcie_phy_ops =3D { + .read =3D aspeed_pcie_phy_read, + .write =3D aspeed_pcie_phy_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + }, +}; + +static void aspeed_pcie_phy_reset(DeviceState *dev) +{ + AspeedPCIEPhyState *s =3D ASPEED_PCIE_PHY(dev); + AspeedPCIEPhyClass *apc =3D ASPEED_PCIE_PHY_GET_CLASS(s); + + memset(s->regs, 0, apc->nr_regs << 2); + + s->regs[R_PEHR_ID] =3D + (0x1150 << R_PEHR_ID_DEV_SHIFT) | PCI_VENDOR_ID_ASPEED; + s->regs[R_PEHR_CLASS_CODE] =3D 0x06040006; + s->regs[R_PEHR_DATALINK] =3D 0xD7040022; + s->regs[R_PEHR_LINK] =3D R_PEHR_LINK_STS_MASK; +} + +static void aspeed_pcie_phy_realize(DeviceState *dev, Error **errp) +{ + AspeedPCIEPhyState *s =3D ASPEED_PCIE_PHY(dev); + AspeedPCIEPhyClass *apc =3D ASPEED_PCIE_PHY_GET_CLASS(s); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + g_autofree char *name; + + s->regs =3D g_new(uint32_t, apc->nr_regs); + name =3D g_strdup_printf(TYPE_ASPEED_PCIE_PHY ".regs.%d", s->id); + memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_pcie_phy_ops, s, na= me, + apc->nr_regs << 2); + sysbus_init_mmio(sbd, &s->mmio); +} + +static void aspeed_pcie_phy_unrealize(DeviceState *dev) +{ + AspeedPCIEPhyState *s =3D ASPEED_PCIE_PHY(dev); + + g_free(s->regs); + s->regs =3D NULL; +} + +static const Property aspeed_pcie_phy_props[] =3D { + DEFINE_PROP_UINT32("id", AspeedPCIEPhyState, id, 0), +}; + +static void aspeed_pcie_phy_class_init(ObjectClass *klass, const void *dat= a) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + AspeedPCIEPhyClass *apc =3D ASPEED_PCIE_PHY_CLASS(klass); + + dc->desc =3D "ASPEED PCIe Phy"; + dc->realize =3D aspeed_pcie_phy_realize; + dc->unrealize =3D aspeed_pcie_phy_unrealize; + device_class_set_legacy_reset(dc, aspeed_pcie_phy_reset); + device_class_set_props(dc, aspeed_pcie_phy_props); + + apc->nr_regs =3D 0x100 >> 2; +} + +static const TypeInfo aspeed_pcie_phy_info =3D { + .name =3D TYPE_ASPEED_PCIE_PHY, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(AspeedPCIEPhyState), + .class_init =3D aspeed_pcie_phy_class_init, + .class_size =3D sizeof(AspeedPCIEPhyClass), +}; + +static void aspeed_pcie_register_types(void) +{ + type_register_static(&aspeed_pcie_phy_info); +} + +type_init(aspeed_pcie_register_types); + diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 2aa4b5d778..83d2676f6c 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -544,6 +544,7 @@ config ASPEED_SOC bool default y depends on TCG && ARM + imply PCI_DEVICES select DS1338 select FTGMAC100 select I2C @@ -564,6 +565,8 @@ config ASPEED_SOC select MAX31785 select FSI_APB2OPB_ASPEED select AT24C + select PCI_EXPRESS + select PCI_EXPRESS_ASPEED =20 config MPS2 bool diff --git a/hw/pci-host/Kconfig b/hw/pci-host/Kconfig index 9824fa188d..8cbb8304a3 100644 --- a/hw/pci-host/Kconfig +++ b/hw/pci-host/Kconfig @@ -46,6 +46,10 @@ config PCI_I440FX select PCI select PAM =20 +config PCI_EXPRESS_ASPEED + bool + select PCI_EXPRESS + config PCI_EXPRESS_Q35 bool select PCI_EXPRESS diff --git a/hw/pci-host/meson.build b/hw/pci-host/meson.build index 937a0f72ac..86b754d0b0 100644 --- a/hw/pci-host/meson.build +++ b/hw/pci-host/meson.build @@ -2,6 +2,7 @@ pci_ss =3D ss.source_set() pci_ss.add(when: 'CONFIG_PAM', if_true: files('pam.c')) pci_ss.add(when: 'CONFIG_PCI_BONITO', if_true: files('bonito.c')) pci_ss.add(when: 'CONFIG_GT64120', if_true: files('gt64120.c')) +pci_ss.add(when: 'CONFIG_PCI_EXPRESS_ASPEED', if_true: files('aspeed_pcie.= c')) pci_ss.add(when: 'CONFIG_PCI_EXPRESS_DESIGNWARE', if_true: files('designwa= re.c')) pci_ss.add(when: 'CONFIG_PCI_EXPRESS_GENERIC_BRIDGE', if_true: files('gpex= .c')) pci_ss.add(when: ['CONFIG_PCI_EXPRESS_GENERIC_BRIDGE', 'CONFIG_ACPI'], if_= true: files('gpex-acpi.c')) diff --git a/hw/pci-host/trace-events b/hw/pci-host/trace-events index 0a816b9aa1..3438516756 100644 --- a/hw/pci-host/trace-events +++ b/hw/pci-host/trace-events @@ -1,5 +1,9 @@ # See docs/devel/tracing.rst for syntax documentation. =20 +# aspeed_pcie.c +aspeed_pcie_phy_read(uint32_t id, uint64_t addr, uint32_t value) "%d: addr= 0x%" PRIx64 " value 0x%" PRIx32 +aspeed_pcie_phy_write(uint32_t id, uint64_t addr, uint32_t value) "%d: add= r 0x%" PRIx64 " value 0x%" PRIx32 + # bonito.c bonito_spciconf_small_access(uint64_t addr, unsigned size) "PCI config add= ress is smaller then 32-bit, addr: 0x%"PRIx64", size: %u" =20 --=20 2.43.0