From nobody Sun Sep 28 17:46:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1757576004; cv=none; d=zohomail.com; s=zohoarc; b=BnPcAfjMv/EoIuaGMZKEz9FnK2sCRuJKfTZwTpUZCQS5GvHhd3xOYu6zsQDefAl3n6OsCA5hb7xhzxhXHqOHnCQr3Y+CHcRMQsRlUAtbvY3KS6Bg1Cqt7tdWlG3k2+nuokdSEWER4XxDl4MoL7EZgsaU8Fq9TADSnpxu+rnDXMs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1757576004; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=OK/B8kgl9BJZL9fN1mIioxBIa/IKU+FxqivhAn8C/y4=; b=G31Je33purJFm1PJ4EHaWNLR9GXqF/ALx+pOCCNACo/9DAFOTtMuM8Xmv0+x1MMIZ4eGXLyw1xHkScZ7L99apPGW0P38qStFf0mDV3Hs8nRgcBZfPkpvf9wVUyfsKMOdZ1ElYFCgIRAMj7hD9ZGXwxSu9Az8TSzrQJ/8RrcIv5o= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1757576004331238.87105256359757; Thu, 11 Sep 2025 00:33:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uwbhn-00013u-9v; Thu, 11 Sep 2025 03:26:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uwbhC-00083h-7a; Thu, 11 Sep 2025 03:26:19 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uwbhA-00015t-2j; Thu, 11 Sep 2025 03:26:17 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 11 Sep 2025 15:24:57 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 11 Sep 2025 15:24:57 +0800 To: Paolo Bonzini , Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "Michael S. Tsirkin" , "Marcel Apfelbaum" , "open list:ARM TCG CPUs" , "open list:All patches CC here" CC: , , , , Subject: [PATCH v2 12/14] hw/arm/aspeed_ast27x0: Introduce 3 PCIe RCs for AST2700 Date: Thu, 11 Sep 2025 15:24:36 +0800 Message-ID: <20250911072452.314553-13-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250911072452.314553-1-jamin_lin@aspeedtech.com> References: <20250911072452.314553-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1757576005333116600 Content-Type: text/plain; charset="utf-8" Add PCIe Root Complex support to the AST2700 SoC model. The AST2700 A1 silicon revision provides three PCIe Root Complexes: PCIe0 with its PHY at 0x12C15000, config (H2X) block at 0x120E0000, MMIO window at 0x60000000, and GIC IRQ 56. PCIe1 with its PHY at 0x12C15800, config (H2X) block at 0x120F0000, MMIO window at 0x80000000, and GIC IRQ 57. PCIe2 with its PHY at 0x14C1C000, config (H2X) block at 0x140D0000, MMIO window at 0xA0000000, and IRQ routed through INTC4 bit 31 mapped to GIC IRQ 196. Each RC instantiates a PHY device, a PCIe config (H2X) bridge, and an MMIO alias region. The per-RC MMIO alias size is 0x20000000. The AST2700 A0 silicon revision does not support PCIe Root Complexes, so pcie_num is set to 0 in that variant. Signed-off-by: Jamin Lin --- include/hw/arm/aspeed_soc.h | 1 + hw/arm/aspeed_ast27x0.c | 61 +++++++++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 79fe353f83..070e2b49c5 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -185,6 +185,7 @@ struct AspeedSoCClass { uint32_t silicon_rev; uint64_t sram_size; uint64_t secsram_size; + int pcie_num; int spis_num; int ehcis_num; int wdts_num; diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 6aa3841b69..48296397ae 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -38,6 +38,8 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D { [ASPEED_DEV_EHCI2] =3D 0x12063000, [ASPEED_DEV_HACE] =3D 0x12070000, [ASPEED_DEV_EMMC] =3D 0x12090000, + [ASPEED_DEV_PCIE0] =3D 0x120E0000, + [ASPEED_DEV_PCIE1] =3D 0x120F0000, [ASPEED_DEV_INTC] =3D 0x12100000, [ASPEED_GIC_DIST] =3D 0x12200000, [ASPEED_GIC_REDIST] =3D 0x12280000, @@ -45,6 +47,8 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D { [ASPEED_DEV_SCU] =3D 0x12C02000, [ASPEED_DEV_RTC] =3D 0x12C0F000, [ASPEED_DEV_TIMER1] =3D 0x12C10000, + [ASPEED_DEV_PCIE_PHY0] =3D 0x12C15000, + [ASPEED_DEV_PCIE_PHY1] =3D 0x12C15800, [ASPEED_DEV_SLI] =3D 0x12C17000, [ASPEED_DEV_UART4] =3D 0x12C1A000, [ASPEED_DEV_IOMEM1] =3D 0x14000000, @@ -59,6 +63,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D { [ASPEED_DEV_ETH2] =3D 0x14060000, [ASPEED_DEV_ETH3] =3D 0x14070000, [ASPEED_DEV_SDHCI] =3D 0x14080000, + [ASPEED_DEV_PCIE2] =3D 0x140D0000, [ASPEED_DEV_EHCI3] =3D 0x14121000, [ASPEED_DEV_EHCI4] =3D 0x14123000, [ASPEED_DEV_ADC] =3D 0x14C00000, @@ -66,6 +71,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D { [ASPEED_DEV_GPIO] =3D 0x14C0B000, [ASPEED_DEV_I2C] =3D 0x14C0F000, [ASPEED_DEV_INTCIO] =3D 0x14C18000, + [ASPEED_DEV_PCIE_PHY2] =3D 0x14C1C000, [ASPEED_DEV_SLIIO] =3D 0x14C1E000, [ASPEED_DEV_VUART] =3D 0x14C30000, [ASPEED_DEV_UART0] =3D 0x14C33000, @@ -81,6 +87,9 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D { [ASPEED_DEV_UART11] =3D 0x14C33A00, [ASPEED_DEV_UART12] =3D 0x14C33B00, [ASPEED_DEV_WDT] =3D 0x14C37000, + [ASPEED_DEV_PCIE_MMIO0] =3D 0x60000000, + [ASPEED_DEV_PCIE_MMIO1] =3D 0x80000000, + [ASPEED_DEV_PCIE_MMIO2] =3D 0xA0000000, [ASPEED_DEV_SPI_BOOT] =3D 0x100000000, [ASPEED_DEV_LTPI] =3D 0x300000000, [ASPEED_DEV_SDRAM] =3D 0x400000000, @@ -156,6 +165,8 @@ static const int aspeed_soc_ast2700a1_irqmap[] =3D { [ASPEED_DEV_DP] =3D 28, [ASPEED_DEV_EHCI1] =3D 33, [ASPEED_DEV_EHCI2] =3D 37, + [ASPEED_DEV_PCIE0] =3D 56, + [ASPEED_DEV_PCIE1] =3D 57, [ASPEED_DEV_LPC] =3D 192, [ASPEED_DEV_IBT] =3D 192, [ASPEED_DEV_KCS] =3D 192, @@ -166,6 +177,7 @@ static const int aspeed_soc_ast2700a1_irqmap[] =3D { [ASPEED_DEV_WDT] =3D 195, [ASPEED_DEV_PWM] =3D 195, [ASPEED_DEV_I3C] =3D 195, + [ASPEED_DEV_PCIE2] =3D 196, [ASPEED_DEV_UART0] =3D 196, [ASPEED_DEV_UART1] =3D 196, [ASPEED_DEV_UART2] =3D 196, @@ -233,6 +245,7 @@ static const int ast2700_gic132_gic196_intcmap[] =3D { [ASPEED_DEV_UART12] =3D 18, [ASPEED_DEV_EHCI3] =3D 28, [ASPEED_DEV_EHCI4] =3D 29, + [ASPEED_DEV_PCIE2] =3D 31, }; =20 /* GICINT 133 */ @@ -519,6 +532,17 @@ static void aspeed_soc_ast2700_init(Object *obj) =20 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); object_initialize_child(obj, "hace", &s->hace, typename); + + for (i =3D 0; i < sc->pcie_num; i++) { + snprintf(typename, sizeof(typename), "aspeed.pcie-phy-%s", socname= ); + object_initialize_child(obj, "pcie-phy[*]", &s->pcie_phy[i], typen= ame); + object_property_set_int(OBJECT(&s->pcie_phy[i]), "id", i, &error_a= bort); + + snprintf(typename, sizeof(typename), "aspeed.pcie-cfg-%s", socname= ); + object_initialize_child(obj, "pcie-cfg[*]", &s->pcie[i], typename); + object_property_set_int(OBJECT(&s->pcie[i]), "id", i, &error_abort= ); + } + object_initialize_child(obj, "dpmcu", &s->dpmcu, TYPE_UNIMPLEMENTED_DEVICE); object_initialize_child(obj, "ltpi", &s->ltpi, @@ -619,6 +643,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) AspeedINTCClass *ic =3D ASPEED_INTC_GET_CLASS(&a->intc[0]); AspeedINTCClass *icio =3D ASPEED_INTC_GET_CLASS(&a->intc[1]); g_autofree char *name =3D NULL; + MemoryRegion *mmio_alias; + MemoryRegion *mmio_mr; qemu_irq irq; =20 /* Default boot region (SPI memory or ROMs) */ @@ -936,6 +962,39 @@ static void aspeed_soc_ast2700_realize(DeviceState *de= v, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); =20 + /* PCIe */ + for (i =3D 0; i < sc->pcie_num; i++) { + if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie_phy[i]), errp)) { + return; + } + aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->pcie_phy[i]), 0, + sc->memmap[ASPEED_DEV_PCIE_PHY0 + i]); + + object_property_set_int(OBJECT(&s->pcie[i]), "dram-base", + sc->memmap[ASPEED_DEV_SDRAM], + &error_abort); + object_property_set_link(OBJECT(&s->pcie[i]), "dram", + OBJECT(s->dram_mr), &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie[i]), errp)) { + return; + } + aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->pcie[i]), 0, + sc->memmap[ASPEED_DEV_PCIE0 + i]); + irq =3D aspeed_soc_get_irq(s, ASPEED_DEV_PCIE0 + i); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie[i].rc), 0, irq); + + name =3D g_strdup_printf("aspeed.pcie-mmio.%d", i); + mmio_alias =3D g_new0(MemoryRegion, 1); + mmio_mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->pcie[i].rc),= 1); + + memory_region_init_alias(mmio_alias, OBJECT(&s->pcie[i].rc), name, + mmio_mr, sc->memmap[ASPEED_DEV_PCIE_MMIO0= + i], + 0x20000000); + memory_region_add_subregion(s->memory, + sc->memmap[ASPEED_DEV_PCIE_MMIO0 + i], + mmio_alias); + } + aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->dpmcu), "aspeed.dpmcu", sc->memmap[ASPEED_DEV_DPMCU], @@ -974,6 +1033,7 @@ static void aspeed_soc_ast2700a0_class_init(ObjectClas= s *oc, const void *data) sc->valid_cpu_types =3D valid_cpu_types; sc->silicon_rev =3D AST2700_A0_SILICON_REV; sc->sram_size =3D 0x20000; + sc->pcie_num =3D 0; sc->spis_num =3D 3; sc->ehcis_num =3D 2; sc->wdts_num =3D 8; @@ -1002,6 +1062,7 @@ static void aspeed_soc_ast2700a1_class_init(ObjectCla= ss *oc, const void *data) sc->valid_cpu_types =3D valid_cpu_types; sc->silicon_rev =3D AST2700_A1_SILICON_REV; sc->sram_size =3D 0x20000; + sc->pcie_num =3D 3; sc->spis_num =3D 3; sc->ehcis_num =3D 4; sc->wdts_num =3D 8; --=20 2.43.0