From nobody Sun Sep 28 16:35:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1757497218307863.0450005399761; Wed, 10 Sep 2025 02:40:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uwHFP-0003s5-5A; Wed, 10 Sep 2025 05:36:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uwHEr-0003ef-Qd for qemu-devel@nongnu.org; Wed, 10 Sep 2025 05:35:45 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uwHEd-0007dx-3f for qemu-devel@nongnu.org; Wed, 10 Sep 2025 05:35:37 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8Dx_tJZRsFoacEIAA--.18681S3; Wed, 10 Sep 2025 17:35:21 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowJAxE+RWRsFoj8+LAA--.52579S3; Wed, 10 Sep 2025 17:35:21 +0800 (CST) From: Song Gao To: maobibo@loongson.cn Cc: qemu-devel@nongnu.org, philmd@linaro.org, jiaxun.yang@flygoat.com Subject: [PATCH v7 01/11] target/loongarch: move some machine define to virt.h Date: Wed, 10 Sep 2025 17:11:40 +0800 Message-Id: <20250910091150.2424979-2-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250910091150.2424979-1-gaosong@loongson.cn> References: <20250910091150.2424979-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJAxE+RWRsFoj8+LAA--.52579S3 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1757497220568154100 Content-Type: text/plain; charset="utf-8" move some machine define to virt.h Signed-off-by: Song Gao Reviewed-by: Bibo Mao --- include/hw/loongarch/virt.h | 19 +++++++++++++++++++ target/loongarch/cpu.h | 21 --------------------- 2 files changed, 19 insertions(+), 21 deletions(-) diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h index 602feab0f0..7120b46714 100644 --- a/include/hw/loongarch/virt.h +++ b/include/hw/loongarch/virt.h @@ -13,6 +13,25 @@ #include "hw/block/flash.h" #include "hw/loongarch/boot.h" =20 +#define IOCSRF_TEMP 0 +#define IOCSRF_NODECNT 1 +#define IOCSRF_MSI 2 +#define IOCSRF_EXTIOI 3 +#define IOCSRF_CSRIPI 4 +#define IOCSRF_FREQCSR 5 +#define IOCSRF_FREQSCALE 6 +#define IOCSRF_DVFSV1 7 +#define IOCSRF_GMOD 9 +#define IOCSRF_VM 11 + +#define VERSION_REG 0x0 +#define FEATURE_REG 0x8 +#define VENDOR_REG 0x10 +#define CPUNAME_REG 0x20 +#define MISC_FUNC_REG 0x420 +#define IOCSRM_EXTIOI_EN 48 +#define IOCSRM_EXTIOI_INT_ENCODE 49 + #define LOONGARCH_MAX_CPUS 256 =20 #define VIRT_FWCFG_BASE 0x1e020000UL diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 7731f6acdc..fd3d94b55a 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -21,27 +21,6 @@ #include "cpu-csr.h" #include "cpu-qom.h" =20 -#define IOCSRF_TEMP 0 -#define IOCSRF_NODECNT 1 -#define IOCSRF_MSI 2 -#define IOCSRF_EXTIOI 3 -#define IOCSRF_CSRIPI 4 -#define IOCSRF_FREQCSR 5 -#define IOCSRF_FREQSCALE 6 -#define IOCSRF_DVFSV1 7 -#define IOCSRF_GMOD 9 -#define IOCSRF_VM 11 - -#define VERSION_REG 0x0 -#define FEATURE_REG 0x8 -#define VENDOR_REG 0x10 -#define CPUNAME_REG 0x20 -#define MISC_FUNC_REG 0x420 -#define IOCSRM_EXTIOI_EN 48 -#define IOCSRM_EXTIOI_INT_ENCODE 49 - -#define IOCSR_MEM_SIZE 0x428 - #define FCSR0_M1 0x1f /* FCSR1 mask, Enables */ #define FCSR0_M2 0x1f1f0000 /* FCSR2 mask, Cause and Flags */ #define FCSR0_M3 0x300 /* FCSR3 mask, Round Mode */ --=20 2.41.0 From nobody Sun Sep 28 16:35:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1757497107169482.7653753880743; Wed, 10 Sep 2025 02:38:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uwHFF-0003kh-8H; Wed, 10 Sep 2025 05:36:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uwHEs-0003el-22 for qemu-devel@nongnu.org; Wed, 10 Sep 2025 05:35:45 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uwHEg-0007e2-I6 for qemu-devel@nongnu.org; Wed, 10 Sep 2025 05:35:41 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8DxP9NZRsFobMEIAA--.18296S3; Wed, 10 Sep 2025 17:35:21 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowJAxE+RWRsFoj8+LAA--.52579S4; Wed, 10 Sep 2025 17:35:21 +0800 (CST) From: Song Gao To: maobibo@loongson.cn Cc: qemu-devel@nongnu.org, philmd@linaro.org, jiaxun.yang@flygoat.com Subject: [PATCH v7 02/11] hw/loongarch: add virt feature avecintc and cpu feature msgint support Date: Wed, 10 Sep 2025 17:11:41 +0800 Message-Id: <20250910091150.2424979-3-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250910091150.2424979-1-gaosong@loongson.cn> References: <20250910091150.2424979-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJAxE+RWRsFoj8+LAA--.52579S4 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1757497109754154100 Content-Type: text/plain; charset="utf-8" Avecintc feature is added in LoongArchVirtMachinState, and it is used to check whether virt machine supports the advanced interrupt controller and by default set avecintc with ON_OFF_AUTO_ON. LoongArchVirtMachineState adds misc_feature and misc_status for misc features and status. and set the default avec feature bit. Msegint feature is added in LoongArchCPU, and it is used to check whether th cpu supports the Message-Interrupts and by default set mesgint with ON_OFF_AUTO_AUTO. Signed-off-by: Song Gao Reviewed-by: Bibo Mao --- hw/loongarch/virt.c | 32 +++++++++++++++++++++++++++ include/hw/loongarch/virt.h | 14 ++++++++++++ target/loongarch/cpu.c | 29 ++++++++++++++++++++++++ target/loongarch/cpu.h | 1 + target/loongarch/loongarch-qmp-cmds.c | 2 +- 5 files changed, 77 insertions(+), 1 deletion(-) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 31215b7785..37c38ae63f 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -48,6 +48,27 @@ #include "qemu/error-report.h" #include "kvm/kvm_loongarch.h" =20 +static void virt_get_avecintc(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + LoongArchVirtMachineState *lvms =3D LOONGARCH_VIRT_MACHINE(obj); + OnOffAuto avecintc =3D lvms->avecintc; + + visit_type_OnOffAuto(v, name, &avecintc, errp); + +} +static void virt_set_avecintc(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + LoongArchVirtMachineState *lvms =3D LOONGARCH_VIRT_MACHINE(obj); + + visit_type_OnOffAuto(v, name, &lvms->avecintc, errp); + if (lvms->avecintc =3D=3D ON_OFF_AUTO_OFF) { + lvms->misc_feature &=3D ~BIT(IOCSRF_AVEC); + lvms->misc_status &=3D ~BIT(IOCSRM_AVEC_EN); + } +} + static void virt_get_veiointc(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -692,6 +713,7 @@ static void virt_init(MachineState *machine) hwaddr base, size, ram_size =3D machine->ram_size; MachineClass *mc =3D MACHINE_GET_CLASS(machine); Object *cpuobj; + LoongArchCPU *cpu; =20 if (!cpu_model) { cpu_model =3D LOONGARCH_CPU_TYPE_NAME("la464"); @@ -717,6 +739,10 @@ static void virt_init(MachineState *machine) } qdev_realize_and_unref(DEVICE(cpuobj), NULL, &error_fatal); } + cpu =3D LOONGARCH_CPU(cpuobj); + if (cpu->msgint !=3D ON_OFF_AUTO_OFF) { + lvms->misc_feature =3D BIT(IOCSRF_AVEC); + } fw_cfg_add_memory(machine); =20 /* Node0 memory */ @@ -847,6 +873,8 @@ static void virt_initfn(Object *obj) if (tcg_enabled()) { lvms->veiointc =3D ON_OFF_AUTO_OFF; } + + lvms->avecintc =3D ON_OFF_AUTO_ON; lvms->acpi =3D ON_OFF_AUTO_AUTO; lvms->oem_id =3D g_strndup(ACPI_BUILD_APPNAME6, 6); lvms->oem_table_id =3D g_strndup(ACPI_BUILD_APPNAME8, 8); @@ -1239,6 +1267,10 @@ static void virt_class_init(ObjectClass *oc, const v= oid *data) NULL, NULL); object_class_property_set_description(oc, "v-eiointc", "Enable Virt Extend I/O Interrupt Controller."= ); + object_class_property_add(oc, "avecintc", "OnOffAuto", + virt_get_avecintc, virt_set_avecintc, NULL, NULL); + object_class_property_set_description(oc, "avecintc", + "Enable Advance Interrupt Controller."); machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); machine_class_allow_dynamic_sysbus_dev(mc, TYPE_UEFI_VARS_SYSBUS); #ifdef CONFIG_TPM diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h index 7120b46714..68b8e92e99 100644 --- a/include/hw/loongarch/virt.h +++ b/include/hw/loongarch/virt.h @@ -23,6 +23,7 @@ #define IOCSRF_DVFSV1 7 #define IOCSRF_GMOD 9 #define IOCSRF_VM 11 +#define IOCSRF_AVEC 15 =20 #define VERSION_REG 0x0 #define FEATURE_REG 0x8 @@ -31,6 +32,7 @@ #define MISC_FUNC_REG 0x420 #define IOCSRM_EXTIOI_EN 48 #define IOCSRM_EXTIOI_INT_ENCODE 49 +#define IOCSRM_AVEC_EN 51 =20 #define LOONGARCH_MAX_CPUS 256 =20 @@ -69,6 +71,7 @@ struct LoongArchVirtMachineState { Notifier powerdown_notifier; OnOffAuto acpi; OnOffAuto veiointc; + OnOffAuto avecintc; char *oem_id; char *oem_table_id; DeviceState *acpi_ged; @@ -84,6 +87,8 @@ struct LoongArchVirtMachineState { DeviceState *extioi; struct memmap_entry *memmap_table; unsigned int memmap_entries; + uint64_t misc_feature; + uint64_t misc_status; }; =20 #define TYPE_LOONGARCH_VIRT_MACHINE MACHINE_TYPE_NAME("virt") @@ -91,6 +96,15 @@ OBJECT_DECLARE_SIMPLE_TYPE(LoongArchVirtMachineState, LO= ONGARCH_VIRT_MACHINE) void virt_acpi_setup(LoongArchVirtMachineState *lvms); void virt_fdt_setup(LoongArchVirtMachineState *lvms); =20 +static inline bool virt_has_avecintc(LoongArchVirtMachineState *lvms) +{ + if (!(lvms->misc_feature & BIT(IOCSRF_AVEC))) { + return false; + } + + return true; +} + static inline bool virt_is_veiointc_enabled(LoongArchVirtMachineState *lvm= s) { if (lvms->veiointc =3D=3D ON_OFF_AUTO_OFF) { diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 55ee317bf2..0258bea6df 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -495,6 +495,31 @@ static void loongarch_set_lasx(Object *obj, bool value= , Error **errp) cpu->env.cpucfg[2] =3D FIELD_DP32(val, CPUCFG2, LASX, value); } =20 +static bool loongarch_get_msgint(Object *obj, Error **errp) +{ + return LOONGARCH_CPU(obj)->msgint !=3D ON_OFF_AUTO_OFF; +} + +static void loongarch_set_msgint(Object *obj, bool value, Error **errp) +{ + LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); + uint32_t val; + + cpu->msgint =3D value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; + + if (kvm_enabled()) { + /* kvm feature detection in function kvm_arch_init_vcpu */ + return; + } + + val =3D cpu->env.cpucfg[1]; + if (cpu->msgint =3D=3D ON_OFF_AUTO_ON) { + if (FIELD_EX32(val, CPUCFG1, MSG_INT) =3D=3D 0) { + cpu->env.cpucfg[1]=3D FIELD_DP32(val, CPUCFG1, MSG_INT, value); + } + } +} + static void loongarch_cpu_post_init(Object *obj) { LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); @@ -503,10 +528,14 @@ static void loongarch_cpu_post_init(Object *obj) cpu->pmu =3D ON_OFF_AUTO_OFF; cpu->lsx =3D ON_OFF_AUTO_AUTO; cpu->lasx =3D ON_OFF_AUTO_AUTO; + cpu->msgint =3D ON_OFF_AUTO_AUTO; + object_property_add_bool(obj, "lsx", loongarch_get_lsx, loongarch_set_lsx); object_property_add_bool(obj, "lasx", loongarch_get_lasx, loongarch_set_lasx); + object_property_add_bool(obj, "msgint", loongarch_get_msgint, + loongarch_set_msgint); /* lbt is enabled only in kvm mode, not supported in tcg mode */ if (kvm_enabled()) { kvm_loongarch_cpu_post_init(cpu); diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index fd3d94b55a..1e8a9dbef8 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -396,6 +396,7 @@ struct ArchCPU { OnOffAuto pmu; OnOffAuto lsx; OnOffAuto lasx; + OnOffAuto msgint; OnOffAuto kvm_pv_ipi; OnOffAuto kvm_steal_time; int32_t socket_id; /* socket-id of this CPU */ diff --git a/target/loongarch/loongarch-qmp-cmds.c b/target/loongarch/loong= arch-qmp-cmds.c index 1d8cd32f5f..152cd4a551 100644 --- a/target/loongarch/loongarch-qmp-cmds.c +++ b/target/loongarch/loongarch-qmp-cmds.c @@ -41,7 +41,7 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **= errp) } =20 static const char *cpu_model_advertised_features[] =3D { - "lsx", "lasx", "lbt", "pmu", "kvm-pv-ipi", "kvm-steal-time", NULL + "lsx", "lasx", "lbt", "pmu", "msgint", "kvm-pv-ipi", "kvm-steal-time",= NULL }; =20 CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType= type, --=20 2.41.0 From nobody Sun Sep 28 16:35:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1757497167188287.46663468845566; Wed, 10 Sep 2025 02:39:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uwHFH-0003m3-Lw; Wed, 10 Sep 2025 05:36:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uwHEr-0003eh-SB for qemu-devel@nongnu.org; Wed, 10 Sep 2025 05:35:45 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uwHEe-0007eA-O4 for qemu-devel@nongnu.org; Wed, 10 Sep 2025 05:35:37 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8BxmdFaRsFob8EIAA--.18879S3; Wed, 10 Sep 2025 17:35:22 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowJAxE+RWRsFoj8+LAA--.52579S5; Wed, 10 Sep 2025 17:35:21 +0800 (CST) From: Song Gao To: maobibo@loongson.cn Cc: qemu-devel@nongnu.org, philmd@linaro.org, jiaxun.yang@flygoat.com Subject: [PATCH v7 03/11] hw/loongarch: add misc register supoort avecintc Date: Wed, 10 Sep 2025 17:11:42 +0800 Message-Id: <20250910091150.2424979-4-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250910091150.2424979-1-gaosong@loongson.cn> References: <20250910091150.2424979-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJAxE+RWRsFoj8+LAA--.52579S5 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1757497168342116600 Content-Type: text/plain; charset="utf-8" Add feature register and misc register for avecintc feature checking and setting Signed-off-by: Song Gao Reviewed-by: Bibo Mao --- hw/loongarch/virt.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 37c38ae63f..0883f3a272 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -561,6 +561,10 @@ static MemTxResult virt_iocsr_misc_write(void *opaque,= hwaddr addr, return MEMTX_OK; } =20 + if (virt_has_avecintc(lvms) && val & BIT(IOCSRM_AVEC_EN)) { + lvms->misc_status |=3D BIT(IOCSRM_AVEC_EN); + } + features =3D address_space_ldl(&lvms->as_iocsr, EXTIOI_VIRT_BASE + EXTIOI_VIRT_CONFIG, attrs, NULL); @@ -596,6 +600,9 @@ static MemTxResult virt_iocsr_misc_read(void *opaque, h= waddr addr, break; case FEATURE_REG: ret =3D BIT(IOCSRF_MSI) | BIT(IOCSRF_EXTIOI) | BIT(IOCSRF_CSRIPI); + if (virt_has_avecintc(lvms)) { + ret |=3D BIT(IOCSRF_AVEC); + } if (kvm_enabled()) { ret |=3D BIT(IOCSRF_VM); } @@ -625,6 +632,10 @@ static MemTxResult virt_iocsr_misc_read(void *opaque, = hwaddr addr, if (features & BIT(EXTIOI_ENABLE_INT_ENCODE)) { ret |=3D BIT_ULL(IOCSRM_EXTIOI_INT_ENCODE); } + if (virt_has_avecintc(lvms) && + (lvms->misc_status & BIT(IOCSRM_AVEC_EN))) { + ret |=3D BIT_ULL(IOCSRM_AVEC_EN); + } break; default: g_assert_not_reached(); --=20 2.41.0 From nobody Sun Sep 28 16:35:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1757497063958778.2401139663853; Wed, 10 Sep 2025 02:37:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uwHFJ-0003nP-W1; Wed, 10 Sep 2025 05:36:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uwHEs-0003ek-2F for qemu-devel@nongnu.org; Wed, 10 Sep 2025 05:35:47 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uwHEg-0007e6-BY for qemu-devel@nongnu.org; Wed, 10 Sep 2025 05:35:41 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8Bx379aRsFodcEIAA--.17339S3; Wed, 10 Sep 2025 17:35:22 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowJAxE+RWRsFoj8+LAA--.52579S6; Wed, 10 Sep 2025 17:35:22 +0800 (CST) From: Song Gao To: maobibo@loongson.cn Cc: qemu-devel@nongnu.org, philmd@linaro.org, jiaxun.yang@flygoat.com Subject: [PATCH v7 04/11] loongarch: add a advance interrupt controller device Date: Wed, 10 Sep 2025 17:11:43 +0800 Message-Id: <20250910091150.2424979-5-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250910091150.2424979-1-gaosong@loongson.cn> References: <20250910091150.2424979-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJAxE+RWRsFoj8+LAA--.52579S6 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1757497064914116600 Content-Type: text/plain; charset="utf-8" Add Loongarch advance interrupt controller device base Definition. Signed-off-by: Song Gao Reviewed-by: Bibo Mao --- hw/intc/Kconfig | 3 ++ hw/intc/loongarch_avec.c | 68 ++++++++++++++++++++++++++++++++ hw/intc/meson.build | 1 + hw/loongarch/Kconfig | 1 + include/hw/intc/loongarch_avec.h | 35 ++++++++++++++++ 5 files changed, 108 insertions(+) create mode 100644 hw/intc/loongarch_avec.c create mode 100644 include/hw/intc/loongarch_avec.h diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index 7547528f2c..b9266dc269 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -109,3 +109,6 @@ config LOONGARCH_PCH_MSI =20 config LOONGARCH_EXTIOI bool + +config LOONGARCH_AVEC + bool diff --git a/hw/intc/loongarch_avec.c b/hw/intc/loongarch_avec.c new file mode 100644 index 0000000000..5a3e7ecc03 --- /dev/null +++ b/hw/intc/loongarch_avec.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * QEMU Loongson Advance interrupt controller. + * + * Copyright (C) 2025 Loongson Technology Corporation Limited + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/irq.h" +#include "hw/intc/loongarch_pch_msi.h" +#include "hw/intc/loongarch_pch_pic.h" +#include "hw/intc/loongarch_avec.h" +#include "hw/pci/msi.h" +#include "hw/misc/unimp.h" +#include "migration/vmstate.h" +#include "trace.h" +#include "hw/qdev-properties.h" + + +static void loongarch_avec_realize(DeviceState *dev, Error **errp) +{ + LoongArchAVECClass *lac =3D LOONGARCH_AVEC_GET_CLASS(dev); + + Error *local_err =3D NULL; + lac->parent_realize(dev, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + return; +} + +static void loongarch_avec_unrealize(DeviceState *dev) +{ + return; +} + +static void loongarch_avec_init(Object *obj) +{ + return; +} + +static void loongarch_avec_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + LoongArchAVECClass *lac =3D LOONGARCH_AVEC_CLASS(klass); + + dc->unrealize =3D loongarch_avec_unrealize; + device_class_set_parent_realize(dc, loongarch_avec_realize, + &lac->parent_realize); +} + +static const TypeInfo loongarch_avec_info =3D { + .name =3D TYPE_LOONGARCH_AVEC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(LoongArchAVECState), + .instance_init =3D loongarch_avec_init, + .class_init =3D loongarch_avec_class_init, +}; + +static void loongarch_avec_register_types(void) +{ + type_register_static(&loongarch_avec_info); +} + +type_init(loongarch_avec_register_types) diff --git a/hw/intc/meson.build b/hw/intc/meson.build index 3efb276b6e..6aae4bbe53 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -80,3 +80,4 @@ specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true= : files('loongarch_pch_ specific_ss.add(when: 'CONFIG_LOONGARCH_EXTIOI', if_true: files('loongarch= _extioi.c', 'loongarch_extioi_common.c')) specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_LOONGARCH_EXTIOI'], if_true: files('loongarch_extioi_kvm.c')) +specific_ss.add(when: 'CONFIG_LOONGARCH_AVEC', if_true: files('loongarch_a= vec.c')) diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig index bb2838b7b5..1bf240b1e2 100644 --- a/hw/loongarch/Kconfig +++ b/hw/loongarch/Kconfig @@ -15,6 +15,7 @@ config LOONGARCH_VIRT select LOONGARCH_PCH_PIC select LOONGARCH_PCH_MSI select LOONGARCH_EXTIOI + select LOONGARCH_AVEC select LS7A_RTC select SMBIOS select ACPI_CPU_HOTPLUG diff --git a/include/hw/intc/loongarch_avec.h b/include/hw/intc/loongarch_a= vec.h new file mode 100644 index 0000000000..92e2ca9590 --- /dev/null +++ b/include/hw/intc/loongarch_avec.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * LoongArch Advance interrupt controller definitions + * + * Copyright (C) 2025 Loongson Technology Corporation Limited + */ + +#include "qom/object.h" +#include "hw/sysbus.h" +#include "hw/loongarch/virt.h" + + +#define NR_VECTORS 256 + +#define TYPE_LOONGARCH_AVEC "loongarch_avec" +OBJECT_DECLARE_TYPE(LoongArchAVECState, LoongArchAVECClass, LOONGARCH_AVEC) + +typedef struct AVECCore { + CPUState *cpu; + qemu_irq parent_irq; + uint64_t arch_id; +} AVECCore; + +struct LoongArchAVECState { + SysBusDevice parent_obj; + AVECCore *cpu; + uint32_t num_cpu; +}; + +struct LoongArchAVECClass { + SysBusDeviceClass parent_class; + + DeviceRealize parent_realize; + DeviceUnrealize parent_unrealize; +}; --=20 2.41.0 From nobody Sun Sep 28 16:35:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1757497028125404.6405398385208; Wed, 10 Sep 2025 02:37:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uwHFF-0003kg-8t; Wed, 10 Sep 2025 05:36:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uwHEr-0003ei-RG for qemu-devel@nongnu.org; Wed, 10 Sep 2025 05:35:45 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uwHEc-0007e4-Pa for qemu-devel@nongnu.org; Wed, 10 Sep 2025 05:35:40 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8Cx6tFaRsFodMEIAA--.18812S3; Wed, 10 Sep 2025 17:35:22 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowJAxE+RWRsFoj8+LAA--.52579S7; Wed, 10 Sep 2025 17:35:22 +0800 (CST) From: Song Gao To: maobibo@loongson.cn Cc: qemu-devel@nongnu.org, philmd@linaro.org, jiaxun.yang@flygoat.com Subject: [PATCH v7 05/11] target/loongarch: add msg interrupt CSR registers Date: Wed, 10 Sep 2025 17:11:44 +0800 Message-Id: <20250910091150.2424979-6-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250910091150.2424979-1-gaosong@loongson.cn> References: <20250910091150.2424979-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJAxE+RWRsFoj8+LAA--.52579S7 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1757497028604116600 Content-Type: text/plain; charset="utf-8" include CSR_MSGIS0-3, CSR_MSGIR and CSR_MSGIE. Signed-off-by: Song Gao Reviewed-by: Bibo Mao --- target/loongarch/cpu-csr.h | 3 +++ target/loongarch/cpu.h | 11 +++++++++++ target/loongarch/machine.c | 25 +++++++++++++++++++++++-- 3 files changed, 37 insertions(+), 2 deletions(-) diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h index 0834e91f30..4792677086 100644 --- a/target/loongarch/cpu-csr.h +++ b/target/loongarch/cpu-csr.h @@ -186,6 +186,9 @@ FIELD(CSR_MERRCTL, ISMERR, 0, 1) =20 #define LOONGARCH_CSR_CTAG 0x98 /* TagLo + TagHi */ =20 +#define LOONGARCH_CSR_MSGIS(N) (0xa0 + N) +#define LOONGARCH_CSR_MSGIR 0xa4 + /* Direct map windows CSRs*/ #define LOONGARCH_CSR_DMW(N) (0x180 + N) FIELD(CSR_DMW, PLV0, 0, 1) diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 1e8a9dbef8..807a710810 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -233,6 +233,13 @@ FIELD(TLB_MISC, ASID, 1, 10) FIELD(TLB_MISC, VPPN, 13, 35) FIELD(TLB_MISC, PS, 48, 6) =20 +/*Msg interrupt registers */ +#define N_MSGIS 4 +FIELD(CSR_MSGIS, IS, 0, 63) +FIELD(CSR_MSGIR, INTNUM, 0, 8) +FIELD(CSR_MSGIR, ACTIVE, 31, 1) +FIELD(CSR_MSGIE, PT, 0, 8) + #define LSX_LEN (128) #define LASX_LEN (256) =20 @@ -350,6 +357,10 @@ typedef struct CPUArchState { uint64_t CSR_DBG; uint64_t CSR_DERA; uint64_t CSR_DSAVE; + /* Msg interrupt registers */ + uint64_t CSR_MSGIS[N_MSGIS]; + uint64_t CSR_MSGIR; + uint64_t CSR_MSGIE; struct { uint64_t guest_addr; } stealtime; diff --git a/target/loongarch/machine.c b/target/loongarch/machine.c index 4e70f5c879..0cc787462c 100644 --- a/target/loongarch/machine.c +++ b/target/loongarch/machine.c @@ -45,6 +45,26 @@ static const VMStateDescription vmstate_fpu =3D { }, }; =20 +static bool avec_needed(void *opaque) +{ + LoongArchCPU *cpu =3D opaque; + + return FIELD_EX64(cpu->env.cpucfg[1], CPUCFG1, MSG_INT); +} + +static const VMStateDescription vmstate_avec =3D { + .name =3D "cpu/msg", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D avec_needed, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT64_ARRAY(env.CSR_MSGIS, LoongArchCPU, N_MSGIS), + VMSTATE_UINT64(env.CSR_MSGIR, LoongArchCPU), + VMSTATE_UINT64(env.CSR_MSGIE, LoongArchCPU), + VMSTATE_END_OF_LIST() + }, +}; + static const VMStateDescription vmstate_lsxh_reg =3D { .name =3D "lsxh_reg", .version_id =3D 1, @@ -168,8 +188,8 @@ static const VMStateDescription vmstate_tlb =3D { /* LoongArch CPU state */ const VMStateDescription vmstate_loongarch_cpu =3D { .name =3D "cpu", - .version_id =3D 3, - .minimum_version_id =3D 3, + .version_id =3D 4, + .minimum_version_id =3D 4, .fields =3D (const VMStateField[]) { VMSTATE_UINTTL_ARRAY(env.gpr, LoongArchCPU, 32), VMSTATE_UINTTL(env.pc, LoongArchCPU), @@ -245,6 +265,7 @@ const VMStateDescription vmstate_loongarch_cpu =3D { &vmstate_tlb, #endif &vmstate_lbt, + &vmstate_avec, NULL } }; --=20 2.41.0 From nobody Sun Sep 28 16:35:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1757497111438127.44859117243152; Wed, 10 Sep 2025 02:38:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uwHFK-0003o0-9W; Wed, 10 Sep 2025 05:36:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uwHF8-0003j8-Eh for qemu-devel@nongnu.org; Wed, 10 Sep 2025 05:35:59 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uwHEg-0007e7-CW for qemu-devel@nongnu.org; Wed, 10 Sep 2025 05:35:47 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8AxSNFbRsFoeMEIAA--.18884S3; Wed, 10 Sep 2025 17:35:23 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowJAxE+RWRsFoj8+LAA--.52579S8; Wed, 10 Sep 2025 17:35:22 +0800 (CST) From: Song Gao To: maobibo@loongson.cn Cc: qemu-devel@nongnu.org, philmd@linaro.org, jiaxun.yang@flygoat.com Subject: [PATCH v7 06/11] hw/loongarch: AVEC controller add a MemoryRegion Date: Wed, 10 Sep 2025 17:11:45 +0800 Message-Id: <20250910091150.2424979-7-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250910091150.2424979-1-gaosong@loongson.cn> References: <20250910091150.2424979-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJAxE+RWRsFoj8+LAA--.52579S8 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1757497113648116600 Content-Type: text/plain; charset="utf-8" the AVEC controller use [2fe00000-2ff000000) Memory. Signed-off-by: Song Gao Reviewed-by: Bibo Mao --- hw/intc/loongarch_avec.c | 24 ++++++++++++++++++++ hw/loongarch/virt.c | 39 +++++++++++++++++++++++++++++++- include/hw/intc/loongarch_avec.h | 1 + include/hw/loongarch/virt.h | 1 + include/hw/pci-host/ls7a.h | 2 ++ 5 files changed, 66 insertions(+), 1 deletion(-) diff --git a/hw/intc/loongarch_avec.c b/hw/intc/loongarch_avec.c index 5a3e7ecc03..253bab5461 100644 --- a/hw/intc/loongarch_avec.c +++ b/hw/intc/loongarch_avec.c @@ -17,6 +17,24 @@ #include "trace.h" #include "hw/qdev-properties.h" =20 +static uint64_t loongarch_avec_mem_read(void *opaque, + hwaddr addr, unsigned size) +{ + return 0; +} + +static void loongarch_avec_mem_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + return; +} + + +static const MemoryRegionOps loongarch_avec_ops =3D { + .read =3D loongarch_avec_mem_read, + .write =3D loongarch_avec_mem_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; =20 static void loongarch_avec_realize(DeviceState *dev, Error **errp) { @@ -39,6 +57,12 @@ static void loongarch_avec_unrealize(DeviceState *dev) =20 static void loongarch_avec_init(Object *obj) { + LoongArchAVECState *s =3D LOONGARCH_AVEC(obj); + SysBusDevice *shd =3D SYS_BUS_DEVICE(obj); + memory_region_init_io(&s->avec_mmio, OBJECT(s), &loongarch_avec_ops, + s, TYPE_LOONGARCH_AVEC, VIRT_AVEC_MSG_OFFSET); + sysbus_init_mmio(shd, &s->avec_mmio); + msi_nonbroken =3D true; return; } =20 diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 0883f3a272..c8fb31c485 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -28,6 +28,7 @@ #include "hw/intc/loongarch_extioi.h" #include "hw/intc/loongarch_pch_pic.h" #include "hw/intc/loongarch_pch_msi.h" +#include "hw/intc/loongarch_avec.h" #include "hw/pci-host/ls7a.h" #include "hw/pci-host/gpex.h" #include "hw/misc/unimp.h" @@ -383,7 +384,7 @@ static void virt_cpu_irq_init(LoongArchVirtMachineState= *lvms) static void virt_irq_init(LoongArchVirtMachineState *lvms) { DeviceState *pch_pic, *pch_msi; - DeviceState *ipi, *extioi; + DeviceState *ipi, *extioi, *avec; SysBusDevice *d; int i, start, num; =20 @@ -429,6 +430,33 @@ static void virt_irq_init(LoongArchVirtMachineState *l= vms) * +--------+ +---------+ +---------+ * | UARTs | | Devices | | Devices | * +--------+ +---------+ +---------+ + * + * + * Advanced Extended IRQ model + * + * +-----+ +---------------------------------+ +-------+ + * | IPI | --> | CPUINTC | <-- | Timer | + * +-----+ +---------------------------------+ +-------+ + * ^ ^ ^ + * | | | + * +-------------+ +----------+ +---------+ +-------+ + * | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs | + * +-------------+ +----------+ +---------+ +-------+ + * ^ ^ ^ + * | | | + * +---------+ +---------+ | + * | PCH-PIC | | PCH-MSI | | + * +---------+ +---------+ | + * ^ ^ ^ | + * | | | | + * +---------+ +---------+ +---------+ + * | Devices | | PCH-LPC | | Devices | + * +---------+ +---------+ +---------+ + * ^ + * | + * +---------+ + * | Devices | + * +---------+ */ =20 /* Create IPI device */ @@ -436,6 +464,15 @@ static void virt_irq_init(LoongArchVirtMachineState *l= vms) lvms->ipi =3D ipi; sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); =20 + /* Create AVEC device*/ + if (virt_has_avecintc(lvms)) { + avec =3D qdev_new(TYPE_LOONGARCH_AVEC); + lvms->avec =3D avec; + sysbus_realize_and_unref(SYS_BUS_DEVICE(avec), &error_fatal); + memory_region_add_subregion(get_system_memory(), VIRT_AVEC_BASE, + sysbus_mmio_get_region(SYS_BUS_DEVICE(avec), 0)); + } + /* Create EXTIOI device */ extioi =3D qdev_new(TYPE_LOONGARCH_EXTIOI); lvms->extioi =3D extioi; diff --git a/include/hw/intc/loongarch_avec.h b/include/hw/intc/loongarch_a= vec.h index 92e2ca9590..3e8cf7d2c1 100644 --- a/include/hw/intc/loongarch_avec.h +++ b/include/hw/intc/loongarch_avec.h @@ -23,6 +23,7 @@ typedef struct AVECCore { =20 struct LoongArchAVECState { SysBusDevice parent_obj; + MemoryRegion avec_mmio; AVECCore *cpu; uint32_t num_cpu; }; diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h index 68b8e92e99..bc3cee705d 100644 --- a/include/hw/loongarch/virt.h +++ b/include/hw/loongarch/virt.h @@ -89,6 +89,7 @@ struct LoongArchVirtMachineState { unsigned int memmap_entries; uint64_t misc_feature; uint64_t misc_status; + DeviceState *avec; }; =20 #define TYPE_LOONGARCH_VIRT_MACHINE MACHINE_TYPE_NAME("virt") diff --git a/include/hw/pci-host/ls7a.h b/include/hw/pci-host/ls7a.h index 79d4ea8501..199f47ecc0 100644 --- a/include/hw/pci-host/ls7a.h +++ b/include/hw/pci-host/ls7a.h @@ -24,6 +24,8 @@ #define VIRT_PCH_REG_BASE 0x10000000UL #define VIRT_IOAPIC_REG_BASE (VIRT_PCH_REG_BASE) #define VIRT_PCH_MSI_ADDR_LOW 0x2FF00000UL +#define VIRT_AVEC_MSG_OFFSET 0x1000000UL +#define VIRT_AVEC_BASE (VIRT_PCH_MSI_ADDR_LOW - VIRT_AVEC_MSG_OF= FSET) #define VIRT_PCH_REG_SIZE 0x400 #define VIRT_PCH_MSI_SIZE 0x8 =20 --=20 2.41.0 From nobody Sun Sep 28 16:35:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1757497005559252.8079655892526; Wed, 10 Sep 2025 02:36:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uwHFB-0003jz-NU; Wed, 10 Sep 2025 05:36:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uwHEt-0003es-Ch for qemu-devel@nongnu.org; Wed, 10 Sep 2025 05:35:47 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uwHEe-0007eG-2K for qemu-devel@nongnu.org; Wed, 10 Sep 2025 05:35:42 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8CxaNFbRsFoe8EIAA--.18810S3; Wed, 10 Sep 2025 17:35:23 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowJAxE+RWRsFoj8+LAA--.52579S9; Wed, 10 Sep 2025 17:35:23 +0800 (CST) From: Song Gao To: maobibo@loongson.cn Cc: qemu-devel@nongnu.org, philmd@linaro.org, jiaxun.yang@flygoat.com Subject: [PATCH v7 07/11] hw/loongarch: Implement avec controller imput and output pins Date: Wed, 10 Sep 2025 17:11:46 +0800 Message-Id: <20250910091150.2424979-8-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250910091150.2424979-1-gaosong@loongson.cn> References: <20250910091150.2424979-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJAxE+RWRsFoj8+LAA--.52579S9 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1757497009116116600 Content-Type: text/plain; charset="utf-8" the AVEC controller supports 256*256 irqs input, all the irqs connect CPU I= NT_AVEC irq Signed-off-by: Song Gao --- hw/intc/loongarch_avec.c | 20 ++++++++++++++++++++ target/loongarch/cpu.h | 3 ++- 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/hw/intc/loongarch_avec.c b/hw/intc/loongarch_avec.c index 253bab5461..1f9f376898 100644 --- a/hw/intc/loongarch_avec.c +++ b/hw/intc/loongarch_avec.c @@ -38,7 +38,12 @@ static const MemoryRegionOps loongarch_avec_ops =3D { =20 static void loongarch_avec_realize(DeviceState *dev, Error **errp) { + LoongArchAVECState *s =3D LOONGARCH_AVEC(dev); LoongArchAVECClass *lac =3D LOONGARCH_AVEC_GET_CLASS(dev); + MachineState *machine =3D MACHINE(qdev_get_machine()); + MachineClass *mc =3D MACHINE_GET_CLASS(machine); + const CPUArchIdList *id_list; + int i; =20 Error *local_err =3D NULL; lac->parent_realize(dev, &local_err); @@ -47,6 +52,21 @@ static void loongarch_avec_realize(DeviceState *dev, Err= or **errp) return; } =20 + assert(mc->possible_cpu_arch_ids); + id_list =3D mc->possible_cpu_arch_ids(machine); + s->num_cpu =3D id_list->len; + s->cpu =3D g_new(AVECCore, s->num_cpu); + if (s->cpu =3D=3D NULL) { + error_setg(errp, "Memory allocation for AVECCore fail"); + return; + } + + for (i =3D 0; i < s->num_cpu; i++) { + s->cpu[i].arch_id =3D id_list->cpus[i].arch_id; + s->cpu[i].cpu =3D CPU(id_list->cpus[i].cpu); + qdev_init_gpio_out(dev, &s->cpu[i].parent_irq, 1); + } + return; } =20 diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 807a710810..91261bab98 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -217,9 +217,10 @@ FIELD(CSR_CRMD, WE, 9, 1) extern const char * const regnames[32]; extern const char * const fregnames[32]; =20 -#define N_IRQS 13 +#define N_IRQS 15 #define IRQ_TIMER 11 #define IRQ_IPI 12 +#define INT_AVEC 14 =20 #define LOONGARCH_STLB 2048 /* 2048 STLB */ #define LOONGARCH_MTLB 64 /* 64 MTLB */ --=20 2.41.0 From nobody Sun Sep 28 16:35:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1757497022309190.0411014607231; Wed, 10 Sep 2025 02:37:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uwHF6-0003gs-KH; Wed, 10 Sep 2025 05:35:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uwHEm-0003de-Oh for qemu-devel@nongnu.org; Wed, 10 Sep 2025 05:35:37 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uwHEd-0007eK-1i for qemu-devel@nongnu.org; Wed, 10 Sep 2025 05:35:32 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8Bx2tFbRsFofsEIAA--.18939S3; Wed, 10 Sep 2025 17:35:23 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowJAxE+RWRsFoj8+LAA--.52579S10; Wed, 10 Sep 2025 17:35:23 +0800 (CST) From: Song Gao To: maobibo@loongson.cn Cc: qemu-devel@nongnu.org, philmd@linaro.org, jiaxun.yang@flygoat.com Subject: [PATCH v7 08/11] hw/loongarch: Implement avec set irq Date: Wed, 10 Sep 2025 17:11:47 +0800 Message-Id: <20250910091150.2424979-9-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250910091150.2424979-1-gaosong@loongson.cn> References: <20250910091150.2424979-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJAxE+RWRsFoj8+LAA--.52579S10 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1757497026416154100 Content-Type: text/plain; charset="utf-8" Implement avec set irq and update CSR_MSGIS. Signed-off-by: Song Gao Reviewed-by: Bibo Mao --- hw/intc/loongarch_avec.c | 32 ++++++++++++++++++++++++++++++-- 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/hw/intc/loongarch_avec.c b/hw/intc/loongarch_avec.c index 1f9f376898..0c90579de2 100644 --- a/hw/intc/loongarch_avec.c +++ b/hw/intc/loongarch_avec.c @@ -16,6 +16,14 @@ #include "migration/vmstate.h" #include "trace.h" #include "hw/qdev-properties.h" +#include "target/loongarch/cpu.h" +#include "qemu/error-report.h" +#include "system/hw_accel.h" + +/* msg addr field */ +FIELD(MSG_ADDR, IRQ_NUM, 4, 8) +FIELD(MSG_ADDR, CPU_NUM, 12, 8) +FIELD(MSG_ADDR, FIX, 28, 12) =20 static uint64_t loongarch_avec_mem_read(void *opaque, hwaddr addr, unsigned size) @@ -23,13 +31,33 @@ static uint64_t loongarch_avec_mem_read(void *opaque, return 0; } =20 +static void do_set_vcpu_avec_irq(CPUState *cs, run_on_cpu_data data) +{ + int irq =3D data.host_int; + CPULoongArchState *env; + + env =3D &LOONGARCH_CPU(cs)->env; + cpu_synchronize_state(cs); + set_bit(irq, env->CSR_MSGIS); +} + static void loongarch_avec_mem_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { - return; + int irq_num, cpu_num =3D 0; + LoongArchAVECState *s =3D LOONGARCH_AVEC(opaque); + uint64_t msg_addr =3D addr + VIRT_AVEC_BASE; + CPUState *cs; + + cpu_num =3D FIELD_EX64(msg_addr, MSG_ADDR, CPU_NUM); + cs =3D cpu_by_arch_id(cpu_num); + irq_num =3D FIELD_EX64(msg_addr, MSG_ADDR, IRQ_NUM); + + async_run_on_cpu(cs, do_set_vcpu_avec_irq, + RUN_ON_CPU_HOST_INT(irq_num)); + qemu_set_irq(s->cpu[cpu_num].parent_irq, 1); } =20 - static const MemoryRegionOps loongarch_avec_ops =3D { .read =3D loongarch_avec_mem_read, .write =3D loongarch_avec_mem_write, --=20 2.41.0 From nobody Sun Sep 28 16:35:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1757497006845192.4230415885263; Wed, 10 Sep 2025 02:36:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uwHFJ-0003mm-KN; Wed, 10 Sep 2025 05:36:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uwHEr-0003eg-Qf for qemu-devel@nongnu.org; Wed, 10 Sep 2025 05:35:45 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uwHEg-0007eb-Il for qemu-devel@nongnu.org; Wed, 10 Sep 2025 05:35:41 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8DxO9JbRsFogcEIAA--.18509S3; Wed, 10 Sep 2025 17:35:23 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowJAxE+RWRsFoj8+LAA--.52579S11; Wed, 10 Sep 2025 17:35:23 +0800 (CST) From: Song Gao To: maobibo@loongson.cn Cc: qemu-devel@nongnu.org, philmd@linaro.org, jiaxun.yang@flygoat.com Subject: [PATCH v7 09/11] target/loongarch: Add CSR_ESTAT.bit15 and CSR_ECFG.bit15 for msg interrupts. Date: Wed, 10 Sep 2025 17:11:48 +0800 Message-Id: <20250910091150.2424979-10-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250910091150.2424979-1-gaosong@loongson.cn> References: <20250910091150.2424979-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJAxE+RWRsFoj8+LAA--.52579S11 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1757497010232154100 Content-Type: text/plain; charset="utf-8" Add CSR_ESTAT.bit15 and CSR_ECFG.bit15 for AVEC irq. Reviewed-by: Bibo Mao Signed-off-by: Song Gao --- target/loongarch/cpu-csr.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h index 4792677086..f296eb8d06 100644 --- a/target/loongarch/cpu-csr.h +++ b/target/loongarch/cpu-csr.h @@ -34,11 +34,13 @@ FIELD(CSR_MISC, ALCL, 12, 4) FIELD(CSR_MISC, DWPL, 16, 3) =20 #define LOONGARCH_CSR_ECFG 0x4 /* Exception config */ -FIELD(CSR_ECFG, LIE, 0, 13) +FIELD(CSR_ECFG, LIE, 0, 15) /* bit 15 is msg interrupt enabled */ +FIELD(CSR_ECFG, MSGINT, 14, 1) FIELD(CSR_ECFG, VS, 16, 3) =20 #define LOONGARCH_CSR_ESTAT 0x5 /* Exception status */ -FIELD(CSR_ESTAT, IS, 0, 13) +FIELD(CSR_ESTAT, IS, 0, 15) /* bit 15 is msg interrupt enabled */ +FIELD(CSR_ESTAT, MSGINT, 14, 1) FIELD(CSR_ESTAT, ECODE, 16, 6) FIELD(CSR_ESTAT, ESUBCODE, 22, 9) =20 --=20 2.41.0 From nobody Sun Sep 28 16:35:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1757497002209322.1184323906451; Wed, 10 Sep 2025 02:36:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uwHFL-0003p2-TK; Wed, 10 Sep 2025 05:36:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uwHF6-0003iz-Dj for qemu-devel@nongnu.org; Wed, 10 Sep 2025 05:35:58 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uwHEj-0007er-AW for qemu-devel@nongnu.org; Wed, 10 Sep 2025 05:35:46 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8Dx_tJdRsFoh8EIAA--.18682S3; Wed, 10 Sep 2025 17:35:25 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowJAxE+RWRsFoj8+LAA--.52579S12; Wed, 10 Sep 2025 17:35:23 +0800 (CST) From: Song Gao To: maobibo@loongson.cn Cc: qemu-devel@nongnu.org, philmd@linaro.org, jiaxun.yang@flygoat.com Subject: [PATCH v7 10/11] target/loongarch:Implement csrrd CSR_MSGIR register Date: Wed, 10 Sep 2025 17:11:49 +0800 Message-Id: <20250910091150.2424979-11-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250910091150.2424979-1-gaosong@loongson.cn> References: <20250910091150.2424979-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJAxE+RWRsFoj8+LAA--.52579S12 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1757497007683154100 Content-Type: text/plain; charset="utf-8" implement the read-clear feature for CSR_MSGIR register. Reviewed-by: Bibo Mao Signed-off-by: Song Gao --- target/loongarch/csr.c | 5 +++++ target/loongarch/tcg/csr_helper.c | 21 +++++++++++++++++++ target/loongarch/tcg/helper.h | 1 + .../tcg/insn_trans/trans_privileged.c.inc | 1 + 4 files changed, 28 insertions(+) diff --git a/target/loongarch/csr.c b/target/loongarch/csr.c index 7ea0a30450..f973780bba 100644 --- a/target/loongarch/csr.c +++ b/target/loongarch/csr.c @@ -97,6 +97,11 @@ static CSRInfo csr_info[] =3D { CSR_OFF(DBG), CSR_OFF(DERA), CSR_OFF(DSAVE), + CSR_OFF_ARRAY(MSGIS, 0), + CSR_OFF_ARRAY(MSGIS, 1), + CSR_OFF_ARRAY(MSGIS, 2), + CSR_OFF_ARRAY(MSGIS, 3), + CSR_OFF(MSGIR), }; =20 CSRInfo *get_csr(unsigned int csr_num) diff --git a/target/loongarch/tcg/csr_helper.c b/target/loongarch/tcg/csr_h= elper.c index 0d99e2c92b..ae0046f42c 100644 --- a/target/loongarch/tcg/csr_helper.c +++ b/target/loongarch/tcg/csr_helper.c @@ -73,6 +73,27 @@ target_ulong helper_csrrd_tval(CPULoongArchState *env) return cpu_loongarch_get_constant_timer_ticks(cpu); } =20 +target_ulong helper_csrrd_msgir(CPULoongArchState *env) +{ + int irq, new; + + irq =3D find_first_bit(env->CSR_MSGIS, 256); + if (irq < 256) { + clear_bit(irq, env->CSR_MSGIS); + new =3D find_first_bit(env->CSR_MSGIS, 256); + if (new < 256) { + return irq; + } + + env->CSR_ESTAT =3D FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, MSGINT, 0= ); + } else { + /* bit 31 set 1 for no invalid irq */ + irq =3D BIT(31); + } + + return irq; +} + target_ulong helper_csrwr_estat(CPULoongArchState *env, target_ulong val) { int64_t old_v =3D env->CSR_ESTAT; diff --git a/target/loongarch/tcg/helper.h b/target/loongarch/tcg/helper.h index 1d5cb0198c..db57dbfc16 100644 --- a/target/loongarch/tcg/helper.h +++ b/target/loongarch/tcg/helper.h @@ -100,6 +100,7 @@ DEF_HELPER_1(rdtime_d, i64, env) DEF_HELPER_1(csrrd_pgd, i64, env) DEF_HELPER_1(csrrd_cpuid, i64, env) DEF_HELPER_1(csrrd_tval, i64, env) +DEF_HELPER_1(csrrd_msgir, i64, env) DEF_HELPER_2(csrwr_stlbps, i64, env, tl) DEF_HELPER_2(csrwr_estat, i64, env, tl) DEF_HELPER_2(csrwr_asid, i64, env, tl) diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/targe= t/loongarch/tcg/insn_trans/trans_privileged.c.inc index 34cfab8879..a407ab51b7 100644 --- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc +++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc @@ -83,6 +83,7 @@ void loongarch_csr_translate_init(void) SET_CSR_FUNC(TCFG, NULL, gen_helper_csrwr_tcfg); SET_CSR_FUNC(TVAL, gen_helper_csrrd_tval, NULL); SET_CSR_FUNC(TICLR, NULL, gen_helper_csrwr_ticlr); + SET_CSR_FUNC(MSGIR, gen_helper_csrrd_msgir, NULL); } #undef SET_CSR_FUNC =20 --=20 2.41.0 From nobody Sun Sep 28 16:35:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1757497211189999.3622970463222; Wed, 10 Sep 2025 02:40:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uwHG0-0004dW-Sy; Wed, 10 Sep 2025 05:36:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uwHFz-0004cE-KQ for qemu-devel@nongnu.org; Wed, 10 Sep 2025 05:36:51 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uwHFq-0007mC-Bm for qemu-devel@nongnu.org; Wed, 10 Sep 2025 05:36:51 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8Bx379eRsFoisEIAA--.17341S3; Wed, 10 Sep 2025 17:35:26 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowJAxE+RWRsFoj8+LAA--.52579S13; Wed, 10 Sep 2025 17:35:25 +0800 (CST) From: Song Gao To: maobibo@loongson.cn Cc: qemu-devel@nongnu.org, philmd@linaro.org, jiaxun.yang@flygoat.com Subject: [PATCH v7 11/11] hw/loongarch: Implement AVEC plug/unplug interfaces Date: Wed, 10 Sep 2025 17:11:50 +0800 Message-Id: <20250910091150.2424979-12-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250910091150.2424979-1-gaosong@loongson.cn> References: <20250910091150.2424979-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJAxE+RWRsFoj8+LAA--.52579S13 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1757497234932154100 Content-Type: text/plain; charset="utf-8" when cpu added, connect avec irq to cpu INT_AVEC irq pin. Reviewed-by: Bibo Mao Signed-off-by: Song Gao --- hw/intc/loongarch_avec.c | 71 ++++++++++++++++++++++++++++++++++++++++ hw/loongarch/virt.c | 11 +++++++ 2 files changed, 82 insertions(+) diff --git a/hw/intc/loongarch_avec.c b/hw/intc/loongarch_avec.c index 1bf0dcda24..9faf28a90c 100644 --- a/hw/intc/loongarch_avec.c +++ b/hw/intc/loongarch_avec.c @@ -114,14 +114,81 @@ static void loongarch_avec_init(Object *obj) return; } =20 +static AVECCore *loongarch_avec_get_cpu(LoongArchAVECState *s, + DeviceState *dev) +{ + CPUClass *k =3D CPU_GET_CLASS(dev); + uint64_t arch_id =3D k->get_arch_id(CPU(dev)); + int i; + + for (i =3D 0; i < s->num_cpu; i++) { + if (s->cpu[i].arch_id =3D=3D arch_id) { + return &s->cpu[i]; + } + } + + return NULL; +} + +static void loongarch_avec_cpu_plug(HotplugHandler *hotplug_dev, + DeviceState *dev, Error **errp) +{ + LoongArchAVECState *s =3D LOONGARCH_AVEC(hotplug_dev); + Object *obj =3D OBJECT(dev); + AVECCore *core; + int index; + + if (!object_dynamic_cast(obj, TYPE_LOONGARCH_CPU)) { + warn_report("LoongArch AVEC: Invalid %s device type", + object_get_typename(obj)); + return; + } + core =3D loongarch_avec_get_cpu(s, dev); + if (!core) { + return; + } + + core->cpu =3D CPU(dev); + index =3D core - s->cpu; + + /* connect avec msg irq to cpu irq */ + qdev_connect_gpio_out(DEVICE(s), index, qdev_get_gpio_in(dev, INT_AVEC= )); + return; +} + +static void loongarch_avec_cpu_unplug(HotplugHandler *hotplug_dev, + DeviceState *dev, Error **errp) +{ + LoongArchAVECState *s =3D LOONGARCH_AVEC(hotplug_dev); + Object *obj =3D OBJECT(dev); + AVECCore *core; + + if (!object_dynamic_cast(obj, TYPE_LOONGARCH_CPU)) { + warn_report("LoongArch AVEC: Invalid %s device type", + object_get_typename(obj)); + return; + } + + core =3D loongarch_avec_get_cpu(s, dev); + + if (!core) { + return; + } + + core->cpu =3D NULL; +} + static void loongarch_avec_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); + HotplugHandlerClass *hc =3D HOTPLUG_HANDLER_CLASS(klass); LoongArchAVECClass *lac =3D LOONGARCH_AVEC_CLASS(klass); =20 dc->unrealize =3D loongarch_avec_unrealize; device_class_set_parent_realize(dc, loongarch_avec_realize, &lac->parent_realize); + hc->plug =3D loongarch_avec_cpu_plug; + hc->unplug =3D loongarch_avec_cpu_unplug; } =20 static const TypeInfo loongarch_avec_info =3D { @@ -130,6 +197,10 @@ static const TypeInfo loongarch_avec_info =3D { .instance_size =3D sizeof(LoongArchAVECState), .instance_init =3D loongarch_avec_init, .class_init =3D loongarch_avec_class_init, + .interfaces =3D (const InterfaceInfo[]) { + { TYPE_HOTPLUG_HANDLER }, + { } + }, }; =20 static void loongarch_avec_register_types(void) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index c8fb31c485..a7043f13dd 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -378,6 +378,10 @@ static void virt_cpu_irq_init(LoongArchVirtMachineStat= e *lvms) &error_abort); hotplug_handler_plug(HOTPLUG_HANDLER(lvms->extioi), DEVICE(cs), &error_abort); + if (lvms->avec) { + hotplug_handler_plug(HOTPLUG_HANDLER(lvms->avec), DEVICE(cs), + &error_abort); + } } } =20 @@ -1086,6 +1090,9 @@ static void virt_cpu_unplug(HotplugHandler *hotplug_d= ev, /* Notify ipi and extioi irqchip to remove interrupt routing to CPU */ hotplug_handler_unplug(HOTPLUG_HANDLER(lvms->ipi), dev, &error_abort); hotplug_handler_unplug(HOTPLUG_HANDLER(lvms->extioi), dev, &error_abor= t); + if (lvms->avec) { + hotplug_handler_unplug(HOTPLUG_HANDLER(lvms->avec), dev, &error_ab= ort); + } =20 /* Notify acpi ged CPU removed */ hotplug_handler_unplug(HOTPLUG_HANDLER(lvms->acpi_ged), dev, &error_ab= ort); @@ -1109,6 +1116,10 @@ static void virt_cpu_plug(HotplugHandler *hotplug_de= v, hotplug_handler_plug(HOTPLUG_HANDLER(lvms->extioi), dev, &error_ab= ort); } =20 + if (lvms->avec) { + hotplug_handler_plug(HOTPLUG_HANDLER(lvms->avec), dev, &error_abor= t); + } + if (lvms->acpi_ged) { hotplug_handler_plug(HOTPLUG_HANDLER(lvms->acpi_ged), dev, &error_abort); --=20 2.41.0