From nobody Sun Sep 28 17:48:16 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1757424754; cv=none; d=zohomail.com; s=zohoarc; b=XSBQTI1BvzVMG69/MjnPOvnMWUP7trsgj3hatfZHlcPYnEqbjTDe3MOFmo+SUPjmp/SFhEMx5Yz15mdaR3c29+ybzxgY+a3o1VK86vldC3XXzb49hSfkAmXS/NVBaA0J1DDuJ6uUwky4OrzLO5PP8cpUlY+sdfO23XSUW8ClXP8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1757424754; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=56kzdKNRG71bPkG/4YMn6pcimop/cdvYexGOM9UznkY=; b=HEe7NfjT/LuYNfl/1YqBx7BgBhHFALBZS8MBlI1GH7pBYxhRIvTD5Ai25CVGWUs2eaapzMLwSWAkY5CyE5Eo1FDddQgbhMwBw6jgNtDfY/fpElx0j4mNqS0x7UoI9xNhzsdtZy1rHTmeaIuyWsWCho/KgKgA1txZiqiXujMWLWo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1757424754767295.3253629221366; Tue, 9 Sep 2025 06:32:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uvyRz-0005d7-OL; Tue, 09 Sep 2025 09:31:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uvyRg-0005ZY-SQ; Tue, 09 Sep 2025 09:31:42 -0400 Received: from [115.124.30.118] (helo=out30-118.freemail.mail.aliyun.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uvyRd-00016m-FL; Tue, 09 Sep 2025 09:31:40 -0400 Received: from localhost.localdomain(mailfrom:zhiwei_liu@linux.alibaba.com fp:SMTPD_---0Wne8Vdt_1757424372 cluster:ay36) by smtp.aliyun-inc.com; Tue, 09 Sep 2025 21:26:14 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1757424688; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=56kzdKNRG71bPkG/4YMn6pcimop/cdvYexGOM9UznkY=; b=gOWbEktRr6Vm/w7/0xXxSAT4sAiZDLW8fZeD0J/LaAI90uBeSb/Cs3HKuuP5eabY8d5jGOQSCyJHQ/bVA9jRJ/4s+r2V97+pyKcplmmvf6zN0cMYne33MY2XamBs2qhAkuhCW049UO062Gjdx4TOWYACcQo/U7jfe12jFq+9eDs= From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, Huang Tao , TANG Tiancheng Subject: [RFC PATCH 1/5] target/riscv: Add basic definitions and CSRs for SMMPT Date: Tue, 9 Sep 2025 21:25:29 +0800 Message-Id: <20250909132533.32205-2-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20250909132533.32205-1-zhiwei_liu@linux.alibaba.com> References: <20250909132533.32205-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.124.30.118 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=115.124.30.118; envelope-from=zhiwei_liu@linux.alibaba.com; helo=out30-118.freemail.mail.aliyun.com X-Spam_score_int: -166 X-Spam_score: -16.7 X-Spam_bar: ---------------- X-Spam_report: (-16.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.alibaba.com) X-ZM-MESSAGEID: 1757424755317116600 Content-Type: text/plain; charset="utf-8" This patch lays the groundwork for the SMMPT (Supervisor Domains Access Protection) extension by introducing its fundamental components. It adds: - New CPU configuration flags, `ext_smmpt` and `ext_smsdid`, to enable the extension. - Bit-field definitions for the `mmpt` CSR in `cpu_bits.h`. - The `mmpt` and `msdcfg` CSR numbers and their read/write handlers in `csr.c`. - New fields in `CPUArchState` to store the state of these new CSRs. - A new translation failure reason `TRANSLATE_MPT_FAIL`. This provides the necessary infrastructure for the core MPT logic and MMU integration that will follow. Co-authored-by: Huang Tao Co-authored-by: TANG Tiancheng Signed-off-by: LIU Zhiwei --- target/riscv/cpu.h | 9 +++- target/riscv/cpu_bits.h | 27 ++++++++++ target/riscv/cpu_cfg_fields.h.inc | 2 + target/riscv/csr.c | 83 +++++++++++++++++++++++++++++++ 4 files changed, 120 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 4a862da615..fa7b804cb3 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -130,7 +130,8 @@ enum { TRANSLATE_SUCCESS, TRANSLATE_FAIL, TRANSLATE_PMP_FAIL, - TRANSLATE_G_STAGE_FAIL + TRANSLATE_G_STAGE_FAIL, + TRANSLATE_MPT_FAIL }; =20 /* Extension context status */ @@ -180,6 +181,7 @@ extern RISCVCPUImpliedExtsRule *riscv_multi_ext_implied= _rules[]; #if !defined(CONFIG_USER_ONLY) #include "pmp.h" #include "debug.h" +#include "riscv_smmpt.h" #endif =20 #define RV_VLEN_MAX 1024 @@ -486,6 +488,11 @@ struct CPUArchState { uint64_t hstateen[SMSTATEEN_MAX_COUNT]; uint64_t sstateen[SMSTATEEN_MAX_COUNT]; uint64_t henvcfg; + /* Smsdid */ + uint32_t mptmode; + uint32_t sdid; + uint64_t mptppn; + uint32_t msdcfg; #endif =20 /* Fields from here on are preserved across CPU reset. */ diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index b62dd82fe7..c6a34863d1 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -1164,4 +1164,31 @@ typedef enum CTRType { #define MCONTEXT64 0x0000000000001FFFULL #define MCONTEXT32_HCONTEXT 0x0000007F #define MCONTEXT64_HCONTEXT 0x0000000000003FFFULL + +/* Smsdid */ +#define CSR_MMPT 0xbc0 +#define CSR_MSDCFG 0xbd1 + +#define MMPT_MODE_MASK_32 0xC0000000 +#define MMPT_SDID_MASK_32 0x3F000000 +#define MMPT_PPN_MASK_32 0x003FFFFF + +#define MMPT_MODE_SHIFT_32 30 +#define MMPT_SDID_SHIFT_32 24 + +#define MMPT_MODE_MASK_64 0xF000000000000000ULL +#define MMPT_SDID_MASK_64 0x0FC0000000000000ULL +#define MMPT_PPN_MASK_64 0x000FFFFFFFFFFFFFULL + +#define MPTE_L3_VALID 0x0000100000000000ULL +#define MPTE_L3_RESERVED 0xFFFFE00000000000ULL + +#define MPTE_L2_RESERVED_64 0xFFFF800000000000ULL +#define MPTE_L2_RESERVED_32 0xFE000000 + +#define MPTE_L1_RESERVED_64 0xFFFFFFFF00000000ULL +#define MPTE_L1_RESERVED_32 0xFFFF0000 + +#define MMPT_MODE_SHIFT_64 60 +#define MMPT_SDID_SHIFT_64 54 #endif diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_field= s.h.inc index e2d116f0df..8c8a4ac236 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -60,6 +60,8 @@ BOOL_FIELD(ext_svpbmt) BOOL_FIELD(ext_svrsw60t59b) BOOL_FIELD(ext_svvptc) BOOL_FIELD(ext_svukte) +BOOL_FIELD(ext_smmpt) +BOOL_FIELD(ext_smsdid) BOOL_FIELD(ext_zdinx) BOOL_FIELD(ext_zaamo) BOOL_FIELD(ext_zacas) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 8842e07a73..77bc596ed3 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -793,6 +793,15 @@ static RISCVException rnmi(CPURISCVState *env, int csr= no) =20 return RISCV_EXCP_ILLEGAL_INST; } + +static RISCVException smsdid(CPURISCVState *env, int csrno) +{ + if (riscv_cpu_cfg(env)->ext_smsdid) { + return RISCV_EXCP_NONE; + } + + return RISCV_EXCP_ILLEGAL_INST; +} #endif =20 static RISCVException seed(CPURISCVState *env, int csrno) @@ -5470,6 +5479,77 @@ static RISCVException write_mnstatus(CPURISCVState *= env, int csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException read_mmpt(CPURISCVState *env, int csrno, + target_ulong *val) +{ + if (riscv_cpu_xlen(env) =3D=3D 32) { + uint32_t value =3D 0; + value |=3D env->mptmode << MMPT_MODE_SHIFT_32; + value |=3D (env->sdid << MMPT_SDID_SHIFT_32) & MMPT_SDID_MASK_32; + value |=3D env->mptppn & MMPT_PPN_MASK_32; + *val =3D value; + } else if (riscv_cpu_xlen(env) =3D=3D 64) { + uint64_t value_64 =3D 0; + uint32_t mode_value =3D env->mptmode; + /* mpt_mode_t convert to mmpt.mode value */ + if (mode_value) { + mode_value -=3D SMMTT43 - SMMTT34; + } + value_64 |=3D (uint64_t)mode_value << MMPT_MODE_SHIFT_64; + value_64 |=3D ((uint64_t)env->sdid << MMPT_SDID_SHIFT_64) + & MMPT_SDID_MASK_64; + value_64 |=3D (uint64_t)env->mptppn & MMPT_PPN_MASK_64; + *val =3D value_64; + } else { + return RISCV_EXCP_ILLEGAL_INST; + } + return RISCV_EXCP_NONE; +} + +static RISCVException write_mmpt(CPURISCVState *env, int csrno, + target_ulong val, uintptr_t ra) +{ + /* Fixme: if mode is bare, the remaining fields in mmpt must be zero */ + if (riscv_cpu_xlen(env) =3D=3D 32) { + /* Only write the legal value */ + uint32_t mode_value =3D (val & MMPT_MODE_MASK_32) >> MMPT_MODE_SHI= FT_32; + if (mode_value <=3D SMMTT34) { + env->mptmode =3D mode_value; + } + env->sdid =3D (val & MMPT_SDID_MASK_32) >> MMPT_SDID_SHIFT_32; + env->mptppn =3D val & MMPT_PPN_MASK_32; + } else if (riscv_cpu_xlen(env) =3D=3D 64) { + uint32_t mode_value =3D (val & MMPT_MODE_MASK_64) >> MMPT_MODE_SHI= FT_64; + /* check legal value */ + if (mode_value < SMMTTMAX) { + /* convert to mpt_mode_t */ + if (mode_value) { + mode_value +=3D SMMTT43 - SMMTT34; + } + env->mptmode =3D mode_value; + } + env->sdid =3D (val & MMPT_SDID_MASK_64) >> MMPT_SDID_SHIFT_64; + env->mptppn =3D val & MMPT_PPN_MASK_64; + } else { + return RISCV_EXCP_ILLEGAL_INST; + } + return RISCV_EXCP_NONE; +} + +static RISCVException read_msdcfg(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->msdcfg; + return RISCV_EXCP_NONE; +} + +static RISCVException write_msdcfg(CPURISCVState *env, int csrno, + target_ulong val, uintptr_t ra) +{ + env->msdcfg =3D val; + return RISCV_EXCP_NONE; +} + #endif =20 /* Crypto Extension */ @@ -6666,6 +6746,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { write_mhpmcounterh }, [CSR_SCOUNTOVF] =3D { "scountovf", sscofpmf, read_scountovf, .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + /* Supervisor Domain Identifier and Protection Registers */ + [CSR_MMPT] =3D { "mmpt", smsdid, read_mmpt, write_mmpt }, + [CSR_MSDCFG] =3D { "msdcfg", smsdid, read_msdcfg, write_msdcfg }, =20 #endif /* !CONFIG_USER_ONLY */ }; --=20 2.25.1