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Tue, 09 Sep 2025 15:11:31 -0700 (PDT) Date: Tue, 09 Sep 2025 22:11:01 +0000 In-Reply-To: <20250909-pcie-root-upstream-v1-0-d85883b2688d@google.com> Mime-Version: 1.0 References: <20250909-pcie-root-upstream-v1-0-d85883b2688d@google.com> X-Mailer: b4 0.14.2 Message-ID: <20250909-pcie-root-upstream-v1-6-d85883b2688d@google.com> Subject: [PATCH 6/7] hw/pci-host: rework Nuvoton PCIe windowing and memory regions From: Yubin Zou To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Tyrone Ting , Hao Wu , qemu-arm@nongnu.org, Peter Maydell , Yubin Zou , Titus Rwantare Content-Type: text/plain; charset="utf-8" Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::549; envelope-from=3E6bAaAYKCq4miPWbnUccUZS.QcaeSai-RSjSZbcbUbi.cfU@flex--yubinz.bounces.google.com; helo=mail-pg1-x549.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 09 Sep 2025 18:12:49 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1757456193336116600 Content-Transfer-Encoding: quoted-printable From: Titus Rwantare This switches to a using a fully sized PCI memory region that's separate from system memory. Accesses to this PCI memory region are gated by the AXI to PCIe windows whose size and offsets are validated. - PCIe config space is not necessarily aliased with PCIe mmio space. Ignore translation addresses for config space windows. - Make window configuration register writes order independent. Tested with pci-testdev. Signed-off-by: Titus Rwantare --- hw/arm/npcm8xx.c | 1 - hw/pci-host/npcm_pcierc.c | 156 ++++++++++++++++++++++++++--------= ---- include/hw/pci-host/npcm_pcierc.h | 9 ++- 3 files changed, 115 insertions(+), 51 deletions(-) diff --git a/hw/arm/npcm8xx.c b/hw/arm/npcm8xx.c index f7a5ae2d121ffec99c519b484503e71dc8a43695..504874c99e7d12afa9226878623= 9ca946e8e2129 100644 --- a/hw/arm/npcm8xx.c +++ b/hw/arm/npcm8xx.c @@ -773,7 +773,6 @@ static void npcm8xx_realize(DeviceState *dev, Error **e= rrp) /* PCIe RC */ sysbus_realize(SYS_BUS_DEVICE(&s->pcierc), &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcierc), 0, NPCM8XX_PCIERC_BA); - sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcierc), 1, NPCM8XX_PCIE_ROOT_BA); sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcierc), 0, npcm8xx_irq(s, NPCM8XX_PCIE_RC_IRQ)); =20 diff --git a/hw/pci-host/npcm_pcierc.c b/hw/pci-host/npcm_pcierc.c index 0af76d1067a78bdbb169af3e3d5c4a2514cd0ff5..3aab7d401a7be8c1b14a476ed93= 4f521b8dfdaa7 100644 --- a/hw/pci-host/npcm_pcierc.c +++ b/hw/pci-host/npcm_pcierc.c @@ -17,63 +17,123 @@ #include "qom/object.h" #include "trace.h" =20 + +#define NPCM_SAL BIT(0) +#define NPCM_SAH BIT(1) +#define NPCM_TAL BIT(2) +#define NPCM_TAH BIT(3) +#define NPCM_PARAMS BIT(4) +#define NPCM_BITFIELDS_ALL 0x1f + + +static bool npcm_pcierc_valid_window_addr(hwaddr addr, uint32_t size) +{ + if ((addr + size) > NPCM_PCIE_HOLE_END) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: window mapping @0x%lx, size: %d is invalid.\n", + __func__, addr, size); + return false; + } else if (addr < NPCM_PCIE_HOLE) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: window mapping @0x%lx, is invalid.\n", + __func__, addr); + return false; + } else { + return true; + } +}; + +static bool npcm_pcierc_valid_window_size(hwaddr src, hwaddr dst, uint32_t= size) +{ + if (size > 2 * GiB || size < 4 * KiB) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid PCI window size %d bytes\n", + __func__, size); + return false; + } + + return true; +} + /* Map enabled windows to a memory subregion */ static void npcm_pcierc_map_enabled(NPCMPCIERCState *s, NPCMPCIEWindow *w) { MemoryRegion *system =3D get_system_memory(); uint32_t size =3D NPCM_PCIERC_SAL_SIZE(w->sal); - hwaddr bar =3D ((uint64_t)w->sah) << 32 | (w->sal & 0xFFFFF000); + hwaddr src_ba =3D ((uint64_t)w->sah) << 32 | (w->sal & 0xFFFFF000); + hwaddr dest_ba =3D ((uint64_t)w->tah) << 32 | w->tal; char name[26]; =20 - /* check if window is enabled */ - if (!(w->sal & NPCM_PCIERC_SAL_EN)) { + if (!(w->sal & NPCM_PCIERC_SAL_EN) || /* ignore disabled windows */ + !npcm_pcierc_valid_window_size(src_ba, dest_ba, size) || + memory_region_is_mapped(&w->mem) /* ignore existing windows */) { return; } =20 - if (size > 2 * GiB || size < 4 * KiB) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: Invalid PCI window size %d bytes\n", - __func__, size); + /* bitfield for all 5 registers required to create a PCIe window */ + if (w->set_fields !=3D NPCM_BITFIELDS_ALL) { return; } + w->set_fields =3D 0; =20 + /* + * This implementation of the Nuvoton root complex uses memory region + * aliasing to emulate the behaviour of the windowing system on hardwa= re. + * AXI to PCIe windows in QEMU are system_memory subregions aliased to= PCI + * memory at the respective source and translation addresses + * PCIe to AXI windows are done as PCI memory subregions aliased to sy= stem + * memory. PCIe to AXI windows have no address restrictions. + */ if (w->type =3D=3D AXI2PCIE) { + if (!npcm_pcierc_valid_window_addr(src_ba, size)) { + return; + }; snprintf(name, sizeof(name), "npcm-axi2pcie-window-%d", w->id); + if (w->params & + (NPCM_PCIERC_TRSF_PARAM_CONFIG | NPCM_PCIERC_TRSL_ID_CONFIG)) { + memory_region_init_alias(&w->mem, OBJECT(s), name, + &s->rp_config, 0, size); + } else { + memory_region_init_alias(&w->mem, OBJECT(s), name, + &s->pcie_memory, dest_ba, size); + } + memory_region_add_subregion(system, src_ba, &w->mem); } else if (w->type =3D=3D PCIE2AXI) { snprintf(name, sizeof(name), "npcm-pcie2axi-window-%d", w->id); + memory_region_init_alias(&w->mem, OBJECT(s), name, + system, src_ba, size); + memory_region_add_subregion(&s->pcie_memory, dest_ba, &w->mem); } else { qemu_log_mask(LOG_GUEST_ERROR, "%s: unable to map uninitialized PCIe window", __func__); return; } - - /* TODO: set subregion to target translation address */ - /* add subregion starting at the window source address */ - if (!memory_region_is_mapped(&w->mem)) { - memory_region_init(&w->mem, OBJECT(s), name, size); - memory_region_add_subregion(system, bar, &w->mem); - } } =20 /* unmap windows marked as disabled */ -static void npcm_pcierc_unmap_disabled(NPCMPCIEWindow *w) +static void npcm_pcierc_unmap_disabled(NPCMPCIERCState *s, NPCMPCIEWindow = *w) { MemoryRegion *system =3D get_system_memory(); + /* Bit 0 in the Source address enables the window */ if (memory_region_is_mapped(&w->mem) && !(w->sal & NPCM_PCIERC_SAL_EN)= ) { - memory_region_del_subregion(system, &w->mem); + if (w->type =3D=3D AXI2PCIE) { + memory_region_del_subregion(system, &w->mem); + } else { + memory_region_del_subregion(&s->pcie_memory, &w->mem); + } } } =20 static void npcm_pcie_update_window_maps(NPCMPCIERCState *s) { for (int i =3D 0; i < NPCM_PCIERC_NUM_PA_WINDOWS; i++) { - npcm_pcierc_unmap_disabled(&s->pcie2axi[i]); + npcm_pcierc_unmap_disabled(s, &s->pcie2axi[i]); } =20 for (int i =3D 0; i < NPCM_PCIERC_NUM_AP_WINDOWS; i++) { - npcm_pcierc_unmap_disabled(&s->axi2pcie[i]); + npcm_pcierc_unmap_disabled(s, &s->axi2pcie[i]); } =20 for (int i =3D 0; i < NPCM_PCIERC_NUM_AP_WINDOWS; i++) { @@ -177,22 +237,27 @@ static void npcm_pcierc_write_window(NPCMPCIERCState = *s, hwaddr addr, switch (offset) { case NPCM_PCIERC_SAL_OFFSET: window->sal =3D data; + window->set_fields |=3D NPCM_SAL; break; =20 case NPCM_PCIERC_SAH_OFFSET: window->sah =3D data; + window->set_fields |=3D NPCM_SAH; break; =20 case NPCM_PCIERC_TAL_OFFSET: window->tal =3D data; + window->set_fields |=3D NPCM_TAL; break; =20 case NPCM_PCIERC_TAH_OFFSET: window->tah =3D data; + window->set_fields |=3D NPCM_TAH; break; =20 case NPCM_PCIERC_PARAM_OFFSET: window->params =3D data; + window->set_fields |=3D NPCM_PARAMS; break; =20 default: @@ -305,7 +370,7 @@ static uint64_t npcm_pcie_host_config_read(void *opaque= , hwaddr addr, PCIDevice *pcid =3D pci_find_device(pcih->bus, bus, devfn); =20 if (pcid) { - return pci_host_config_read_common(pcid, addr, + return pci_host_config_read_common(pcid, (addr & 0x7FF), pci_config_size(pcid), size); } @@ -323,7 +388,7 @@ static void npcm_pcie_host_config_write(void *opaque, h= waddr addr, PCIDevice *pcid =3D pci_find_device(pcih->bus, bus, devfn); =20 if (pcid) { - pci_host_config_write_common(pcid, addr, + pci_host_config_write_common(pcid, (addr & 0x7FF), pci_config_size(pcid), data, size); @@ -413,40 +478,43 @@ static void npcm_pcie_set_irq(void *opaque, int irq_n= um, int level) static void npcm_pcierc_realize(DeviceState *dev, Error **errp) { NPCMPCIERCState *s =3D NPCM_PCIERC(dev); + PCIHostState *phs =3D PCI_HOST_BRIDGE(dev); SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); - PCIHostState *pci =3D PCI_HOST_BRIDGE(dev); PCIDevice *root =3D pci_new(PCI_DEVFN(0, 0), TYPE_NPCM_PCIE_ROOT_PORT); =20 - memory_region_init_io(&s->mmio, OBJECT(s), &npcm_pcierc_cfg_ops, - s, TYPE_NPCM_PCIERC, 4 * KiB); - sysbus_init_mmio(sbd, &s->mmio); - sysbus_init_irq(sbd, &s->irq); + /* init the underlying memory region for all PCI address space */ + memory_region_init(&s->pcie_memory, OBJECT(s), "npcm-pcie-mem", UINT64= _MAX); =20 - /* IO memory region is needed to create a PCI bus, but is unused on AR= M */ + /* I/O memory region is needed to create a PCI bus, but is unused on A= RM */ memory_region_init(&s->pcie_io, OBJECT(s), "npcm-pcie-io", 16); =20 - /* - * pcie_root is a 128 MiB memory region in the BMC physical address sp= ace - * in which all PCIe windows must have their programmable source or - * destination address - */ - memory_region_init_io(&s->pcie_root, OBJECT(s), &npcm_pcie_cfg_space_o= ps, - s, "npcm-pcie-config", 128 * MiB); - sysbus_init_mmio(sbd, &s->pcie_root); - - pci->bus =3D pci_register_root_bus(dev, "pcie", + phs->bus =3D pci_register_root_bus(dev, "pcie", npcm_pcie_set_irq, pci_swizzle_map_irq_fn, - s, &s->pcie_root, &s->pcie_io, + s, &s->pcie_memory, &s->pcie_io, 0, 4, TYPE_PCIE_BUS); =20 - address_space_init(&s->pcie_space, &s->pcie_root, "pcie-address-space"= ); - pci_realize_and_unref(root, pci->bus, &error_fatal); - pci_setup_iommu(pci->bus, &npcm_pcierc_iommu_ops, s); + address_space_init(&s->pcie_space, &s->pcie_memory, "pcie-address-spac= e"); + pci_setup_iommu(phs->bus, &npcm_pcierc_iommu_ops, s); + /* init region for root complex registers (not config space) */ + memory_region_init_io(&s->rc_regs, OBJECT(s), &npcm_pcierc_cfg_ops, + s, TYPE_NPCM_PCIERC, 4 * KiB); + sysbus_init_mmio(sbd, &s->rc_regs); + sysbus_init_irq(sbd, &s->irq); + + /* create and add region for the root port in config space */ + memory_region_init_io(&s->rp_config, OBJECT(s), + &npcm_pcie_cfg_space_ops, s, "npcm-pcie-config", + 4 * KiB); =20 + /* realize the root port */ + pci_realize_and_unref(root, phs->bus, &error_fatal); + /* enable MSI (non-X) in root port config space */ msi_nonbroken =3D true; msi_init(root, NPCM_PCIERC_MSI_OFFSET, NPCM_PCIERC_MSI_NR, true, true, errp); + + npcm_pcierc_reset_pcie_windows(s); } =20 static void npcm_pcie_root_port_realize(DeviceState *dev, Error **errp) @@ -461,13 +529,6 @@ static void npcm_pcie_root_port_realize(DeviceState *d= ev, Error **errp) } } =20 -static void npcm_pcierc_instance_init(Object *obj) -{ - NPCMPCIERCState *s =3D NPCM_PCIERC(obj); - - npcm_pcierc_reset_pcie_windows(s); -} - static void npcm_pcierc_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -507,7 +568,6 @@ static const TypeInfo npcm_pcierc_type_info =3D { .name =3D TYPE_NPCM_PCIERC, .parent =3D TYPE_PCIE_HOST_BRIDGE, .instance_size =3D sizeof(NPCMPCIERCState), - .instance_init =3D npcm_pcierc_instance_init, .class_init =3D npcm_pcierc_class_init, }; =20 diff --git a/include/hw/pci-host/npcm_pcierc.h b/include/hw/pci-host/npcm_p= cierc.h index 7d18177510f60d49f7fae7908dd1e3bfbe9ae12b..a986e7666abadd8c0bb97ac5e10= 853339f0fe815 100644 --- a/include/hw/pci-host/npcm_pcierc.h +++ b/include/hw/pci-host/npcm_pcierc.h @@ -96,6 +96,9 @@ #define TYPE_NPCM_PCIERC "npcm-pcie-root-complex" OBJECT_DECLARE_SIMPLE_TYPE(NPCMPCIERCState, NPCM_PCIERC) =20 +#define NPCM_PCIE_HOLE (0xe8000000) +#define NPCM_PCIE_HOLE_END (0xe8000000 + (128 * MiB)) + typedef enum { AXI2PCIE =3D 1, PCIE2AXI @@ -111,6 +114,7 @@ typedef struct NPCMPCIEWindow { =20 MemoryRegion mem; /* QEMU memory subregion per window */ NPCMPCIEWindowType type; /* translation direction */ + uint8_t set_fields; uint8_t id; } NPCMPCIEWindow; =20 @@ -127,7 +131,7 @@ struct NPCMPCIERCState { qemu_irq irq; =20 /* PCIe RC registers */ - MemoryRegion mmio; + MemoryRegion rc_regs; uint32_t rccfgnum; uint32_t rcinten; uint32_t rcintstat; @@ -137,8 +141,9 @@ struct NPCMPCIERCState { =20 /* Address translation state */ AddressSpace pcie_space; - MemoryRegion pcie_root; + MemoryRegion pcie_memory; MemoryRegion pcie_io; /* unused - but required for IO space PCI */ + MemoryRegion rp_config; NPCMPCIERootPort port; /* PCIe to AXI Windows */ NPCMPCIEWindow pcie2axi[NPCM_PCIERC_NUM_PA_WINDOWS]; --=20 2.51.0.384.g4c02a37b29-goog