From nobody Wed Sep 10 01:55:30 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1757361857; cv=none; d=zohomail.com; s=zohoarc; b=icMNBbiEEI/DBGn/yXaxD55PusMN8A0drQpytMiXiPpwGuLemEFaal1tsJ97afkDgKQucLvAAhkR54nkmq/wVpV4+IFFqGCVOMdoFgUd+Kzmyiqwn3PIvQu/OafzogRJypF/9ZnAuU3wfacZkb7sYEM1fsSEgrbcC0zCUsAcupI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1757361857; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=RQtxonTOjRwPC9RPCw19uNdTlo87v2Np4J9qhVBWPyY=; b=R28G0krk/GAILeA7q2SqxONLqv1uTg3FFfd4ZI9RTpNMvcmIrZiIeSZE2/O+M9steGMGtUPAokxw/SK2/KtGCAtUrRgn9hK1dnbcb5WEn/ho/GdZ4FclwFH1ndHc6B9idnbezFIv7RHic1FWY2SMeUWkVFYA+oqZ9o0MBGRzMGY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1757361857536166.5718847775422; Mon, 8 Sep 2025 13:04:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uvi3M-0001lh-Qg; Mon, 08 Sep 2025 16:01:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uvi3K-0001l8-EB; Mon, 08 Sep 2025 16:01:26 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uvi3G-0006qq-SD; Mon, 08 Sep 2025 16:01:26 -0400 Received: from pps.filterd (m0353729.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 588Fqqxj018799; Mon, 8 Sep 2025 20:01:18 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 490cmwkn4h-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 20:01:18 +0000 (GMT) Received: from m0353729.ppops.net (m0353729.ppops.net [127.0.0.1]) by pps.reinject (8.18.1.12/8.18.0.8) with ESMTP id 588Jsbmf024589; Mon, 8 Sep 2025 20:01:17 GMT Received: from ppma23.wdc07v.mail.ibm.com (5d.69.3da9.ip4.static.sl-reverse.com [169.61.105.93]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 490cmwkn4g-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 20:01:17 +0000 (GMT) Received: from pps.filterd (ppma23.wdc07v.mail.ibm.com [127.0.0.1]) by ppma23.wdc07v.mail.ibm.com (8.18.1.2/8.18.1.2) with ESMTP id 588H5fnY010594; Mon, 8 Sep 2025 20:01:16 GMT Received: from smtprelay05.dal12v.mail.ibm.com ([172.16.1.7]) by ppma23.wdc07v.mail.ibm.com (PPS) with ESMTPS id 4910smqnfa-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 20:01:16 +0000 Received: from smtpav02.wdc07v.mail.ibm.com (smtpav02.wdc07v.mail.ibm.com [10.39.53.229]) by smtprelay05.dal12v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 588K1EGv23134866 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 8 Sep 2025 20:01:15 GMT Received: from smtpav02.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 922DA5805D; Mon, 8 Sep 2025 20:01:14 +0000 (GMT) Received: from smtpav02.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C44935805B; Mon, 8 Sep 2025 20:01:13 +0000 (GMT) Received: from mglenn-KVM.. (unknown [9.10.239.198]) by smtpav02.wdc07v.mail.ibm.com (Postfix) with ESMTP; Mon, 8 Sep 2025 20:01:13 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=RQtxonTOjRwPC9RPC w19uNdTlo87v2Np4J9qhVBWPyY=; b=lYs4zV/u1Nf2l4oe1imPa1UQSVVXjTSz2 mhJBayWAlCZNltyYdcUIHXsXJT2+qK27tI9VPk3qhsOohmUqO8VWJBZAiYy3fsnm K/XOJ5KTXSpnxEz9hdcFPEynyIalZacf7UKlpgbpSNqCefth1ZwRo/0xmurgeyqB Wwijm2uCbKoXHX+ZaECAC2plty9CtDeanAQZCMT3iWN3cgFCEu/UUd5XuhQDHic2 dfxGTE4E/Z/WP4mNadT1NPecfuEgjALbMYHffkEnznlxNogpjbTIwHPT4nMFN2xE Cggtj0rXenCA1E3xBmP1DA/elarqmLnEd/k6k8Z4wwsB6tA51TZhA== From: Glenn Miles To: qemu-devel@nongnu.org Cc: Glenn Miles , qemu-ppc@nongnu.org, clg@redhat.com, npiggin@gmail.com, harshpb@linux.ibm.com, thuth@redhat.com, rathc@linux.ibm.com, richard.henderson@linaro.org Subject: [PATCH v3 1/9] target/ppc: IBM PPE42 general regs and flags Date: Mon, 8 Sep 2025 15:00:11 -0500 Message-ID: <20250908200028.115789-2-milesg@linux.ibm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250908200028.115789-1-milesg@linux.ibm.com> References: <20250908200028.115789-1-milesg@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: RpSFy1WWXHUeupbhXw8y5V345ZhGK2GA X-Proofpoint-ORIG-GUID: ehoxSyENBwdVF9thY2pIZhvuj3zLeyf_ X-Authority-Analysis: v=2.4 cv=J52q7BnS c=1 sm=1 tr=0 ts=68bf360e cx=c_pps a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17 a=yJojWOMRYYMA:10 a=VnNF1IyMAAAA:8 a=KjnWNliXgB7EaSLBB8sA:9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDAyNSBTYWx0ZWRfXxi0ECsInUwVu Yxn1EFcPw6FhDr9uML3SBtYBwfvphMdZvtzCkvBypUcj4FMky64WjiyfI6TNcn38s4O3PGTCBMt 5Nq3lxqmUkNqMir40icOD4Rl/O+9tPBvhfXyDRSU9NYPlovKHp9ID1I1LGytWUuhQWXbdHNKEGb iJ4s+uAAg+TcxsRskcA/XhIxmL3U7FJ8oK/KVVsMcIxYftXqG+LeaCwHodwVCc+T5wwv2/c2+mY gtNLuNQsUvffAl49jjFyATKura8RdnvBsbAcvUJTiX/IihjdrD3dw6S92YyDup8ih/00QgTgwjn ab3x47VeoC5yG+jOxf5S9WVI5LZ5pUQ7sQ6YIH3WYTd92HLyTL5P6Hah9kXF3AntfADubHTaNDg oxkCia+4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-08_06,2025-09-08_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 suspectscore=0 spamscore=0 phishscore=0 bulkscore=0 adultscore=0 malwarescore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060025 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=milesg@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1757361859789124100 Content-Type: text/plain; charset="utf-8" Introduces general IBM PPE42 processor register definitions and flags. Signed-off-by: Glenn Miles --- Changes from v2: - Split general registers and flags from v2 patch 1 target/ppc/cpu-models.h | 4 ++++ target/ppc/cpu.h | 49 ++++++++++++++++++++++++++++++++++++++++- 2 files changed, 52 insertions(+), 1 deletion(-) diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h index 72ad31ba50..c6cd27f390 100644 --- a/target/ppc/cpu-models.h +++ b/target/ppc/cpu-models.h @@ -69,6 +69,10 @@ enum { /* Xilinx cores */ CPU_POWERPC_X2VP4 =3D 0x20010820, CPU_POWERPC_X2VP20 =3D 0x20010860, + /* IBM PPE42 Family */ + CPU_POWERPC_PPE42 =3D 0x42000000, + CPU_POWERPC_PPE42X =3D 0x42100000, + CPU_POWERPC_PPE42XM =3D 0x42200000, /* PowerPC 440 family */ /* Generic PowerPC 440 */ #define CPU_POWERPC_440 CPU_POWERPC_440GXf diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 6b90543811..81a0e16641 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -282,6 +282,8 @@ typedef enum powerpc_input_t { PPC_FLAGS_INPUT_POWER9, /* Freescale RCPU bus */ PPC_FLAGS_INPUT_RCPU, + /* PPE42 bus */ + PPC_FLAGS_INPUT_PPE42, } powerpc_input_t; =20 #define PPC_INPUT(env) ((env)->bus_model) @@ -433,39 +435,64 @@ typedef enum { #define MSR_TM PPC_BIT_NR(31) /* Transactional Memory Available (Book3s)= */ #define MSR_CM PPC_BIT_NR(32) /* Computation mode for BookE hfla= gs */ #define MSR_ICM PPC_BIT_NR(33) /* Interrupt computation mode for BookE = */ +#define MSR_SEM0 PPC_BIT_NR(33) /* SIB Error Mask Bit 0 (PPE42) = */ +#define MSR_SEM1 PPC_BIT_NR(34) /* SIB Error Mask Bit 1 (PPE42) = */ +#define MSR_SEM2 PPC_BIT_NR(35) /* SIB Error Mask Bit 2 (PPE42) = */ #define MSR_GS PPC_BIT_NR(35) /* guest state for BookE = */ +#define MSR_SEM3 PPC_BIT_NR(36) /* SIB Error Mask Bit 3 (PPE42) = */ +#define MSR_SEM4 PPC_BIT_NR(37) /* SIB Error Mask Bit 4 (PPE42) = */ #define MSR_UCLE PPC_BIT_NR(37) /* User-mode cache lock enable for BookE = */ #define MSR_VR PPC_BIT_NR(38) /* altivec available x hfla= gs */ #define MSR_SPE PPC_BIT_NR(38) /* SPE enable for BookE x hfla= gs */ +#define MSR_SEM5 PPC_BIT_NR(38) /* SIB Error Mask Bit 5 (PPE42) = */ +#define MSR_SEM6 PPC_BIT_NR(39) /* SIB Error Mask Bit 6 (PPE42) = */ #define MSR_VSX PPC_BIT_NR(40) /* Vector Scalar Extension (>=3D 2.06)x hf= lags */ +#define MSR_IS0 PPC_BIT_NR(40) /* Instance Specific Bit 0 (PPE42) = */ #define MSR_S PPC_BIT_NR(41) /* Secure state = */ +#define MSR_SIBRC0 PPC_BIT_NR(41) /* Last SIB return code Bit 0 (PPE42) = */ +#define MSR_SIBRC1 PPC_BIT_NR(42) /* Last SIB return code Bit 1 (PPE42) = */ +#define MSR_SIBRC2 PPC_BIT_NR(43) /* Last SIB return code Bit 2 (PPE42) = */ +#define MSR_LP PPC_BIT_NR(44) /* Low Priority (PPE42) = */ #define MSR_KEY PPC_BIT_NR(44) /* key bit on 603e = */ #define MSR_POW PPC_BIT_NR(45) /* Power management = */ #define MSR_WE PPC_BIT_NR(45) /* Wait State Enable on 405 = */ +#define MSR_IS1 PPC_BIT_NR(46) /* Instance Specific Bit 1 (PPE42) = */ #define MSR_TGPR PPC_BIT_NR(46) /* TGPR usage on 602/603 x = */ #define MSR_CE PPC_BIT_NR(46) /* Critical int. enable on embedded PPC x = */ #define MSR_ILE PPC_BIT_NR(47) /* Interrupt little-endian mode = */ +#define MSR_UIE PPC_BIT_NR(47) /* Unmaskable Interrupt Enable (PPE42) = */ #define MSR_EE PPC_BIT_NR(48) /* External interrupt enable = */ #define MSR_PR PPC_BIT_NR(49) /* Problem state hfla= gs */ #define MSR_FP PPC_BIT_NR(50) /* Floating point available hfla= gs */ #define MSR_ME PPC_BIT_NR(51) /* Machine check interrupt enable = */ #define MSR_FE0 PPC_BIT_NR(52) /* Floating point exception mode 0 = */ +#define MSR_IS2 PPC_BIT_NR(52) /* Instance Specific Bit 2 (PPE42) = */ +#define MSR_IS3 PPC_BIT_NR(53) /* Instance Specific Bit 3 (PPE42) = */ #define MSR_SE PPC_BIT_NR(53) /* Single-step trace enable x hfla= gs */ #define MSR_DWE PPC_BIT_NR(53) /* Debug wait enable on 405 x = */ #define MSR_UBLE PPC_BIT_NR(53) /* User BTB lock enable on e500 x = */ #define MSR_BE PPC_BIT_NR(54) /* Branch trace enable x hfla= gs */ #define MSR_DE PPC_BIT_NR(54) /* Debug int. enable on embedded PPC x = */ #define MSR_FE1 PPC_BIT_NR(55) /* Floating point exception mode 1 = */ +#define MSR_IPE PPC_BIT_NR(55) /* Imprecise Mode Enable (PPE42) = */ #define MSR_AL PPC_BIT_NR(56) /* AL bit on POWER = */ +#define MSR_SIBRCA0 PPC_BIT_NR(56) /* SIB Return Code Accumulator 0 (PPE42= ) */ +#define MSR_SIBRCA1 PPC_BIT_NR(57) /* SIB Return Code Accumulator 1 (PPE42= ) */ #define MSR_EP PPC_BIT_NR(57) /* Exception prefix on 601 = */ #define MSR_IR PPC_BIT_NR(58) /* Instruction relocate = */ #define MSR_IS PPC_BIT_NR(58) /* Instruction address space (BookE) = */ +#define MSR_SIBRCA2 PPC_BIT_NR(58) /* SIB Return Code Accumulator 2 (PPE42= ) */ +#define MSR_SIBRCA3 PPC_BIT_NR(59) /* SIB Return Code Accumulator 3 (PPE42= ) */ #define MSR_DR PPC_BIT_NR(59) /* Data relocate = */ #define MSR_DS PPC_BIT_NR(59) /* Data address space (BookE) = */ #define MSR_PE PPC_BIT_NR(60) /* Protection enable on 403 = */ +#define MSR_SIBRCA4 PPC_BIT_NR(60) /* SIB Return Code Accumulator 4 (PPE42= ) */ +#define MSR_SIBRCA5 PPC_BIT_NR(61) /* SIB Return Code Accumulator 5 (PPE42= ) */ #define MSR_PX PPC_BIT_NR(61) /* Protection exclusive on 403 x = */ #define MSR_PMM PPC_BIT_NR(61) /* Performance monitor mark on POWER x = */ #define MSR_RI PPC_BIT_NR(62) /* Recoverable interrupt 1 = */ +#define MSR_SIBRCA6 PPC_BIT_NR(62) /* SIB Return Code Accumulator 6 (PPE42= ) */ +#define MSR_SIBRCA7 PPC_BIT_NR(63) /* SIB Return Code Accumulator 7 (PPE42= ) */ #define MSR_LE PPC_BIT_NR(63) /* Little-endian mode 1 hfla= gs */ =20 FIELD(MSR, SF, MSR_SF, 1) @@ -517,6 +544,9 @@ FIELD(MSR, PX, MSR_PX, 1) FIELD(MSR, PMM, MSR_PMM, 1) FIELD(MSR, RI, MSR_RI, 1) FIELD(MSR, LE, MSR_LE, 1) +FIELD(MSR, SEM, MSR_SEM6, 7) +FIELD(MSR, SIBRC, MSR_SIBRC2, 3) +FIELD(MSR, SIBRCA, MSR_SIBRCA7, 8) =20 /* * FE0 and FE1 bits are not side-by-side @@ -785,6 +815,8 @@ enum { POWERPC_FLAG_SMT_1LPAR =3D 0x00800000, /* Has BHRB */ POWERPC_FLAG_BHRB =3D 0x01000000, + /* Use PPE42-specific behavior = */ + POWERPC_FLAG_PPE42 =3D 0x02000000, }; =20 /* @@ -1750,9 +1782,12 @@ void ppc_compat_add_property(Object *obj, const char= *name, #define SPR_BOOKE_CSRR0 (0x03A) #define SPR_BOOKE_CSRR1 (0x03B) #define SPR_BOOKE_DEAR (0x03D) +#define SPR_PPE42_EDR (0x03D) #define SPR_IAMR (0x03D) #define SPR_BOOKE_ESR (0x03E) +#define SPR_PPE42_ISR (0x03E) #define SPR_BOOKE_IVPR (0x03F) +#define SPR_PPE42_IVPR (0x03F) #define SPR_MPC_EIE (0x050) #define SPR_MPC_EID (0x051) #define SPR_MPC_NRI (0x052) @@ -1818,6 +1853,7 @@ void ppc_compat_add_property(Object *obj, const char = *name, #define SPR_TBU40 (0x11E) #define SPR_SVR (0x11E) #define SPR_BOOKE_PIR (0x11E) +#define SPR_PPE42_PIR (0x11E) #define SPR_PVR (0x11F) #define SPR_HSPRG0 (0x130) #define SPR_BOOKE_DBSR (0x130) @@ -1827,6 +1863,7 @@ void ppc_compat_add_property(Object *obj, const char = *name, #define SPR_BOOKE_EPCR (0x133) #define SPR_SPURR (0x134) #define SPR_BOOKE_DBCR0 (0x134) +#define SPR_PPE42_DBCR (0x134) #define SPR_IBCR (0x135) #define SPR_PURR (0x135) #define SPR_BOOKE_DBCR1 (0x135) @@ -1844,6 +1881,7 @@ void ppc_compat_add_property(Object *obj, const char = *name, #define SPR_HSRR1 (0x13B) #define SPR_BOOKE_IAC4 (0x13B) #define SPR_BOOKE_DAC1 (0x13C) +#define SPR_PPE42_DACR (0x13C) #define SPR_MMCRH (0x13C) #define SPR_DABR2 (0x13D) #define SPR_BOOKE_DAC2 (0x13D) @@ -1853,12 +1891,14 @@ void ppc_compat_add_property(Object *obj, const cha= r *name, #define SPR_BOOKE_DVC2 (0x13F) #define SPR_LPIDR (0x13F) #define SPR_BOOKE_TSR (0x150) +#define SPR_PPE42_TSR (0x150) #define SPR_HMER (0x150) #define SPR_HMEER (0x151) #define SPR_PCR (0x152) #define SPR_HEIR (0x153) #define SPR_BOOKE_LPIDR (0x152) #define SPR_BOOKE_TCR (0x154) +#define SPR_PPE42_TCR (0x154) #define SPR_BOOKE_TLB0PS (0x158) #define SPR_BOOKE_TLB1PS (0x159) #define SPR_BOOKE_TLB2PS (0x15A) @@ -2528,6 +2568,12 @@ enum { PPC2_MEM_LWSYNC =3D 0x0000000000200000ULL, /* ISA 2.06 BCD assist instructions = */ PPC2_BCDA_ISA206 =3D 0x0000000000400000ULL, + /* PPE42 instructions = */ + PPC2_PPE42 =3D 0x0000000000800000ULL, + /* PPE42X instructions = */ + PPC2_PPE42X =3D 0x0000000001000000ULL, + /* PPE42XM instructions = */ + PPC2_PPE42XM =3D 0x0000000002000000ULL, =20 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX= | \ PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \ @@ -2537,7 +2583,8 @@ enum { PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \ PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \ PPC2_ISA300 | PPC2_ISA310 | PPC2_MEM_LWSYNC | \ - PPC2_BCDA_ISA206) + PPC2_BCDA_ISA206 | PPC2_PPE42 | PPC2_PPE42X | \ + PPC2_PPE42XM) }; =20 /*************************************************************************= ****/ --=20 2.43.0 From nobody Wed Sep 10 01:55:30 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1757361813; cv=none; d=zohomail.com; s=zohoarc; b=ciXs9ctpvyFOCh93XBcFiTyl60y2LLdBbaUGXYVjLbO5MWehtcxjnqZG8lzpcqtQRUDYCssj6E273wfIY1IHPl9/dnbFAhN6N6TdDRWKGsR2D28qDOw/+NkgXYO4sG24eB1/WRcol4E9vjO8Cqy03sQjU8ZqJnY/HoGoOk1CE7c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1757361813; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=JM8JywnivPsWI4gVK1kR+K8RKWYC81ZStz7UTGvkxC4=; b=gnxCX8rojyle4aNZU8ZPG1UmSGD+9y4j2K719fVy+TLSv6wnYO40awPlOrIXkakA4NIZpjHZ6NM7mkJBzv03z7jaIAkm/u7yYJ6KR0GSxZGzvEr6axDjhTObkTMH4cxHpcfEBjKdpghzdHh+9CzzEFoYM0U22rXLSW2OJyxzjIo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1757361813919432.61045889538343; Mon, 8 Sep 2025 13:03:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uvi3U-0001oc-Hc; Mon, 08 Sep 2025 16:01:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uvi3S-0001n6-6S; Mon, 08 Sep 2025 16:01:34 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uvi3L-0006sA-OT; Mon, 08 Sep 2025 16:01:33 -0400 Received: from pps.filterd (m0360072.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 588GUw9u017992; Mon, 8 Sep 2025 20:01:23 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 490uke8wmt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 20:01:22 +0000 (GMT) Received: from m0360072.ppops.net (m0360072.ppops.net [127.0.0.1]) by pps.reinject (8.18.1.12/8.18.0.8) with ESMTP id 588K0DtI012453; Mon, 8 Sep 2025 20:01:22 GMT Received: from ppma21.wdc07v.mail.ibm.com (5b.69.3da9.ip4.static.sl-reverse.com [169.61.105.91]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 490uke8wmq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 20:01:22 +0000 (GMT) Received: from pps.filterd (ppma21.wdc07v.mail.ibm.com [127.0.0.1]) by ppma21.wdc07v.mail.ibm.com (8.18.1.2/8.18.1.2) with ESMTP id 588GfeoF007982; Mon, 8 Sep 2025 20:01:21 GMT Received: from smtprelay04.wdc07v.mail.ibm.com ([172.16.1.71]) by ppma21.wdc07v.mail.ibm.com (PPS) with ESMTPS id 49109pfqrj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 20:01:21 +0000 Received: from smtpav02.wdc07v.mail.ibm.com (smtpav02.wdc07v.mail.ibm.com [10.39.53.229]) by smtprelay04.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 588K1Kg138142584 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 8 Sep 2025 20:01:20 GMT Received: from smtpav02.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2B60D5805B; Mon, 8 Sep 2025 20:01:20 +0000 (GMT) Received: from smtpav02.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5367B58059; Mon, 8 Sep 2025 20:01:19 +0000 (GMT) Received: from mglenn-KVM.. (unknown [9.10.239.198]) by smtpav02.wdc07v.mail.ibm.com (Postfix) with ESMTP; Mon, 8 Sep 2025 20:01:19 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=JM8JywnivPsWI4gVK 1kR+K8RKWYC81ZStz7UTGvkxC4=; b=gdl/Jc6jwTO9fT93ftYw4VwbmSb5Wgw3m Xhc0YklQMGcAhHE8+78IKt8l7w7hGgWkhXvt3QhVovt9eVdSPnyXJ/4u2smWZ+F7 tOxHIugvvT2oaAP9ssRz8lVr+RpC3aqRxGlBxyIA72dKeMW1+lVKnwoaWGtkMM1t 7epWSqDl3+YDQAMVgWd97Da6W8UJW4aL1qBz1RGNuG42zhzjyXAgxmXNNCcDPlOh ZpAYrqRMERvtjodvPy6JmsuBfPGYPGJWpnrOuSg6yZjn5svEVRtVN4ifsoGg4dcj Z7UzUHDrCe4ybFIUIS+nemrLuuyVdrDxYX0BF3Noq6AyUfj0MiD0A== From: Glenn Miles To: qemu-devel@nongnu.org Cc: Glenn Miles , qemu-ppc@nongnu.org, clg@redhat.com, npiggin@gmail.com, harshpb@linux.ibm.com, thuth@redhat.com, rathc@linux.ibm.com, richard.henderson@linaro.org Subject: [PATCH v3 2/9] target/ppc: Add IBM PPE42 family of processors Date: Mon, 8 Sep 2025 15:00:12 -0500 Message-ID: <20250908200028.115789-3-milesg@linux.ibm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250908200028.115789-1-milesg@linux.ibm.com> References: <20250908200028.115789-1-milesg@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDE5NSBTYWx0ZWRfX4/aOVIjfUvET jIkVN9RYirJTgwzo5E0JJEQ3jKabXbTxRQDKpUONBtTSivFvSTZGq92bFzkvNjg2A+RA3HiqoHJ J0sXvMeGLWEyFxvjFweKXPkHO5r033XDNHBVGTaDnkujhRX7ND13KI+yEm4Olta8lzDiR75kDUI wnqVpz13E0YgczSyjbn8KirGRHMZjNymMr3QSdyBcDYJUYYNEazY1xnw1VEdOC6xP2+geEn7Yui UVDyYEwCrCx1UBhHJ6b3X1uQ/z7Xj+998VJqfiUW0GDJUjEGY8qHGbG5y7aWiVlnB0fT627FDPQ aEuBUfGuF7S839gEm1DB0qZcvgs/OJf6+N5dt2919pFbqPj5qYSqkSGdriNz436KE+uSD00FPrC 0diN1p3C X-Proofpoint-ORIG-GUID: sIFqy0q5r4WMf0lVyWHBrqd-3BN86TqM X-Proofpoint-GUID: YBp76Vk_0eDAuz4BTvbwC4Bc8Xz8qWpO X-Authority-Analysis: v=2.4 cv=StCQ6OO0 c=1 sm=1 tr=0 ts=68bf3612 cx=c_pps a=GFwsV6G8L6GxiO2Y/PsHdQ==:117 a=GFwsV6G8L6GxiO2Y/PsHdQ==:17 a=yJojWOMRYYMA:10 a=jRLB2SoPAAAA:8 a=VnNF1IyMAAAA:8 a=CMSrYuGzgbGWQ58TYJUA:9 a=yloqiLrygL2q3s9aD-8D:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-08_06,2025-09-08_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 bulkscore=0 clxscore=1015 adultscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060195 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=milesg@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1757361815739124100 Content-Type: text/plain; charset="utf-8" Adds the IBM PPE42 family of 32-bit processors supporting the PPE42, PPE42X and PPE42XM processor versions. These processors are used as embedded processors in the IBM Power9, Power10 and Power12 processors for various tasks. It is basically a stripped down version of the IBM PowerPC 405 processor, with some added instructions for handling 64-bit loads and stores. For more information on the PPE 42 processor please visit: https://wiki.raptorcs.com/w/images/a/a3/PPE_42X_Core_Users_Manual.pdf Supports PPE42 SPR's (Including the MSR). Does not yet support exceptions, new PPE42 instructions and does not prevent access to some invalid instructions and registers (currently allows access to invalid GPR's and CR fields). Signed-off-by: Glenn Miles --- Changes from v2: - Split general CPU changes from v2 patch 1 target/ppc/cpu-models.c | 7 ++ target/ppc/cpu_init.c | 204 ++++++++++++++++++++++++++++++++------- target/ppc/helper_regs.c | 41 +++++--- target/ppc/translate.c | 6 +- 4 files changed, 203 insertions(+), 55 deletions(-) diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c index ea86ea202a..09f73e23a8 100644 --- a/target/ppc/cpu-models.c +++ b/target/ppc/cpu-models.c @@ -116,6 +116,13 @@ NULL) POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405, NULL) + /* PPE42 Embedded Controllers = */ + POWERPC_DEF("PPE42", CPU_POWERPC_PPE42, ppe42, + "Generic PPE 42") + POWERPC_DEF("PPE42X", CPU_POWERPC_PPE42X, ppe42= x, + "Generic PPE 42X") + POWERPC_DEF("PPE42XM", CPU_POWERPC_PPE42XM, ppe42= xm, + "Generic PPE 42XM") /* PowerPC 440 family = */ #if defined(TODO_USER_ONLY) POWERPC_DEF("440", CPU_POWERPC_440, 440GP, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index a0e77f2673..8759b598bc 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -1653,6 +1653,47 @@ static void register_8xx_sprs(CPUPPCState *env) * ... and more (thermal management, performance counters, ...) */ =20 +static void register_ppe42_sprs(CPUPPCState *env) +{ + spr_register(env, SPR_PPE42_EDR, "EDR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_PPE42_ISR, "ISR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_PPE42_IVPR, "IVPR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + 0xfff80000); + spr_register(env, SPR_PPE42_PIR, "PIR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_pir, + 0x00000000); + spr_register(env, SPR_PPE42_DBCR, "DBCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_40x_dbcr0, + 0x00000000); + spr_register(env, SPR_PPE42_DACR, "DACR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Timer */ + spr_register(env, SPR_DECR, "DECR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_decr, &spr_write_decr, + 0x00000000); + spr_register(env, SPR_PPE42_TSR, "TSR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_booke_tsr, + 0x00000000); + spr_register(env, SPR_BOOKE_TCR, "TCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_booke_tcr, + 0x00000000); +} + /*************************************************************************= ****/ /* Exception vectors models = */ static void init_excp_4xx(CPUPPCState *env) @@ -2200,6 +2241,79 @@ POWERPC_FAMILY(405)(ObjectClass *oc, const void *dat= a) POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; } =20 +static void init_proc_ppe42(CPUPPCState *env) +{ + register_ppe42_sprs(env); + + env->dcache_line_size =3D 32; + env->icache_line_size =3D 32; + /* Allocate hardware IRQ controller */ + ppc40x_irq_init(env_archcpu(env)); + + SET_FIT_PERIOD(8, 12, 16, 20); + SET_WDT_PERIOD(16, 20, 24, 28); +} + +static void ppe42_class_common_init(PowerPCCPUClass *pcc) +{ + pcc->init_proc =3D init_proc_ppe42; + pcc->check_pow =3D check_pow_nocheck; + pcc->check_attn =3D check_attn_none; + pcc->insns_flags =3D PPC_INSNS_BASE | + PPC_WRTEE | + PPC_CACHE | + PPC_CACHE_DCBZ | + PPC_MEM_SYNC; + pcc->msr_mask =3D R_MSR_SEM_MASK | + (1ull << MSR_IS0) | + R_MSR_SIBRC_MASK | + (1ull << MSR_LP) | + (1ull << MSR_WE) | + (1ull << MSR_IS1) | + (1ull << MSR_UIE) | + (1ull << MSR_EE) | + (1ull << MSR_ME) | + (1ull << MSR_IS2) | + (1ull << MSR_IS3) | + (1ull << MSR_IPE) | + R_MSR_SIBRCA_MASK; + pcc->mmu_model =3D POWERPC_MMU_REAL; + pcc->excp_model =3D POWERPC_EXCP_40x; + pcc->bus_model =3D PPC_FLAGS_INPUT_PPE42; + pcc->bfd_mach =3D bfd_mach_ppc_403; + pcc->flags =3D POWERPC_FLAG_PPE42 | POWERPC_FLAG_BUS_CLK; +} + +POWERPC_FAMILY(ppe42)(ObjectClass *oc, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + PowerPCCPUClass *pcc =3D POWERPC_CPU_CLASS(oc); + + dc->desc =3D "PPE 42"; + pcc->insns_flags2 =3D PPC2_PPE42; + ppe42_class_common_init(pcc); +} + +POWERPC_FAMILY(ppe42x)(ObjectClass *oc, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + PowerPCCPUClass *pcc =3D POWERPC_CPU_CLASS(oc); + + dc->desc =3D "PPE 42X"; + pcc->insns_flags2 =3D PPC2_PPE42 | PPC2_PPE42X; + ppe42_class_common_init(pcc); +} + +POWERPC_FAMILY(ppe42xm)(ObjectClass *oc, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + PowerPCCPUClass *pcc =3D POWERPC_CPU_CLASS(oc); + + dc->desc =3D "PPE 42XM"; + pcc->insns_flags2 =3D PPC2_PPE42 | PPC2_PPE42X | PPC2_PPE42XM; + ppe42_class_common_init(pcc); +} + static void init_proc_440EP(CPUPPCState *env) { register_BookE_sprs(env, 0x000000000000FFFFULL); @@ -6802,53 +6916,63 @@ static void init_ppc_proc(PowerPCCPU *cpu) =20 /* MSR bits & flags consistency checks */ if (env->msr_mask & (1 << 25)) { - switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { + switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE | + POWERPC_FLAG_PPE42)) { case POWERPC_FLAG_SPE: case POWERPC_FLAG_VRE: + case POWERPC_FLAG_PPE42: break; default: fprintf(stderr, "PowerPC MSR definition inconsistency\n" - "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n"= ); + "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n" + "or POWERPC_FLAG_PPE42\n"); exit(1); } } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { fprintf(stderr, "PowerPC MSR definition inconsistency\n" - "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n= "); + "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n" + "nor POWERPC_FLAG_PPE42\n"); exit(1); } if (env->msr_mask & (1 << 17)) { - switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { + switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE | + POWERPC_FLAG_PPE42)) { case POWERPC_FLAG_TGPR: case POWERPC_FLAG_CE: + case POWERPC_FLAG_PPE42: break; default: fprintf(stderr, "PowerPC MSR definition inconsistency\n" - "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n"= ); + "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n" + "or POWERPC_FLAG_PPE42\n"); exit(1); } - } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { + } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE | + POWERPC_FLAG_PPE42)) { fprintf(stderr, "PowerPC MSR definition inconsistency\n" - "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n= "); + "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n" + "nor POWERPC_FLAG_PPE42\n"); exit(1); } if (env->msr_mask & (1 << 10)) { switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | - POWERPC_FLAG_UBLE)) { + POWERPC_FLAG_UBLE | POWERPC_FLAG_PPE42)) { case POWERPC_FLAG_SE: case POWERPC_FLAG_DWE: case POWERPC_FLAG_UBLE: + case POWERPC_FLAG_PPE42: break; default: fprintf(stderr, "PowerPC MSR definition inconsistency\n" "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or " - "POWERPC_FLAG_UBLE\n"); + "POWERPC_FLAG_UBLE or POWERPC_FLAG_PPE42\n"); exit(1); } } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | - POWERPC_FLAG_UBLE)) { + POWERPC_FLAG_UBLE | POWERPC_FLAG_PPE42)) { fprintf(stderr, "PowerPC MSR definition inconsistency\n" "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE no= r " - "POWERPC_FLAG_UBLE\n"); + "POWERPC_FLAG_UBLE nor POWERPC_FLAG_PPE42\n"); exit(1); } if (env->msr_mask & (1 << 9)) { @@ -6867,18 +6991,23 @@ static void init_ppc_proc(PowerPCCPU *cpu) exit(1); } if (env->msr_mask & (1 << 2)) { - switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { + switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM | + POWERPC_FLAG_PPE42)) { case POWERPC_FLAG_PX: case POWERPC_FLAG_PMM: + case POWERPC_FLAG_PPE42: break; default: fprintf(stderr, "PowerPC MSR definition inconsistency\n" - "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n"); + "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n" + "or POWERPC_FLAG_PPE42\n"); exit(1); } - } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { + } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM | + POWERPC_FLAG_PPE42)) { fprintf(stderr, "PowerPC MSR definition inconsistency\n" - "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n"= ); + "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n" + "nor POWERPC_FLAG_PPE42\n"); exit(1); } if ((env->flags & POWERPC_FLAG_BUS_CLK) =3D=3D 0) { @@ -7243,39 +7372,40 @@ static void ppc_cpu_reset_hold(Object *obj, ResetTy= pe type) } =20 msr =3D (target_ulong)0; - msr |=3D (target_ulong)MSR_HVB; - msr |=3D (target_ulong)1 << MSR_EP; + if (!(env->flags & POWERPC_FLAG_PPE42)) { + msr |=3D (target_ulong)MSR_HVB; + msr |=3D (target_ulong)1 << MSR_EP; #if defined(DO_SINGLE_STEP) && 0 - /* Single step trace mode */ - msr |=3D (target_ulong)1 << MSR_SE; - msr |=3D (target_ulong)1 << MSR_BE; + /* Single step trace mode */ + msr |=3D (target_ulong)1 << MSR_SE; + msr |=3D (target_ulong)1 << MSR_BE; #endif #if defined(CONFIG_USER_ONLY) - msr |=3D (target_ulong)1 << MSR_FP; /* Allow floating point usage */ - msr |=3D (target_ulong)1 << MSR_FE0; /* Allow floating point exception= s */ - msr |=3D (target_ulong)1 << MSR_FE1; - msr |=3D (target_ulong)1 << MSR_VR; /* Allow altivec usage */ - msr |=3D (target_ulong)1 << MSR_VSX; /* Allow VSX usage */ - msr |=3D (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ - msr |=3D (target_ulong)1 << MSR_PR; + msr |=3D (target_ulong)1 << MSR_FP; /* Allow floating point usage = */ + msr |=3D (target_ulong)1 << MSR_FE0; /* Allow floating point excep= tions */ + msr |=3D (target_ulong)1 << MSR_FE1; + msr |=3D (target_ulong)1 << MSR_VR; /* Allow altivec usage */ + msr |=3D (target_ulong)1 << MSR_VSX; /* Allow VSX usage */ + msr |=3D (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ + msr |=3D (target_ulong)1 << MSR_PR; #if defined(TARGET_PPC64) - msr |=3D (target_ulong)1 << MSR_TM; /* Transactional memory */ + msr |=3D (target_ulong)1 << MSR_TM; /* Transactional memory */ #endif #if !TARGET_BIG_ENDIAN - msr |=3D (target_ulong)1 << MSR_LE; /* Little-endian user mode */ - if (!((env->msr_mask >> MSR_LE) & 1)) { - fprintf(stderr, "Selected CPU does not support little-endian.\n"); - exit(1); - } + msr |=3D (target_ulong)1 << MSR_LE; /* Little-endian user mode */ + if (!((env->msr_mask >> MSR_LE) & 1)) { + fprintf(stderr, "Selected CPU does not support little-endian.\= n"); + exit(1); + } #endif #endif =20 #if defined(TARGET_PPC64) - if (mmu_is_64bit(env->mmu_model)) { - msr |=3D (1ULL << MSR_SF); - } + if (mmu_is_64bit(env->mmu_model)) { + msr |=3D (1ULL << MSR_SF); + } #endif - + } hreg_store_msr(env, msr, 1); =20 #if !defined(CONFIG_USER_ONLY) diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 7e5726871e..aaefeffa66 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -306,9 +306,6 @@ int hreg_store_msr(CPUPPCState *env, target_ulong value= , int alter_hv) value &=3D ~(1 << MSR_ME); value |=3D env->msr & (1 << MSR_ME); } - if ((value ^ env->msr) & (R_MSR_IR_MASK | R_MSR_DR_MASK)) { - cpu_interrupt_exittb(cs); - } if ((env->mmu_model =3D=3D POWERPC_MMU_BOOKE || env->mmu_model =3D=3D POWERPC_MMU_BOOKE206) && ((value ^ env->msr) & R_MSR_GS_MASK)) { @@ -319,8 +316,14 @@ int hreg_store_msr(CPUPPCState *env, target_ulong valu= e, int alter_hv) /* Swap temporary saved registers with GPRs */ hreg_swap_gpr_tgpr(env); } - if (unlikely((value ^ env->msr) & R_MSR_EP_MASK)) { - env->excp_prefix =3D FIELD_EX64(value, MSR, EP) * 0xFFF00000; + /* PPE42 uses IR, DR and EP MSR bits for other purposes */ + if (likely(!(env->flags & POWERPC_FLAG_PPE42))) { + if ((value ^ env->msr) & (R_MSR_IR_MASK | R_MSR_DR_MASK)) { + cpu_interrupt_exittb(cs); + } + if (unlikely((value ^ env->msr) & R_MSR_EP_MASK)) { + env->excp_prefix =3D FIELD_EX64(value, MSR, EP) * 0xFFF00000; + } } /* * If PR=3D1 then EE, IR and DR must be 1 @@ -462,6 +465,23 @@ void register_generic_sprs(PowerPCCPU *cpu) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); + + spr_register(env, SPR_PVR, "PVR", + /* Linux permits userspace to read PVR */ +#if defined(CONFIG_LINUX_USER) + &spr_read_generic, +#else + SPR_NOACCESS, +#endif + SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + pcc->pvr); + + /* PPE42 doesn't support SPRG1-3, SVR or TB regs */ + if (env->insns_flags2 & PPC2_PPE42) { + return; + } + spr_register(env, SPR_SPRG1, "SPRG1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, @@ -475,17 +495,6 @@ void register_generic_sprs(PowerPCCPU *cpu) &spr_read_generic, &spr_write_generic, 0x00000000); =20 - spr_register(env, SPR_PVR, "PVR", - /* Linux permits userspace to read PVR */ -#if defined(CONFIG_LINUX_USER) - &spr_read_generic, -#else - SPR_NOACCESS, -#endif - SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - pcc->pvr); - /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE= */ if (pcc->svr !=3D POWERPC_SVR_NONE) { if (pcc->svr & POWERPC_SVR_E500) { diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 27f90c3cc5..fc817dab54 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -4264,8 +4264,10 @@ static void gen_mtmsr(DisasContext *ctx) /* L=3D1 form only updates EE and RI */ mask &=3D (1ULL << MSR_RI) | (1ULL << MSR_EE); } else { - /* mtmsr does not alter S, ME, or LE */ - mask &=3D ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S)); + if (likely(!(ctx->insns_flags2 & PPC2_PPE42))) { + /* mtmsr does not alter S, ME, or LE */ + mask &=3D ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR= _S)); + } =20 /* * XXX: we need to update nip before the store if we enter --=20 2.43.0 From nobody Wed Sep 10 01:55:30 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1757361885; cv=none; d=zohomail.com; s=zohoarc; b=X0XkOgwOXxjEcivru0jMwtzhw+M1c6noOhQ7C64R9ggcNMeorgLSEWXJxTBQztZRv/+yE6S/axUa5dGzpa34uKQ3Q9BKds+SP54pXQ4jcBKjJ5njKgaPjaWR5p8WEztyRgUUkrw6I4j1JXZVh5/nPaKq63DP5lLA+HMScqyKAAE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1757361885; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ZxrZpsIH/cZNyxirGJ9eYD0u2tv0u7H9eYN85zUAfU0=; b=YG2igPFS3gbJBUrHuFtefFA1ABjWR93TYACRM3UBs6c2stEMLcRejWwYgN5W03wFNVgejBWyDMY7ABNoXd2wz8qS19N7w71XT3sC8HnS6DdVSCNX8Cg91QGMc86E5dmNokLj3p+BUeu8dJAVqZ4ovvz3xNpYOZ4ikT9Kcsu5LfM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175736188524822.529833654476874; Mon, 8 Sep 2025 13:04:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uvi3T-0001nb-48; Mon, 08 Sep 2025 16:01:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uvi3R-0001mm-5h; Mon, 08 Sep 2025 16:01:33 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uvi3O-0006tQ-VX; Mon, 08 Sep 2025 16:01:32 -0400 Received: from pps.filterd (m0360083.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 588J5vL4030018; Mon, 8 Sep 2025 20:01:27 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 490cff3pyb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 20:01:26 +0000 (GMT) Received: from m0360083.ppops.net (m0360083.ppops.net [127.0.0.1]) by pps.reinject (8.18.1.12/8.18.0.8) with ESMTP id 588Jx9PE000586; Mon, 8 Sep 2025 20:01:26 GMT Received: from ppma11.dal12v.mail.ibm.com (db.9e.1632.ip4.static.sl-reverse.com [50.22.158.219]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 490cff3py7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 20:01:26 +0000 (GMT) Received: from pps.filterd (ppma11.dal12v.mail.ibm.com [127.0.0.1]) by ppma11.dal12v.mail.ibm.com (8.18.1.2/8.18.1.2) with ESMTP id 588I2RA8001155; Mon, 8 Sep 2025 20:01:25 GMT Received: from smtprelay02.dal12v.mail.ibm.com ([172.16.1.4]) by ppma11.dal12v.mail.ibm.com (PPS) with ESMTPS id 4912037dy8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 20:01:25 +0000 Received: from smtpav02.wdc07v.mail.ibm.com (smtpav02.wdc07v.mail.ibm.com [10.39.53.229]) by smtprelay02.dal12v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 588K1OMx21561890 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 8 Sep 2025 20:01:24 GMT Received: from smtpav02.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3CC9D5805D; Mon, 8 Sep 2025 20:01:24 +0000 (GMT) Received: from smtpav02.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6E7ED5805B; Mon, 8 Sep 2025 20:01:23 +0000 (GMT) Received: from mglenn-KVM.. (unknown [9.10.239.198]) by smtpav02.wdc07v.mail.ibm.com (Postfix) with ESMTP; Mon, 8 Sep 2025 20:01:23 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=ZxrZpsIH/cZNyxirG J9eYD0u2tv0u7H9eYN85zUAfU0=; b=OS03U+wxF2Sksw3YWg8lpHo+yScBskFyB +OjHdMDsJI1oVuSZ/vHgLPj4BGofPRWBeOxum9O8xn0NXGTPW/n31/oZtsicqX9m kMb3Ne9gmMPutpc4M5ZNiFXJ6kL+UiPXCfJuO3SMccHH9OXmNxk8UJnJIFhqrbBg h5hRdDMsINLOQNPI9NjHbQyGvGftnuw9uMFeIZo8z4spqxXLmE7qqXH1x3juhMyJ 11ahxuuaDOWR3HJDiHZZ8X3EdrhIa5oJWM5e27Y3MtGBuMnBoItFPKKqKR7qv+o/ LfzqvHvc1FgyCjN0Gpy0Vu6MIYmg6l0iXJZDKyEtlBW1NoKs5u5tw== From: Glenn Miles To: qemu-devel@nongnu.org Cc: Glenn Miles , qemu-ppc@nongnu.org, clg@redhat.com, npiggin@gmail.com, harshpb@linux.ibm.com, thuth@redhat.com, rathc@linux.ibm.com, richard.henderson@linaro.org Subject: [PATCH v3 3/9] target/ppc: IBM PPE42 exception flags and regs Date: Mon, 8 Sep 2025 15:00:13 -0500 Message-ID: <20250908200028.115789-4-milesg@linux.ibm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250908200028.115789-1-milesg@linux.ibm.com> References: <20250908200028.115789-1-milesg@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: e8LtuTNngVHSRFIMtuapXVGY9iLfolOH X-Proofpoint-GUID: wbRTTrZfDx80Vzt3xCm4DM5hzIVcPaXF X-Authority-Analysis: v=2.4 cv=EYDIQOmC c=1 sm=1 tr=0 ts=68bf3617 cx=c_pps a=aDMHemPKRhS1OARIsFnwRA==:117 a=aDMHemPKRhS1OARIsFnwRA==:17 a=yJojWOMRYYMA:10 a=VnNF1IyMAAAA:8 a=kP3OWSx2Bt75d2xkwRIA:9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDAyMCBTYWx0ZWRfX1Yn4wSJUMyqP 3mV/9qoKccaKOHOrONkyzF63pmH/33rvbfyE81LzZpglwSawq/F0crWIAL8uPpnvuqWNK9vNzUh 3fluAyw6tFdLZ6/brhzPdJ++YJfTAdv7CJe9aBVYbATCiV7Zp8RCB3jKXa9RhoNjXHK4w2vntPQ kLod1rUnxwjzOwtEv4Cg+qYMGTkjPHmELTLuNAAXWDJ+w9AZI/nrspO64zM4orYanMmF3lzeCvN azY9Hh1suLCJf4zxk2Cr9TV4YE6Fg1RDailqSTRvzEvZrUeoCgSyALc1wUsWhhIf5zNoRp1gTbP I8/+XJnd3OnjHsmMeUfCb5hQqlgkQ6yXsprychHhQWD+F+ko569kO3kYh8ENPqsxBJ96awdO9HX g8eERy3t X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-08_06,2025-09-08_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 suspectscore=0 spamscore=0 impostorscore=0 priorityscore=1501 phishscore=0 clxscore=1015 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060020 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=milesg@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1757361885624116600 Content-Type: text/plain; charset="utf-8" Introduces flags and register definitions needed for the IBM PPE42 exception model. Signed-off-by: Glenn Miles --- Changes from v2: - Split exception flags and registers from v2 patch 1 target/ppc/cpu.h | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 81a0e16641..c68dd4f141 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -220,6 +220,8 @@ typedef enum powerpc_excp_t { POWERPC_EXCP_POWER10, /* POWER11 exception model */ POWERPC_EXCP_POWER11, + /* PPE42 exception model */ + POWERPC_EXCP_PPE42, } powerpc_excp_t; =20 /*************************************************************************= ****/ @@ -760,6 +762,31 @@ FIELD(MSR, SIBRCA, MSR_SIBRCA7, 8) #define ESR_VLEMI PPC_BIT(58) /* VLE operation */ #define ESR_MIF PPC_BIT(62) /* Misaligned instruction (VLE) */ =20 +/* PPE42 Interrupt Status Register bits */ +#define PPE42_ISR_SRSMS0 PPC_BIT_NR(48) /* Sys Reset State Machine State = 0 */ +#define PPE42_ISR_SRSMS1 PPC_BIT_NR(49) /* Sys Reset State Machine State = 1 */ +#define PPE42_ISR_SRSMS2 PPC_BIT_NR(50) /* Sys Reset State Machine State = 2 */ +#define PPE42_ISR_SRSMS3 PPC_BIT_NR(51) /* Sys Reset State Machine State = 3 */ +#define PPE42_ISR_EP PPC_BIT_NR(53) /* MSR[EE] Maskable Event Pending= */ +#define PPE42_ISR_PTR PPC_BIT_NR(56) /* Program Interrupt from trap = */ +#define PPE42_ISR_ST PPC_BIT_NR(57) /* Data Interrupt caused by store= */ +#define PPE42_ISR_MFE PPC_BIT_NR(60) /* Multiple Fault Error = */ +#define PPE42_ISR_MCS0 PPC_BIT_NR(61) /* Machine Check Status bit0 = */ +#define PPE42_ISR_MCS1 PPC_BIT_NR(62) /* Machine Check Status bit1 = */ +#define PPE42_ISR_MCS2 PPC_BIT_NR(63) /* Machine Check Status bit2 = */ +FIELD(PPE42_ISR, SRSMS, PPE42_ISR_SRSMS3, 4) +FIELD(PPE42_ISR, MCS, PPE42_ISR_MCS2, 3) + +/* PPE42 Machine Check Status field values */ +#define PPE42_ISR_MCS_INSTRUCTION 0 +#define PPE42_ISR_MCS_DATA_LOAD 1 +#define PPE42_ISR_MCS_DATA_PRECISE_STORE 2 +#define PPE42_ISR_MCS_DATA_IMPRECISE_STORE 3 +#define PPE42_ISR_MCS_PROGRAM 4 +#define PPE42_ISR_MCS_ISI 5 +#define PPE42_ISR_MCS_ALIGNMENT 6 +#define PPE42_ISR_MCS_DSI 7 + /* Transaction EXception And Summary Register bits = */ #define TEXASR_FAILURE_PERSISTENT (63 - 7) #define TEXASR_DISALLOWED (63 - 8) --=20 2.43.0 From nobody Wed Sep 10 01:55:30 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1757361930; cv=none; d=zohomail.com; s=zohoarc; b=Wg7UeHjPMWOoRFHH8QABDJGPfvHVYZq66ak7jSQL9n5CGZa/Il0spW/2nEjrE9nlfJxL2pspi8HsGMy1bxgCXvY6aewMLnqf/G8GFnsJNXmjUhMl9PL61ILnBQxBtEvABMqfMU2WyXsJ1eQn8t6MWaRnQkg12bBgCpX+fLHCtqI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1757361930; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=BqyMs1gqmQOLLuNrdoGToJpHq5rq8LOmEAHHJRZbLrY=; b=G6/6ZpUOMx2gTQ2Q0NX3ffh4muDMQv+nz4jaMQ9jkmEMl+g+MbJyXuKSWr1EPOIIENqF45g0jOulw6IUg0BIfSRPD8te839veMn8ebvCrcj5RhjaijO8qmAtz2CaH29ay+4pL8/L+coTh6kGXXaMzJ29PttrPU6/6yYIn2G9TEw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1757361930924979.5699277551527; Mon, 8 Sep 2025 13:05:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uvi3f-0001rA-5i; Mon, 08 Sep 2025 16:01:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uvi3d-0001qM-FE; Mon, 08 Sep 2025 16:01:45 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uvi3V-0006u1-Ch; Mon, 08 Sep 2025 16:01:45 -0400 Received: from pps.filterd (m0356516.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 588JcNdm009190; Mon, 8 Sep 2025 20:01:30 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 490acqunna-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 20:01:30 +0000 (GMT) Received: from m0356516.ppops.net (m0356516.ppops.net [127.0.0.1]) by pps.reinject (8.18.1.12/8.18.0.8) with ESMTP id 588K0Cxl024831; Mon, 8 Sep 2025 20:01:29 GMT Received: from ppma11.dal12v.mail.ibm.com (db.9e.1632.ip4.static.sl-reverse.com [50.22.158.219]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 490acqunn7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 20:01:29 +0000 (GMT) Received: from pps.filterd (ppma11.dal12v.mail.ibm.com [127.0.0.1]) by ppma11.dal12v.mail.ibm.com (8.18.1.2/8.18.1.2) with ESMTP id 588I2RAC001155; Mon, 8 Sep 2025 20:01:28 GMT Received: from smtprelay05.dal12v.mail.ibm.com ([172.16.1.7]) by ppma11.dal12v.mail.ibm.com (PPS) with ESMTPS id 4912037dyp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 20:01:28 +0000 Received: from smtpav02.wdc07v.mail.ibm.com (smtpav02.wdc07v.mail.ibm.com [10.39.53.229]) by smtprelay05.dal12v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 588K1RGI27591122 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 8 Sep 2025 20:01:28 GMT Received: from smtpav02.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 976045805C; Mon, 8 Sep 2025 20:01:27 +0000 (GMT) Received: from smtpav02.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C9ECC5805E; Mon, 8 Sep 2025 20:01:26 +0000 (GMT) Received: from mglenn-KVM.. (unknown [9.10.239.198]) by smtpav02.wdc07v.mail.ibm.com (Postfix) with ESMTP; Mon, 8 Sep 2025 20:01:26 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=BqyMs1gqmQOLLuNrd oGToJpHq5rq8LOmEAHHJRZbLrY=; b=s45viWSJagLr9fqRJ65xt/GW5QHG/GtsY hReVzxdufDVQshuwQxxyD9Ci3XUQ2aI0E9u/mmTEX4giApQAjFBvZ6lxJMvaoU3b q8mXd6yKaKnDU5swIl/D25GpR9rZ9dGHRh3TxiEeYfyehYSBCatKCoaUPbqDeZbV 04IrVq8DNJLygy+97kQaMjM0dK3STmrXkYuWOeMYn6tBkAMTcWJJtYrgbNEhO8wl Wu0o/g5cue6MHaKOUL66EAvDAm/tQ/L5ymRriKWEqBJI1SV3/0DfW1eMe+1EF0ib /ezQKmvLGoLiFoN2YcYpJnSmc8DLYZeJK+0v5+VZxdF2tGjPKeD1Q== From: Glenn Miles To: qemu-devel@nongnu.org Cc: Glenn Miles , qemu-ppc@nongnu.org, clg@redhat.com, npiggin@gmail.com, harshpb@linux.ibm.com, thuth@redhat.com, rathc@linux.ibm.com, richard.henderson@linaro.org Subject: [PATCH v3 4/9] target/ppc: Add IBM PPE42 exception model Date: Mon, 8 Sep 2025 15:00:14 -0500 Message-ID: <20250908200028.115789-5-milesg@linux.ibm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250908200028.115789-1-milesg@linux.ibm.com> References: <20250908200028.115789-1-milesg@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: cLEvvBAd52qjR8shN8_sulhvxypnzF7q X-Authority-Analysis: v=2.4 cv=Mp1S63ae c=1 sm=1 tr=0 ts=68bf361a cx=c_pps a=aDMHemPKRhS1OARIsFnwRA==:117 a=aDMHemPKRhS1OARIsFnwRA==:17 a=yJojWOMRYYMA:10 a=VnNF1IyMAAAA:8 a=h1b_CP1ddBs6gX6iP-IA:9 X-Proofpoint-ORIG-GUID: D9qGkRNTzJTZMMkR-mRHzik-JjM2Y5Wj X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDAwMCBTYWx0ZWRfX13+PjH2HGFZS oiU5s1tpJODEK2glc51sqLgropNyfUj0OF215QVs0Z4VyoXucDh5darfTtQa+l23DVFMmgXFucM W3F/j9NUX4gUGhffZIDoW71/DZIr2uz2BNGdvFPudQ7x6LLVDPeTarqYKo/QwbxW1244rb3WxEM pBK2VpkwfFyd1dm9tMYzDTEf8Wdz3J7DPytCu23o4DuDb4VTFfYNUxDDtCbL4gEEFw5xHURsqLI qAw9//35/yZcHtBc7NkJwLS4txbNpzEgZSXc/kLBa/SQQUMrpYPsCvVe/qiH3tRIWSLKL+rz9fn YqWl207Fvs8mS0AXA0PDfdZ4ExfMnj3gVUA+MvEcxzMBtP0xRDAjS74Rhlo38tO4jlpeXpS0aK7 4LEPe5/Y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-08_06,2025-09-08_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 clxscore=1015 phishscore=0 spamscore=0 adultscore=0 priorityscore=1501 bulkscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060000 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=milesg@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1757361932563116600 Content-Type: text/plain; charset="utf-8" Add support for the IBM PPE42 exception model including new exception vectors, exception priorities and setting of PPE42 SPRs for determining the cause of an exception. Signed-off-by: Glenn Miles --- Changes from v2: - Split exception changes from v2 patch 1 target/ppc/cpu_init.c | 39 ++++++++- target/ppc/excp_helper.c | 163 +++++++++++++++++++++++++++++++++++ target/ppc/tcg-excp_helper.c | 12 +++ 3 files changed, 213 insertions(+), 1 deletion(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 8759b598bc..698d61bf0c 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -1720,6 +1720,30 @@ static void init_excp_4xx(CPUPPCState *env) #endif } =20 +static void init_excp_ppe42(CPUPPCState *env) +{ +#if !defined(CONFIG_USER_ONLY) + /* Machine Check vector changed after version 0 */ + if (((env->spr[SPR_PVR] & 0xf00000ul) >> 20) =3D=3D 0) { + env->excp_vectors[POWERPC_EXCP_MCHECK] =3D 0x00000000; + } else { + env->excp_vectors[POWERPC_EXCP_MCHECK] =3D 0x00000020; + } + env->excp_vectors[POWERPC_EXCP_RESET] =3D 0x00000040; + env->excp_vectors[POWERPC_EXCP_DSI] =3D 0x00000060; + env->excp_vectors[POWERPC_EXCP_ISI] =3D 0x00000080; + env->excp_vectors[POWERPC_EXCP_EXTERNAL] =3D 0x000000A0; + env->excp_vectors[POWERPC_EXCP_ALIGN] =3D 0x000000C0; + env->excp_vectors[POWERPC_EXCP_PROGRAM] =3D 0x000000E0; + env->excp_vectors[POWERPC_EXCP_DECR] =3D 0x00000100; + env->excp_vectors[POWERPC_EXCP_FIT] =3D 0x00000120; + env->excp_vectors[POWERPC_EXCP_WDT] =3D 0x00000140; + env->ivpr_mask =3D 0xFFFFFE00UL; + /* Hardware reset vector */ + env->hreset_vector =3D 0x00000040UL; +#endif +} + static void init_excp_MPC5xx(CPUPPCState *env) { #if !defined(CONFIG_USER_ONLY) @@ -2245,6 +2269,7 @@ static void init_proc_ppe42(CPUPPCState *env) { register_ppe42_sprs(env); =20 + init_excp_ppe42(env); env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ @@ -2278,7 +2303,7 @@ static void ppe42_class_common_init(PowerPCCPUClass *= pcc) (1ull << MSR_IPE) | R_MSR_SIBRCA_MASK; pcc->mmu_model =3D POWERPC_MMU_REAL; - pcc->excp_model =3D POWERPC_EXCP_40x; + pcc->excp_model =3D POWERPC_EXCP_PPE42; pcc->bus_model =3D PPC_FLAGS_INPUT_PPE42; pcc->bfd_mach =3D bfd_mach_ppc_403; pcc->flags =3D POWERPC_FLAG_PPE42 | POWERPC_FLAG_BUS_CLK; @@ -7855,6 +7880,18 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int f= lags) * they can be read with "p $ivor0", "p $ivor1", etc. */ break; + case POWERPC_EXCP_PPE42: + qemu_fprintf(f, "SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx "\n", + env->spr[SPR_SRR0], env->spr[SPR_SRR1]); + + qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx + " ISR " TARGET_FMT_lx " EDR " TARGET_FMT_lx "\n", + env->spr[SPR_PPE42_TCR], env->spr[SPR_PPE42_TSR], + env->spr[SPR_PPE42_ISR], env->spr[SPR_PPE42_EDR]); + + qemu_fprintf(f, " PIR " TARGET_FMT_lx " IVPR " TARGET_FMT_lx "\= n", + env->spr[SPR_PPE42_PIR], env->spr[SPR_PPE42_IVPR]); + break; case POWERPC_EXCP_40x: qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n= ", diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 1efdc4066e..d8bca19fff 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -949,6 +949,125 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int ex= cp) powerpc_set_excp_state(cpu, vector, new_msr); } =20 +static void powerpc_excp_ppe42(PowerPCCPU *cpu, int excp) +{ + CPUPPCState *env =3D &cpu->env; + target_ulong msr, new_msr, vector; + target_ulong mcs =3D PPE42_ISR_MCS_INSTRUCTION; + bool promote_unmaskable; + + msr =3D env->msr; + + /* + * New interrupt handler msr preserves SIBRC and ME unless explicitly + * overridden by the exception. All other MSR bits are zeroed out. + */ + new_msr =3D env->msr & (((target_ulong)1 << MSR_ME) | R_MSR_SIBRC_MASK= ); + + /* HV emu assistance interrupt only exists on server arch 2.05 or late= r */ + if (excp =3D=3D POWERPC_EXCP_HV_EMU) { + excp =3D POWERPC_EXCP_PROGRAM; + } + + /* + * Unmaskable interrupts (Program, ISI, Alignment and DSI) are promote= d to + * machine check if MSR_UIE is 0. + */ + promote_unmaskable =3D !(msr & ((target_ulong)1 << MSR_UIE)); + + + switch (excp) { + case POWERPC_EXCP_MCHECK: /* Machine check exception = */ + break; + case POWERPC_EXCP_DSI: /* Data storage exception = */ + trace_ppc_excp_dsi(env->spr[SPR_PPE42_ISR], env->spr[SPR_PPE42_EDR= ]); + if (promote_unmaskable) { + excp =3D POWERPC_EXCP_MCHECK; + mcs =3D PPE42_ISR_MCS_DSI; + } + break; + case POWERPC_EXCP_ISI: /* Instruction storage exception = */ + trace_ppc_excp_isi(msr, env->nip); + if (promote_unmaskable) { + excp =3D POWERPC_EXCP_MCHECK; + mcs =3D PPE42_ISR_MCS_ISI; + } + break; + case POWERPC_EXCP_EXTERNAL: /* External input = */ + break; + case POWERPC_EXCP_ALIGN: /* Alignment exception = */ + if (promote_unmaskable) { + excp =3D POWERPC_EXCP_MCHECK; + mcs =3D PPE42_ISR_MCS_ALIGNMENT; + } + break; + case POWERPC_EXCP_PROGRAM: /* Program exception = */ + if (promote_unmaskable) { + excp =3D POWERPC_EXCP_MCHECK; + mcs =3D PPE42_ISR_MCS_PROGRAM; + } + switch (env->error_code & ~0xF) { + case POWERPC_EXCP_INVAL: + trace_ppc_excp_inval(env->nip); + env->spr[SPR_PPE42_ISR] &=3D ~((target_ulong)1 << PPE42_ISR_PT= R); + break; + case POWERPC_EXCP_TRAP: + env->spr[SPR_PPE42_ISR] |=3D ((target_ulong)1 << PPE42_ISR_PTR= ); + break; + default: + /* Should never occur */ + cpu_abort(env_cpu(env), "Invalid program exception %d. Abortin= g\n", + env->error_code); + break; + } +#ifdef CONFIG_TCG + env->spr[SPR_PPE42_EDR] =3D ppc_ldl_code(env, env->nip); +#endif + break; + case POWERPC_EXCP_DECR: /* Decrementer exception = */ + break; + case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt = */ + trace_ppc_excp_print("FIT"); + break; + case POWERPC_EXCP_WDT: /* Watchdog timer interrupt = */ + trace_ppc_excp_print("WDT"); + break; + case POWERPC_EXCP_RESET: /* System reset exception = */ + /* reset exceptions don't have ME set */ + new_msr &=3D ~((target_ulong)1 << MSR_ME); + break; + default: + cpu_abort(env_cpu(env), "Invalid PPE42 exception %d. Aborting\n", + excp); + break; + } + + env->spr[SPR_SRR0] =3D env->nip; + env->spr[SPR_SRR1] =3D msr; + + vector =3D env->excp_vectors[excp]; + if (vector =3D=3D (target_ulong)-1ULL) { + cpu_abort(env_cpu(env), + "Raised an exception without defined vector %d\n", excp); + } + vector |=3D env->spr[SPR_PPE42_IVPR]; + + if (excp =3D=3D POWERPC_EXCP_MCHECK) { + /* Also set the Machine Check Status (MCS) */ + env->spr[SPR_PPE42_ISR] &=3D ~R_PPE42_ISR_MCS_MASK; + env->spr[SPR_PPE42_ISR] |=3D (mcs & R_PPE42_ISR_MCS_MASK); + env->spr[SPR_PPE42_ISR] &=3D ~((target_ulong)1 << PPE42_ISR_MFE); + + /* Machine checks halt execution if MSR_ME is 0 */ + powerpc_mcheck_checkstop(env); + + /* machine check exceptions don't have ME set */ + new_msr &=3D ~((target_ulong)1 << MSR_ME); + } + + powerpc_set_excp_state(cpu, vector, new_msr); +} + static void powerpc_excp_booke(PowerPCCPU *cpu, int excp) { CPUPPCState *env =3D &cpu->env; @@ -1589,6 +1708,9 @@ void powerpc_excp(PowerPCCPU *cpu, int excp) case POWERPC_EXCP_POWER11: powerpc_excp_books(cpu, excp); break; + case POWERPC_EXCP_PPE42: + powerpc_excp_ppe42(cpu, excp); + break; default: g_assert_not_reached(); } @@ -1945,6 +2067,43 @@ static int p9_next_unmasked_interrupt(CPUPPCState *e= nv, } #endif /* TARGET_PPC64 */ =20 +static int ppe42_next_unmasked_interrupt(CPUPPCState *env) +{ + bool async_deliver; + + /* External reset */ + if (env->pending_interrupts & PPC_INTERRUPT_RESET) { + return PPC_INTERRUPT_RESET; + } + /* Machine check exception */ + if (env->pending_interrupts & PPC_INTERRUPT_MCK) { + return PPC_INTERRUPT_MCK; + } + + async_deliver =3D FIELD_EX64(env->msr, MSR, EE); + + if (async_deliver !=3D 0) { + /* Watchdog timer */ + if (env->pending_interrupts & PPC_INTERRUPT_WDT) { + return PPC_INTERRUPT_WDT; + } + /* External Interrupt */ + if (env->pending_interrupts & PPC_INTERRUPT_EXT) { + return PPC_INTERRUPT_EXT; + } + /* Fixed interval timer */ + if (env->pending_interrupts & PPC_INTERRUPT_FIT) { + return PPC_INTERRUPT_FIT; + } + /* Decrementer exception */ + if (env->pending_interrupts & PPC_INTERRUPT_DECR) { + return PPC_INTERRUPT_DECR; + } + } + + return 0; +} + static int ppc_next_unmasked_interrupt(CPUPPCState *env) { uint32_t pending_interrupts =3D env->pending_interrupts; @@ -1970,6 +2129,10 @@ static int ppc_next_unmasked_interrupt(CPUPPCState *= env) } #endif =20 + if (env->excp_model =3D=3D POWERPC_EXCP_PPE42) { + return ppe42_next_unmasked_interrupt(env); + } + /* External reset */ if (pending_interrupts & PPC_INTERRUPT_RESET) { return PPC_INTERRUPT_RESET; diff --git a/target/ppc/tcg-excp_helper.c b/target/ppc/tcg-excp_helper.c index f835be5156..edecfb8572 100644 --- a/target/ppc/tcg-excp_helper.c +++ b/target/ppc/tcg-excp_helper.c @@ -229,6 +229,18 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr v= addr, case POWERPC_MMU_BOOKE206: env->spr[SPR_BOOKE_DEAR] =3D vaddr; break; + case POWERPC_MMU_REAL: + if (env->flags & POWERPC_FLAG_PPE42) { + env->spr[SPR_PPE42_EDR] =3D vaddr; + if (access_type =3D=3D MMU_DATA_STORE) { + env->spr[SPR_PPE42_ISR] |=3D PPE42_ISR_ST; + } else { + env->spr[SPR_PPE42_ISR] &=3D ~PPE42_ISR_ST; + } + } else { + env->spr[SPR_DAR] =3D vaddr; + } + break; default: env->spr[SPR_DAR] =3D vaddr; break; --=20 2.43.0 From nobody Wed Sep 10 01:55:30 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1757361762; cv=none; d=zohomail.com; s=zohoarc; b=T7JjYAd/mqiQbHRrhUbV44lDazKbYXm5z09kGHSYfKyV14iQGkcT7nELdUVTMci/5QzEhBslCswq1Y/rMooqCuXRZPhoMDQI2eJ6whhO7eSQj0AcJIHmLDaI7/Y/P/B4ARH8atn69lVkGw01gv8KB+Zd7Z1LLMzruVBLRUW1eSM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1757361762; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=uDB0VznG86QpKWSk7+vbMedx2AEfs7dNe5SWwhZAs28=; b=FhROWPsIpbqdVmVkJpNCllox6+xfaFISD/OoFFxLarLEiBuL4vv7UyYjrM4o0xvyVHV4Dk30iuYv/F3/VT6VrSIzxMWjTp8qrRHtpaIOU3BLRtUUWLJtq+YwuMaYgz5l31LUSnWLjCGK9eidfOTMsT3MtnHFiwJ2cCslT/UYGSU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1757361762742303.20068867940824; Mon, 8 Sep 2025 13:02:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uvi3Y-0001pI-TD; Mon, 08 Sep 2025 16:01:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uvi3X-0001ow-8G; Mon, 08 Sep 2025 16:01:39 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uvi3U-0006v5-Ub; Mon, 08 Sep 2025 16:01:39 -0400 Received: from pps.filterd (m0360072.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 588IrUcN010489; Mon, 8 Sep 2025 20:01:33 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 490uke8wph-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 20:01:33 +0000 (GMT) Received: from m0360072.ppops.net (m0360072.ppops.net [127.0.0.1]) by pps.reinject (8.18.1.12/8.18.0.8) with ESMTP id 588K0lEN013726; Mon, 8 Sep 2025 20:01:32 GMT Received: from ppma23.wdc07v.mail.ibm.com (5d.69.3da9.ip4.static.sl-reverse.com [169.61.105.93]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 490uke8wpb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 20:01:32 +0000 (GMT) Received: from pps.filterd (ppma23.wdc07v.mail.ibm.com [127.0.0.1]) by ppma23.wdc07v.mail.ibm.com (8.18.1.2/8.18.1.2) with ESMTP id 588H5fni010594; Mon, 8 Sep 2025 20:01:32 GMT Received: from smtprelay02.wdc07v.mail.ibm.com ([172.16.1.69]) by ppma23.wdc07v.mail.ibm.com (PPS) with ESMTPS id 4910smqnj0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 20:01:32 +0000 Received: from smtpav02.wdc07v.mail.ibm.com (smtpav02.wdc07v.mail.ibm.com [10.39.53.229]) by smtprelay02.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 588K1VdK21693004 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 8 Sep 2025 20:01:31 GMT Received: from smtpav02.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id EAD6D58059; Mon, 8 Sep 2025 20:01:30 +0000 (GMT) Received: from smtpav02.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1EACB5805D; Mon, 8 Sep 2025 20:01:30 +0000 (GMT) Received: from mglenn-KVM.. (unknown [9.10.239.198]) by smtpav02.wdc07v.mail.ibm.com (Postfix) with ESMTP; Mon, 8 Sep 2025 20:01:30 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=uDB0VznG86QpKWSk7 +vbMedx2AEfs7dNe5SWwhZAs28=; b=q2y0QmBamCZD+hwwGl5gyWAWN3+DUNMlQ 7YkRE9TvWj1duBZRHnmL0bo6hqFIwk488kxXxSGfHC3LF4ETrx89mUONeE69Bppe jtZvFe1r0VNlHXrMSnlQ+VVPHDBkBmPvUSZKUMeRh4uR5NqihsvhjFzs5S4OyE5V a/Fqdi2kA3vbL0Rm5FY6yn8q9tLRd048pAGJlG+8Tij0lMCFwHVZ+CHMOI0ZIGmP dvWdOcS/SwJl4tgdmoH0T+mdbnbKJ0GpYh3C6WAX4jhfy6ftcWVsTlPIqN+K/ahW q+fNEQdxCOxjj3ijtb9x+atWjwIb+UlgP3dD7tiraHXPH3E0vckhA== From: Glenn Miles To: qemu-devel@nongnu.org Cc: Glenn Miles , qemu-ppc@nongnu.org, clg@redhat.com, npiggin@gmail.com, harshpb@linux.ibm.com, thuth@redhat.com, rathc@linux.ibm.com, richard.henderson@linaro.org Subject: [PATCH v3 5/9] target/ppc: Support for IBM PPE42 MMU Date: Mon, 8 Sep 2025 15:00:15 -0500 Message-ID: <20250908200028.115789-6-milesg@linux.ibm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250908200028.115789-1-milesg@linux.ibm.com> References: <20250908200028.115789-1-milesg@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDE5NSBTYWx0ZWRfX4ZDS5SsIZO/E tEBxMt7gFL0a3eC3/UAfA0aWY3pd6tN0+2oqSUxu75KwSOitLWBARBLuz3wpGoWzsFv657fJ3jw rykJMOrMERsJLr4vRWkYc3kllQLnecnVKbK6bBT/683d1hwpZNauEWorGcbz4TXWiOIZWIC6hsL CwHObye3X4ykVxvR2GEIUxF+JhoC8AbBpZYRfcjXg/jhjOGMBtaFb4zacZ/SJQUzHxpC2+4XADw mmzEr2OJnnORmtxYz/6K++ZQ/4U/DBnYuPXSjA8OUQhq+gcwyB6r2+fHUyl1kQB6AhRPPBL+Esb qvfVbFHCcAcwGZUhjAFVBKHrLwxBcW4MUNxvKMUCiHbv/WWF/WzZlZWZGgKcPhTSiT8aMn1+b4s LVrygME4 X-Proofpoint-ORIG-GUID: qJ_m_-NrrVGW3BXWpA90mhWBkSIPwS47 X-Proofpoint-GUID: DAC9405k0zBFM92epvUzXRp4oEwJg3G1 X-Authority-Analysis: v=2.4 cv=StCQ6OO0 c=1 sm=1 tr=0 ts=68bf361d cx=c_pps a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17 a=yJojWOMRYYMA:10 a=VnNF1IyMAAAA:8 a=Uotnjwh7_nUNd4_WO1gA:9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-08_06,2025-09-08_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 bulkscore=0 clxscore=1015 adultscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060195 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=milesg@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1757361767152124100 Content-Type: text/plain; charset="utf-8" The IBM PPE42 processor only supports real mode addressing and does not distinguish between problem and supervisor states. It also uses the IR and DR MSR bits for other purposes. Therefore, add a check for PPE42 when we update hflags and cause it to ignore the IR and DR bits when calculating MMU indexes. Signed-off-by: Glenn Miles --- Changes from v2: - Split MMU changes from v2 patch 1 target/ppc/helper_regs.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index aaefeffa66..29158342d5 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -186,6 +186,10 @@ static uint32_t hreg_compute_hflags_value(CPUPPCState = *env) if (env->spr[SPR_LPCR] & LPCR_HR) { hflags |=3D 1 << HFLAGS_HR; } + if (unlikely(ppc_flags & POWERPC_FLAG_PPE42)) { + /* PPE42 has a single address space and no problem state */ + msr =3D 0; + } =20 #ifndef CONFIG_USER_ONLY if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) { --=20 2.43.0 From nobody Wed Sep 10 01:55:30 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1757361929; cv=none; d=zohomail.com; s=zohoarc; b=eEHQTG+AgW7EyVIcQT2Ovlc4qiCwj2C5HmCe/3YYyTiHSQFAj2aqoLlsjszPimX0m75T7HhTlg7N00dDOIJpyODME7inNPehBjJPg0sr4tOBuZqe6ZqbiL/tTHYY5q0Ipxs3TjURx9cvTg/pvhpmRQwUAUdCfOLavD9E2C7gaiQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1757361929; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=66AsjjSVRcegvuBOhATGuGDiMuBVz3edsYg/bJM2AGk=; b=RxR8vhD94uxCRHOoRKFcLy47TWFa0qtHiOuA0EObo5hNUEB3Faglw5a2Ch3yDAaCcGDUZeIYsQ/GLE9tr6eufkEreZcGIU27cQwKTox6AMDI+kBJ0M//brZpiY5UhNmS27GK5KglHhfZRefRnq8xYiFRUJbstSvqeAtXQLeg83k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1757361929384908.1183621807221; Mon, 8 Sep 2025 13:05:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uvi3f-0001rJ-Cg; Mon, 08 Sep 2025 16:01:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uvi3d-0001qB-8D; Mon, 08 Sep 2025 16:01:45 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uvi3Z-0006vo-2s; Mon, 08 Sep 2025 16:01:44 -0400 Received: from pps.filterd (m0356516.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 588CUGxG020168; Mon, 8 Sep 2025 20:01:37 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 490acqunpf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 20:01:37 +0000 (GMT) Received: from m0356516.ppops.net (m0356516.ppops.net [127.0.0.1]) by pps.reinject (8.18.1.12/8.18.0.8) with ESMTP id 588JvXSl019473; Mon, 8 Sep 2025 20:01:36 GMT Received: from ppma23.wdc07v.mail.ibm.com (5d.69.3da9.ip4.static.sl-reverse.com [169.61.105.93]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 490acqunpc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 20:01:36 +0000 (GMT) Received: from pps.filterd (ppma23.wdc07v.mail.ibm.com [127.0.0.1]) by ppma23.wdc07v.mail.ibm.com (8.18.1.2/8.18.1.2) with ESMTP id 588H5fnj010594; Mon, 8 Sep 2025 20:01:36 GMT Received: from smtprelay05.wdc07v.mail.ibm.com ([172.16.1.72]) by ppma23.wdc07v.mail.ibm.com (PPS) with ESMTPS id 4910smqnjp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 20:01:36 +0000 Received: from smtpav02.wdc07v.mail.ibm.com (smtpav02.wdc07v.mail.ibm.com [10.39.53.229]) by smtprelay05.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 588K1YdN11797134 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 8 Sep 2025 20:01:34 GMT Received: from smtpav02.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 95E9E5805C; Mon, 8 Sep 2025 20:01:34 +0000 (GMT) Received: from smtpav02.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B4AFF5805B; Mon, 8 Sep 2025 20:01:33 +0000 (GMT) Received: from mglenn-KVM.. (unknown [9.10.239.198]) by smtpav02.wdc07v.mail.ibm.com (Postfix) with ESMTP; Mon, 8 Sep 2025 20:01:33 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=66AsjjSVRcegvuBOh ATGuGDiMuBVz3edsYg/bJM2AGk=; b=ZP0kVRy3iOuxZcHVHfJ9g1VxrG7Eoa1Vd /QX7HHfdT+jZphEtV8v7ZUgT69NkVmdbwPZX468quQAq180YUWerTiFC4eQL92BO 7YrMUY506Ae4W1A+DZGmxZn/RAiG5yVdeKc6Bzf6EBkwV1JvGdg/pYM9dvSauUe7 6HN6kzQBV8p/vsnX+srV7A6AZwAdWioIzM3emYv35N9jMdAx7R2nuRDlCmKQFDBh sr3bWoozrNdws1i6jAx0LnY+2qfyLPeTcIeSkV/DcFSOGYOK1XPlTkmmVw9uNVLK 18ICeI+ljHIAOhB6LN24m7KE+mFlfZ9Xm1E/zsF9ZMwHrnHmBhq6A== From: Glenn Miles To: qemu-devel@nongnu.org Cc: Glenn Miles , qemu-ppc@nongnu.org, clg@redhat.com, npiggin@gmail.com, harshpb@linux.ibm.com, thuth@redhat.com, rathc@linux.ibm.com, richard.henderson@linaro.org Subject: [PATCH v3 6/9] target/ppc: Add IBM PPE42 special instructions Date: Mon, 8 Sep 2025 15:00:16 -0500 Message-ID: <20250908200028.115789-7-milesg@linux.ibm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250908200028.115789-1-milesg@linux.ibm.com> References: <20250908200028.115789-1-milesg@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: KdXe8xY6pQGzPkbNYTivUDL5gilXGKPN X-Authority-Analysis: v=2.4 cv=Mp1S63ae c=1 sm=1 tr=0 ts=68bf3621 cx=c_pps a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17 a=yJojWOMRYYMA:10 a=NEAV23lmAAAA:8 a=jRLB2SoPAAAA:8 a=VnNF1IyMAAAA:8 a=pXgVCJyPgkniI-CB58UA:9 a=yloqiLrygL2q3s9aD-8D:22 X-Proofpoint-ORIG-GUID: 0KeH774ORm40pBI75YP_BN5gv20usGF- X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDAwMCBTYWx0ZWRfX5ZYyaFotWpF9 J4VpxiSD3mQle+bVBR5CziV/5WRu/xn3q+Udz0ZWCqF3eIFHzQ6wl9NeM2Ijdsf2faa6S0n7WUH NifQdpaRoC2CGVRSajqoXxC9nZBnrinY9BXP9ZPNqbhsoXSTM9e2EVKFIJkDrPaEVA/sf6LnxFA THvhttF0NCdh3KQJt1rimLgBk/Q4gI5PgagXXfjo9+ETeHLXrp/Mayw0iMMuo8STHIzOQllc//B 0gsj6Gy1ISIg5iFZ1qq3YdPleUvWoS8CE7LmTCZmx9i5d0Qt7QUspSBDqt+X0LiZsLxgTiPahnp 8+azPjqImvDzXxWKJ35Joo9DUw5qY/YbTbxZXKZA9cmpkouVZTZQapyykIn92yB3R2Vi2rZz0RM ylCaUZHc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-08_06,2025-09-08_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 clxscore=1015 phishscore=0 spamscore=0 adultscore=0 priorityscore=1501 bulkscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060000 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=milesg@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1757361932239116600 Content-Type: text/plain; charset="utf-8" Adds the following instructions exclusively for IBM PPE42 processors: LSKU LCXU STSKU STCXU LVD LVDU LVDX STVD STVDU STVDX SLVD SRVD CMPWBC CMPLWBC CMPWIBC BNBWI BNBW CLRBWIBC CLRWBC DCBQ RLDICL RLDICR RLDIMI A PPE42 GCC compiler is available here: https://github.com/open-power/ppe42-gcc For more information on the PPE42 processors please visit: https://wiki.raptorcs.com/w/images/a/a3/PPE_42X_Core_Users_Manual.pdf Signed-off-by: Glenn Miles --- Changes from v2: - Utilized the TRANS macro to reduce code target/ppc/insn32.decode | 66 ++- target/ppc/translate.c | 29 +- target/ppc/translate/ppe-impl.c.inc | 663 ++++++++++++++++++++++++++++ 3 files changed, 748 insertions(+), 10 deletions(-) create mode 100644 target/ppc/translate/ppe-impl.c.inc diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index e53fd2840d..8beb588a2a 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -58,6 +58,10 @@ %ds_rtp 22:4 !function=3Dtimes_2 @DS_rtp ...... ....0 ra:5 .............. .. &D rt=3D%d= s_rtp si=3D%ds_si =20 +%dd_si 3:s13 +&DD rt ra si:int64_t +@DD ...... rt:5 ra:5 ............. . .. &DD si=3D%= dd_si + &DX_b vrt b %dx_b 6:10 16:5 0:1 @DX_b ...... vrt:5 ..... .......... ..... . &DX_b b=3D= %dx_b @@ -66,6 +70,11 @@ %dx_d 6:s10 16:5 0:1 @DX ...... rt:5 ..... .......... ..... . &DX d=3D%d= x_d =20 +%md_sh 1:1 11:5 +%md_mb 5:1 6:5 +&MD rs ra sh mb rc +@MD ...... rs:5 ra:5 ..... ...... ... . rc:1 &MD sh=3D%= md_sh mb=3D%md_mb + &VA vrt vra vrb rc @VA ...... vrt:5 vra:5 vrb:5 rc:5 ...... &VA =20 @@ -322,6 +331,13 @@ LDUX 011111 ..... ..... ..... 0000110101 - = @X =20 LQ 111000 ..... ..... ............ ---- @DQ_rtp =20 +LVD 000101 ..... ..... ................ @D +LVDU 001001 ..... ..... ................ @D +LVDX 011111 ..... ..... ..... 0000010001 - @X +LSKU 111010 ..... ..... ............. 0 11 @DD +LCXU 111010 ..... ..... ............. 1 11 @DD + + ### Fixed-Point Store Instructions =20 STB 100110 ..... ..... ................ @D @@ -346,6 +362,11 @@ STDUX 011111 ..... ..... ..... 0010110101 - = @X =20 STQ 111110 ..... ..... ..............10 @DS_rtp =20 +STVDU 010110 ..... ..... ................ @D +STVDX 011111 ..... ..... ..... 0010010001 - @X +STSKU 111110 ..... ..... ............. 0 11 @DD +STCXU 111110 ..... ..... ............. 1 11 @DD + ### Fixed-Point Compare Instructions =20 CMP 011111 ... - . ..... ..... 0000000000 - @X_bfl @@ -461,8 +482,14 @@ PRTYD 011111 ..... ..... ----- 0010111010 - = @X_sa =20 BPERMD 011111 ..... ..... ..... 0011111100 - @X CFUGED 011111 ..... ..... ..... 0011011100 - @X -CNTLZDM 011111 ..... ..... ..... 0000111011 - @X -CNTTZDM 011111 ..... ..... ..... 1000111011 - @X +{ + SLVD 011111 ..... ..... ..... 0000111011 . @X_rc + CNTLZDM 011111 ..... ..... ..... 0000111011 - @X +} +{ + SRVD 011111 ..... ..... ..... 1000111011 . @X_rc + CNTTZDM 011111 ..... ..... ..... 1000111011 - @X +} PDEPD 011111 ..... ..... ..... 0010011100 - @X PEXTD 011111 ..... ..... ..... 0010111100 - @X =20 @@ -981,8 +1008,16 @@ LXSSP 111001 ..... ..... .............. 11 = @DS STXSSP 111101 ..... ..... .............. 11 @DS LXV 111101 ..... ..... ............ . 001 @DQ_TSX STXV 111101 ..... ..... ............ . 101 @DQ_TSX -LXVP 000110 ..... ..... ............ 0000 @DQ_TSXP -STXVP 000110 ..... ..... ............ 0001 @DQ_TSXP + +# STVD PPE instruction overlaps with the LXVP and STXVP instructions +{ + STVD 000110 ..... ..... ................ @D + [ + LXVP 000110 ..... ..... ............ 0000 @DQ_TSXP + STXVP 000110 ..... ..... ............ 0001 @DQ_TSXP + ] +} + LXVX 011111 ..... ..... ..... 0100 - 01100 . @X_TSX STXVX 011111 ..... ..... ..... 0110001100 . @X_TSX LXVPX 011111 ..... ..... ..... 0101001101 - @X_TSXP @@ -1300,3 +1335,26 @@ CLRBHRB 011111 ----- ----- ----- 0110101110 - ## Misc POWER instructions =20 ATTN 000000 00000 00000 00000 0100000000 0 + +# Fused compare-branch instructions for PPE only +%fcb_bdx 1:s10 !function=3Dtimes_4 +&FCB px:bool ra rb:uint64_t bdx lk:bool +@FCB ...... .. px:1 .. ra:5 rb:5 .......... lk:1 &FCB bdx= =3D%fcb_bdx +&FCB_bix px:bool bix ra rb:uint64_t bdx lk:bool +@FCB_bix ...... .. px:1 bix:2 ra:5 rb:5 .......... lk:1 &FCB_bix= bdx=3D%fcb_bdx + +CMPWBC 000001 00 . .. ..... ..... .......... . @FCB_bix +CMPLWBC 000001 01 . .. ..... ..... .......... . @FCB_bix +CMPWIBC 000001 10 . .. ..... ..... .......... . @FCB_bix +BNBWI 000001 11 . 00 ..... ..... .......... . @FCB +BNBW 000001 11 . 01 ..... ..... .......... . @FCB +CLRBWIBC 000001 11 . 10 ..... ..... .......... . @FCB +CLRBWBC 000001 11 . 11 ..... ..... .......... . @FCB + +# Data Cache Block Query for PPE only +DCBQ 011111 ..... ..... ..... 0110010110 - @X + +# Rotate Doubleword Instructions for PPE only (if TARGET_PPC64 not defined) +RLDICL 011110 ..... ..... ..... ...... 000 . . @MD +RLDICR 011110 ..... ..... ..... ...... 001 . . @MD +RLDIMI 011110 ..... ..... ..... ...... 011 . . @MD diff --git a/target/ppc/translate.c b/target/ppc/translate.c index fc817dab54..d422789a1d 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -209,6 +209,11 @@ struct DisasContext { #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ =20 +static inline bool is_ppe(const DisasContext *ctx) +{ + return !!(ctx->flags & POWERPC_FLAG_PPE42); +} + /* Return true iff byteswap is needed in a scalar memop */ static inline bool need_byteswap(const DisasContext *ctx) { @@ -556,11 +561,8 @@ void spr_access_nop(DisasContext *ctx, int sprn, int g= prn) =20 #endif =20 -/* SPR common to all PowerPC */ -/* XER */ -void spr_read_xer(DisasContext *ctx, int gprn, int sprn) +static void gen_get_xer(DisasContext *ctx, TCGv dst) { - TCGv dst =3D cpu_gpr[gprn]; TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); TCGv t2 =3D tcg_temp_new(); @@ -579,9 +581,16 @@ void spr_read_xer(DisasContext *ctx, int gprn, int spr= n) } } =20 -void spr_write_xer(DisasContext *ctx, int sprn, int gprn) +/* SPR common to all PowerPC */ +/* XER */ +void spr_read_xer(DisasContext *ctx, int gprn, int sprn) +{ + TCGv dst =3D cpu_gpr[gprn]; + gen_get_xer(ctx, dst); +} + +static void gen_set_xer(DisasContext *ctx, TCGv src) { - TCGv src =3D cpu_gpr[gprn]; /* Write all flags, while reading back check for isa300 */ tcg_gen_andi_tl(cpu_xer, src, ~((1u << XER_SO) | @@ -594,6 +603,12 @@ void spr_write_xer(DisasContext *ctx, int sprn, int gp= rn) tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); } =20 +void spr_write_xer(DisasContext *ctx, int sprn, int gprn) +{ + TCGv src =3D cpu_gpr[gprn]; + gen_set_xer(ctx, src); +} + /* LR */ void spr_read_lr(DisasContext *ctx, int gprn, int sprn) { @@ -5755,6 +5770,8 @@ static bool resolve_PLS_D(DisasContext *ctx, arg_D *d= , arg_PLS_D *a) =20 #include "translate/bhrb-impl.c.inc" =20 +#include "translate/ppe-impl.c.inc" + /* Handles lfdp */ static void gen_dform39(DisasContext *ctx) { diff --git a/target/ppc/translate/ppe-impl.c.inc b/target/ppc/translate/ppe= -impl.c.inc new file mode 100644 index 0000000000..847cca29f3 --- /dev/null +++ b/target/ppc/translate/ppe-impl.c.inc @@ -0,0 +1,663 @@ +/* + * IBM PPE Instructions + * + * Copyright (c) 2025, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + + +#if !defined(TARGET_PPC64) +static bool vdr_is_valid(uint32_t vdr) +{ + const uint32_t valid_bitmap =3D 0xf00003ff; + return !!((1ul << (vdr & 0x1f)) & valid_bitmap); +} + +static bool ppe_gpr_is_valid(uint32_t reg) +{ + const uint32_t valid_bitmap =3D 0xf00027ff; + return !!((1ul << (reg & 0x1f)) & valid_bitmap); +} +#endif + +#define CHECK_VDR(CTX, VDR) \ + do { \ + if (unlikely(!vdr_is_valid(VDR))) { \ + gen_invalid(CTX); \ + return true; \ + } \ + } while (0) + +#define CHECK_PPE_GPR(CTX, REG) \ + do { \ + if (unlikely(!ppe_gpr_is_valid(REG))) { \ + gen_invalid(CTX); \ + return true; \ + } \ + } while (0) + +#define CHECK_VDR(CTX, VDR) \ + do { \ + if (unlikely(!vdr_is_valid(VDR))) { \ + gen_invalid(CTX); \ + return true; \ + } \ + } while (0) + +#define VDR_PAIR_REG(VDR) (((VDR) + 1) & 0x1f) + +#define CHECK_PPE_LEVEL(CTX, LVL) \ + do { \ + if (unlikely(!((CTX)->insns_flags2 & (LVL)))) { \ + gen_invalid(CTX); \ + return true; \ + } \ + } while (0) + +static bool trans_LCXU(DisasContext *ctx, arg_LCXU *a) +{ +#if defined(TARGET_PPC64) + return false; +#else + int i; + TCGv base, EA; + TCGv lo, hi; + TCGv_i64 t8; + const uint8_t vd_list[] =3D {9, 7, 5, 3, 0}; + + if (unlikely(!is_ppe(ctx))) { + return false; + } + CHECK_PPE_LEVEL(ctx, PPC2_PPE42X); + CHECK_PPE_GPR(ctx, a->rt); + + if (unlikely((a->rt !=3D a->ra) || (a->ra =3D=3D 0) || (a->si < 0xB)))= { + gen_invalid(ctx); + return true; + } + + EA =3D tcg_temp_new(); + base =3D tcg_temp_new(); + + tcg_gen_addi_tl(base, cpu_gpr[a->ra], a->si * 8); + gen_store_spr(SPR_PPE42_EDR, base); + + t8 =3D tcg_temp_new_i64(); + + tcg_gen_addi_tl(EA, base, -8); + tcg_gen_qemu_ld_i64(t8, EA, ctx->mem_idx, DEF_MEMOP(MO_64) | MO_ALIGN); + tcg_gen_extr_i64_tl(cpu_gpr[31], cpu_gpr[30], t8); + + tcg_gen_addi_tl(EA, EA, -8); + tcg_gen_qemu_ld_i64(t8, EA, ctx->mem_idx, DEF_MEMOP(MO_64) | MO_ALIGN); + tcg_gen_extr_i64_tl(cpu_gpr[29], cpu_gpr[28], t8); + + lo =3D tcg_temp_new(); + hi =3D tcg_temp_new(); + + tcg_gen_addi_tl(EA, EA, -8); + tcg_gen_qemu_ld_i64(t8, EA, ctx->mem_idx, DEF_MEMOP(MO_64) | MO_ALIGN); + tcg_gen_extr_i64_tl(lo, hi, t8); + gen_store_spr(SPR_SRR0, hi); + gen_store_spr(SPR_SRR1, lo); + + tcg_gen_addi_tl(EA, EA, -8); + tcg_gen_qemu_ld_i64(t8, EA, ctx->mem_idx, DEF_MEMOP(MO_64) | MO_ALIGN); + tcg_gen_extr_i64_tl(lo, hi, t8); + gen_set_xer(ctx, hi); + tcg_gen_mov_tl(cpu_ctr, lo); + + for (i =3D 0; i < sizeof(vd_list); i++) { + int vd =3D vd_list[i]; + tcg_gen_addi_tl(EA, EA, -8); + tcg_gen_qemu_ld_i64(t8, EA, ctx->mem_idx, DEF_MEMOP(MO_64) | MO_AL= IGN); + tcg_gen_extr_i64_tl(cpu_gpr[VDR_PAIR_REG(vd)], cpu_gpr[vd], t8); + } + + tcg_gen_addi_tl(EA, EA, -8); + tcg_gen_qemu_ld_i64(t8, EA, ctx->mem_idx, DEF_MEMOP(MO_64) | MO_ALIGN); + tcg_gen_extr_i64_tl(lo, hi, t8); + tcg_gen_shri_tl(hi, hi, 28); + tcg_gen_trunc_tl_i32(cpu_crf[0], hi); + gen_store_spr(SPR_SPRG0, lo); + + tcg_gen_addi_tl(EA, base, 4); + tcg_gen_qemu_ld_tl(cpu_lr, EA, ctx->mem_idx, DEF_MEMOP(MO_32) | MO_ALI= GN); + tcg_gen_mov_tl(cpu_gpr[a->ra], base); + return true; +#endif +} + +static bool trans_LSKU(DisasContext *ctx, arg_LSKU *a) +{ +#if defined(TARGET_PPC64) + return false; +#else + int64_t n; + TCGv base, EA; + TCGv_i32 lo, hi; + TCGv_i64 t8; + + if (unlikely(!is_ppe(ctx))) { + return false; + } + + CHECK_PPE_LEVEL(ctx, PPC2_PPE42X); + CHECK_PPE_GPR(ctx, a->rt); + + if (unlikely((a->rt !=3D a->ra) || (a->ra =3D=3D 0) || + (a->si & PPC_BIT(0)) || (a->si =3D=3D 0))) { + gen_invalid(ctx); + return true; + } + + EA =3D tcg_temp_new(); + base =3D tcg_temp_new(); + gen_addr_register(ctx, base); + + + tcg_gen_addi_tl(base, base, a->si * 8); + gen_store_spr(SPR_PPE42_EDR, base); + + n =3D a->si - 1; + t8 =3D tcg_temp_new_i64(); + if (n > 0) { + tcg_gen_addi_tl(EA, base, -8); + tcg_gen_qemu_ld_i64(t8, EA, ctx->mem_idx, DEF_MEMOP(MO_64) | MO_AL= IGN); + hi =3D cpu_gpr[30]; + lo =3D cpu_gpr[31]; + tcg_gen_extr_i64_i32(lo, hi, t8); + } + if (n > 1) { + tcg_gen_addi_tl(EA, base, -16); + tcg_gen_qemu_ld_i64(t8, EA, ctx->mem_idx, DEF_MEMOP(MO_64) | MO_AL= IGN); + hi =3D cpu_gpr[28]; + lo =3D cpu_gpr[29]; + tcg_gen_extr_i64_i32(lo, hi, t8); + } + tcg_gen_addi_tl(EA, base, 4); + tcg_gen_qemu_ld_i32(cpu_lr, EA, ctx->mem_idx, DEF_MEMOP(MO_32) | MO_AL= IGN); + tcg_gen_mov_tl(cpu_gpr[a->ra], base); + return true; +#endif +} + +static bool trans_STCXU(DisasContext *ctx, arg_STCXU *a) +{ +#if defined(TARGET_PPC64) + return false; +#else + TCGv EA; + TCGv lo, hi; + TCGv_i64 t8; + int i; + const uint8_t vd_list[] =3D {9, 7, 5, 3, 0}; + + if (unlikely(!is_ppe(ctx))) { + return false; + } + + CHECK_PPE_LEVEL(ctx, PPC2_PPE42X); + CHECK_PPE_GPR(ctx, a->rt); + + if (unlikely((a->rt !=3D a->ra) || (a->ra =3D=3D 0) || !(a->si & PPC_B= IT(0)))) { + gen_invalid(ctx); + return true; + } + + EA =3D tcg_temp_new(); + tcg_gen_addi_tl(EA, cpu_gpr[a->ra], 4); + tcg_gen_qemu_st_i32(cpu_lr, EA, ctx->mem_idx, DEF_MEMOP(MO_32) | MO_AL= IGN); + + gen_store_spr(SPR_PPE42_EDR, cpu_gpr[a->ra]); + + t8 =3D tcg_temp_new_i64(); + + tcg_gen_concat_tl_i64(t8, cpu_gpr[31], cpu_gpr[30]); + tcg_gen_addi_tl(EA, cpu_gpr[a->ra], -8); + tcg_gen_qemu_st_i64(t8, EA, ctx->mem_idx, DEF_MEMOP(MO_64) | MO_ALIGN); + + tcg_gen_concat_tl_i64(t8, cpu_gpr[29], cpu_gpr[28]); + tcg_gen_addi_tl(EA, EA, -8); + tcg_gen_qemu_st_i64(t8, EA, ctx->mem_idx, DEF_MEMOP(MO_64) | MO_ALIGN); + + lo =3D tcg_temp_new(); + hi =3D tcg_temp_new(); + + gen_load_spr(hi, SPR_SRR0); + gen_load_spr(lo, SPR_SRR1); + tcg_gen_concat_tl_i64(t8, lo, hi); + tcg_gen_addi_tl(EA, EA, -8); + tcg_gen_qemu_st_i64(t8, EA, ctx->mem_idx, DEF_MEMOP(MO_64) | MO_ALIGN); + + gen_get_xer(ctx, hi); + tcg_gen_mov_tl(lo, cpu_ctr); + tcg_gen_concat_tl_i64(t8, lo, hi); + tcg_gen_addi_tl(EA, EA, -8); + tcg_gen_qemu_st_i64(t8, EA, ctx->mem_idx, DEF_MEMOP(MO_64) | MO_ALIGN); + + for (i =3D 0; i < sizeof(vd_list); i++) { + int vd =3D vd_list[i]; + tcg_gen_concat_tl_i64(t8, cpu_gpr[VDR_PAIR_REG(vd)], cpu_gpr[vd]); + tcg_gen_addi_tl(EA, EA, -8); + tcg_gen_qemu_st_i64(t8, EA, ctx->mem_idx, DEF_MEMOP(MO_64) | MO_AL= IGN); + } + + gen_load_spr(lo, SPR_SPRG0); + tcg_gen_extu_i32_tl(hi, cpu_crf[0]); + tcg_gen_shli_tl(hi, hi, 28); + tcg_gen_concat_tl_i64(t8, lo, hi); + tcg_gen_addi_tl(EA, EA, -8); + tcg_gen_qemu_st_i64(t8, EA, ctx->mem_idx, DEF_MEMOP(MO_64) | MO_ALIGN); + + tcg_gen_addi_tl(EA, cpu_gpr[a->ra], a->si * 8); + tcg_gen_qemu_st_i32(cpu_gpr[a->rt], EA, ctx->mem_idx, DEF_MEMOP(MO_32)= | + MO_ALIGN); + tcg_gen_mov_tl(cpu_gpr[a->ra], EA); + return true; +#endif +} + +static bool trans_STSKU(DisasContext *ctx, arg_STSKU *a) +{ +#if defined(TARGET_PPC64) + return false; +#else + int64_t n; + TCGv base, EA; + TCGv_i32 lo, hi; + TCGv_i64 t8; + + if (unlikely(!is_ppe(ctx))) { + return false; + } + + CHECK_PPE_LEVEL(ctx, PPC2_PPE42X); + CHECK_PPE_GPR(ctx, a->rt); + + if (unlikely((a->rt !=3D a->ra) || (a->ra =3D=3D 0) || !(a->si & PPC_B= IT(0)))) { + gen_invalid(ctx); + return true; + } + + EA =3D tcg_temp_new(); + base =3D tcg_temp_new(); + gen_addr_register(ctx, base); + tcg_gen_addi_tl(EA, base, 4); + tcg_gen_qemu_st_i32(cpu_lr, EA, ctx->mem_idx, DEF_MEMOP(MO_32) | MO_AL= IGN); + + gen_store_spr(SPR_PPE42_EDR, base); + + n =3D ~(a->si); + + t8 =3D tcg_temp_new_i64(); + if (n > 0) { + hi =3D cpu_gpr[30]; + lo =3D cpu_gpr[31]; + tcg_gen_concat_i32_i64(t8, lo, hi); + tcg_gen_addi_tl(EA, base, -8); + tcg_gen_qemu_st_i64(t8, EA, ctx->mem_idx, DEF_MEMOP(MO_64) | MO_AL= IGN); + } + if (n > 1) { + hi =3D cpu_gpr[28]; + lo =3D cpu_gpr[29]; + tcg_gen_concat_i32_i64(t8, lo, hi); + tcg_gen_addi_tl(EA, base, -16); + tcg_gen_qemu_st_i64(t8, EA, ctx->mem_idx, DEF_MEMOP(MO_64) | MO_AL= IGN); + } + + tcg_gen_addi_tl(EA, base, a->si * 8); + tcg_gen_qemu_st_i32(cpu_gpr[a->rt], EA, ctx->mem_idx, DEF_MEMOP(MO_32)= | + MO_ALIGN); + tcg_gen_mov_tl(cpu_gpr[a->ra], EA); + return true; +#endif +} + +static bool do_ppe_ldst(DisasContext *ctx, void *a, int rt, int ra, + int rb_or_si, bool update, bool store, bool indexe= d) +{ +#if defined(TARGET_PPC64) + return false; +#else + TCGv ea; + int rt_lo; + TCGv_i64 t8; + TCGv disp; + + /* Some PowerPC CPU's have a different meaning for this instruciton */ + if (unlikely(!is_ppe(ctx))) { + return false; + } + + CHECK_VDR(ctx, rt); + CHECK_PPE_GPR(ctx, ra); + if (indexed) { + CHECK_PPE_GPR(ctx, rb_or_si); + disp =3D cpu_gpr[rb_or_si]; + } else { + disp =3D tcg_constant_tl(rb_or_si); + } + rt_lo =3D VDR_PAIR_REG(rt); + if (update && (ra =3D=3D 0 || (!store && ((ra =3D=3D rt) || (ra =3D=3D= rt_lo))))) { + gen_invalid(ctx); + return true; + } + gen_set_access_type(ctx, ACCESS_INT); + + ea =3D do_ea_calc(ctx, ra, disp); + t8 =3D tcg_temp_new_i64(); + if (store) { + tcg_gen_concat_i32_i64(t8, cpu_gpr[rt_lo], cpu_gpr[rt]); + tcg_gen_qemu_st_i64(t8, ea, ctx->mem_idx, DEF_MEMOP(MO_64)); + } else { + tcg_gen_qemu_ld_i64(t8, ea, ctx->mem_idx, DEF_MEMOP(MO_64)); + tcg_gen_extr_i64_i32(cpu_gpr[rt_lo], cpu_gpr[rt], t8); + } + if (update) { + tcg_gen_mov_tl(cpu_gpr[ra], ea); + } + return true; +#endif +} + +TRANS(LVD, do_ppe_ldst, a->rt, a->ra, a->si, false, false, false) +TRANS(LVDU, do_ppe_ldst, a->rt, a->ra, a->si, true, false, false) +TRANS(LVDX, do_ppe_ldst, a->rt, a->ra, a->rb, false, false, true) +TRANS(STVD, do_ppe_ldst, a->rt, a->ra, a->si, false, true, false) +TRANS(STVDU, do_ppe_ldst, a->rt, a->ra, a->si, true, true, false) +TRANS(STVDX, do_ppe_ldst, a->rt, a->ra, a->rb, false, true, true) + + +#if !defined(TARGET_PPC64) +static bool do_fcb(DisasContext *ctx, TCGv ra_val, TCGv rb_val, int bix, + int32_t bdx, bool s, bool px, bool lk) +{ + TCGCond cond; + uint32_t mask; + TCGLabel *no_branch; + target_ulong dest; + + /* Update CR0 */ + gen_op_cmp32(ra_val, rb_val, s, 0); + + if (lk) { + gen_setlr(ctx, ctx->base.pc_next); + } + + + mask =3D PPC_BIT32(28 + bix); + cond =3D (px) ? TCG_COND_TSTEQ : TCG_COND_TSTNE; + no_branch =3D gen_new_label(); + dest =3D ctx->cia + bdx; + + /* Do the branch if CR0[bix] =3D=3D PX */ + tcg_gen_brcondi_i32(cond, cpu_crf[0], mask, no_branch); + gen_goto_tb(ctx, 0, dest); + gen_set_label(no_branch); + gen_goto_tb(ctx, 1, ctx->base.pc_next); + ctx->base.is_jmp =3D DISAS_NORETURN; + return true; +} +#endif + +static bool do_cmp_branch(DisasContext *ctx, arg_FCB_bix *a, bool s, + bool rb_is_gpr) +{ +#if defined(TARGET_PPC64) + return false; +#else + TCGv old_ra; + TCGv rb_val; + + if (unlikely(!is_ppe(ctx))) { + return false; + } + CHECK_PPE_GPR(ctx, a->ra); + if (rb_is_gpr) { + CHECK_PPE_GPR(ctx, a->rb); + rb_val =3D cpu_gpr[a->rb]; + } else { + rb_val =3D tcg_constant_tl(a->rb); + } + if (a->bix =3D=3D 3) { + old_ra =3D tcg_temp_new(); + tcg_gen_mov_tl(old_ra, cpu_gpr[a->ra]); + tcg_gen_sub_tl(cpu_gpr[a->ra], cpu_gpr[a->ra], rb_val); + return do_fcb(ctx, old_ra, rb_val, 2, + a->bdx, s, a->px, a->lk); + } else { + return do_fcb(ctx, cpu_gpr[a->ra], rb_val, a->bix, + a->bdx, s, a->px, a->lk); + } +#endif +} + +TRANS(CMPWBC, do_cmp_branch, true, true) +TRANS(CMPLWBC, do_cmp_branch, false, true) +TRANS(CMPWIBC, do_cmp_branch, true, false) + +static bool do_mask_branch(DisasContext *ctx, arg_FCB * a, bool invert, + bool update, bool rb_is_gpr) +{ +#if defined(TARGET_PPC64) + return false; +#else + TCGv r; + TCGv mask, shift; + + if (unlikely(!is_ppe(ctx))) { + return false; + } + CHECK_PPE_GPR(ctx, a->ra); + if (rb_is_gpr) { + CHECK_PPE_GPR(ctx, a->rb); + mask =3D tcg_temp_new(); + shift =3D tcg_temp_new(); + tcg_gen_andi_tl(shift, cpu_gpr[a->rb], 0x1f); + tcg_gen_shr_tl(mask, tcg_constant_tl(0x80000000), shift); + } else { + mask =3D tcg_constant_tl(PPC_BIT32(a->rb)); + } + if (invert) { + tcg_gen_not_tl(mask, mask); + } + + /* apply mask to ra */ + r =3D tcg_temp_new(); + tcg_gen_and_tl(r, cpu_gpr[a->ra], mask); + if (update) { + tcg_gen_mov_tl(cpu_gpr[a->ra], r); + } + return do_fcb(ctx, r, tcg_constant_tl(0), 2, + a->bdx, false, a->px, a->lk); +#endif +} + +TRANS(BNBWI, do_mask_branch, false, false, false) +TRANS(BNBW, do_mask_branch, false, false, true) +TRANS(CLRBWIBC, do_mask_branch, true, true, false) +TRANS(CLRBWBC, do_mask_branch, true, true, true) + +#if !defined(TARGET_PPC64) +static void gen_set_Rc0_i64(DisasContext *ctx, TCGv_i64 reg) +{ + TCGv_i64 t0 =3D tcg_temp_new_i64(); + TCGv_i64 t1 =3D tcg_temp_new_i64(); + TCGv_i32 t =3D tcg_temp_new_i32(); + + tcg_gen_movi_i64(t0, CRF_EQ); + tcg_gen_movi_i64(t1, CRF_LT); + tcg_gen_movcond_i64(TCG_COND_LT, t0, reg, tcg_constant_i64(0), t1, t0); + tcg_gen_movi_i64(t1, CRF_GT); + tcg_gen_movcond_i64(TCG_COND_GT, t0, reg, tcg_constant_i64(0), t1, t0); + tcg_gen_extrl_i64_i32(t, t0); + tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); + tcg_gen_or_i32(cpu_crf[0], cpu_crf[0], t); +} +#endif + +static bool do_shift64(DisasContext *ctx, arg_X_rc *a, bool left) +{ +#if defined(TARGET_PPC64) + return false; +#else + int rt_lo, ra_lo; + TCGv_i64 t0, t8; + + /* Check for PPE since opcode overlaps with CNTTZDM instruction */ + if (unlikely(!is_ppe(ctx))) { + return false; + } + CHECK_PPE_LEVEL(ctx, PPC2_PPE42X); + CHECK_VDR(ctx, a->rt); + CHECK_VDR(ctx, a->ra); + CHECK_PPE_GPR(ctx, a->rb); + rt_lo =3D VDR_PAIR_REG(a->rt); + ra_lo =3D VDR_PAIR_REG(a->ra); + t8 =3D tcg_temp_new_i64(); + + /* AND rt with a mask that is 0 when rb >=3D 0x40 */ + t0 =3D tcg_temp_new_i64(); + tcg_gen_extu_tl_i64(t0, cpu_gpr[a->rb]); + tcg_gen_shli_i64(t0, t0, 0x39); + tcg_gen_sari_i64(t0, t0, 0x3f); + + /* form 64bit value from two 32bit regs */ + tcg_gen_concat_tl_i64(t8, cpu_gpr[rt_lo], cpu_gpr[a->rt]); + + /* apply mask */ + tcg_gen_andc_i64(t8, t8, t0); + + /* do the shift */ + tcg_gen_extu_tl_i64(t0, cpu_gpr[a->rb]); + tcg_gen_andi_i64(t0, t0, 0x3f); + if (left) { + tcg_gen_shl_i64(t8, t8, t0); + } else { + tcg_gen_shr_i64(t8, t8, t0); + } + + /* split the 64bit word back into two 32bit regs */ + tcg_gen_extr_i64_tl(cpu_gpr[ra_lo], cpu_gpr[a->ra], t8); + + /* update CR0 if requested */ + if (unlikely(a->rc !=3D 0)) { + gen_set_Rc0_i64(ctx, t8); + } + return true; +#endif +} + +TRANS(SRVD, do_shift64, false) +TRANS(SLVD, do_shift64, true) + +static bool trans_DCBQ(DisasContext *ctx, arg_DCBQ * a) +{ +#if defined(TARGET_PPC64) + return false; +#else + if (unlikely(!is_ppe(ctx))) { + return false; + } + + CHECK_PPE_GPR(ctx, a->rt); + CHECK_PPE_GPR(ctx, a->ra); + CHECK_PPE_GPR(ctx, a->rb); + + /* No cache exists, so just set RT to 0 */ + tcg_gen_movi_tl(cpu_gpr[a->rt], 0); + return true; +#endif +} + +static bool trans_RLDIMI(DisasContext *ctx, arg_RLDIMI *a) +{ +#if defined(TARGET_PPC64) + return false; +#else + TCGv_i64 t_rs, t_ra; + int ra_lo, rs_lo; + uint32_t sh =3D a->sh; + uint32_t mb =3D a->mb; + uint32_t me =3D 63 - sh; + + if (unlikely(!is_ppe(ctx))) { + return false; + } + CHECK_PPE_LEVEL(ctx, PPC2_PPE42X); + CHECK_VDR(ctx, a->rs); + CHECK_VDR(ctx, a->ra); + + rs_lo =3D VDR_PAIR_REG(a->rs); + ra_lo =3D VDR_PAIR_REG(a->ra); + + t_rs =3D tcg_temp_new_i64(); + t_ra =3D tcg_temp_new_i64(); + + tcg_gen_concat_tl_i64(t_rs, cpu_gpr[rs_lo], cpu_gpr[a->rs]); + tcg_gen_concat_tl_i64(t_ra, cpu_gpr[ra_lo], cpu_gpr[a->ra]); + + if (mb <=3D me) { + tcg_gen_deposit_i64(t_ra, t_ra, t_rs, sh, me - mb + 1); + } else { + uint64_t mask =3D mask_u64(mb, me); + TCGv_i64 t1 =3D tcg_temp_new_i64(); + + tcg_gen_rotli_i64(t1, t_rs, sh); + tcg_gen_andi_i64(t1, t1, mask); + tcg_gen_andi_i64(t_ra, t_ra, ~mask); + tcg_gen_or_i64(t_ra, t_ra, t1); + } + + tcg_gen_extr_i64_tl(cpu_gpr[ra_lo], cpu_gpr[a->ra], t_ra); + + if (unlikely(a->rc !=3D 0)) { + gen_set_Rc0_i64(ctx, t_ra); + } + return true; +#endif +} + + +static bool gen_rldinm_i64(DisasContext *ctx, arg_MD *a, int mb, int me, i= nt sh) +{ +#if defined(TARGET_PPC64) + return false; +#else + int len =3D me - mb + 1; + int rsh =3D (64 - sh) & 63; + int ra_lo, rs_lo; + TCGv_i64 t8; + + if (unlikely(!is_ppe(ctx))) { + return false; + } + CHECK_PPE_LEVEL(ctx, PPC2_PPE42X); + CHECK_VDR(ctx, a->rs); + CHECK_VDR(ctx, a->ra); + + rs_lo =3D VDR_PAIR_REG(a->rs); + ra_lo =3D VDR_PAIR_REG(a->ra); + t8 =3D tcg_temp_new_i64(); + tcg_gen_concat_tl_i64(t8, cpu_gpr[rs_lo], cpu_gpr[a->rs]); + if (sh !=3D 0 && len > 0 && me =3D=3D (63 - sh)) { + tcg_gen_deposit_z_i64(t8, t8, sh, len); + } else if (me =3D=3D 63 && rsh + len <=3D 64) { + tcg_gen_extract_i64(t8, t8, rsh, len); + } else { + tcg_gen_rotli_i64(t8, t8, sh); + tcg_gen_andi_i64(t8, t8, mask_u64(mb, me)); + } + tcg_gen_extr_i64_tl(cpu_gpr[ra_lo], cpu_gpr[a->ra], t8); + if (unlikely(a->rc !=3D 0)) { + gen_set_Rc0_i64(ctx, t8); + } + return true; +#endif +} + +TRANS(RLDICL, gen_rldinm_i64, a->mb, 63, a->sh) +TRANS(RLDICR, gen_rldinm_i64, 0, a->mb, a->sh) + --=20 2.43.0 From nobody Wed Sep 10 01:55:30 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1757361814; cv=none; d=zohomail.com; s=zohoarc; b=hrA93lbefO8rM0kp5g0diFXL4bVxJryhmwTrpSztfaoIrWY3RPErfiCKhGhhmmOLUFEF+npZO6n6TGLCdJnXOumRHITntQp6WBhxvLmqrXVyL4f1DthOemrkjH2p59xMfR/1S92v+u2V2lc5Coh9aLfJZCWBk++6B5gGZq+83Gc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1757361814; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=tmyZneTUF01bRMoizCXwTR1Q6ib4smTEY2hiDRpjS3Y=; b=YouKCZPRco8PcP0ldjELcBh0JCsuxIMxENwXA21S5m8GwUbgRuEUoY8JyFusGe35H15TcmSht6BqDQZFQPrDASoQpeD3VSDhgscAbf1SQ8+nD+V7TBepEKKxDla4cE8pnQmigxIm0raZo4VacMUBSK7/nsXKoPoSYL7bJJnG/bk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1757361814926595.6293810087813; Mon, 8 Sep 2025 13:03:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uvi3j-0001sz-KC; Mon, 08 Sep 2025 16:01:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uvi3h-0001s8-Gh; Mon, 08 Sep 2025 16:01:49 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uvi3d-0006x5-W7; Mon, 08 Sep 2025 16:01:49 -0400 Received: from pps.filterd (m0360083.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 588ISPuG004056; Mon, 8 Sep 2025 20:01:41 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 490cff3q18-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 20:01:41 +0000 (GMT) Received: from m0360083.ppops.net (m0360083.ppops.net [127.0.0.1]) by pps.reinject (8.18.1.12/8.18.0.8) with ESMTP id 588K1flC004735; Mon, 8 Sep 2025 20:01:41 GMT Received: from ppma21.wdc07v.mail.ibm.com (5b.69.3da9.ip4.static.sl-reverse.com [169.61.105.91]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 490cff3q12-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 20:01:40 +0000 (GMT) Received: from pps.filterd (ppma21.wdc07v.mail.ibm.com [127.0.0.1]) by ppma21.wdc07v.mail.ibm.com (8.18.1.2/8.18.1.2) with ESMTP id 588GfmHi007965; Mon, 8 Sep 2025 20:01:39 GMT Received: from smtprelay03.dal12v.mail.ibm.com ([172.16.1.5]) by ppma21.wdc07v.mail.ibm.com (PPS) with ESMTPS id 49109pfqub-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 20:01:39 +0000 Received: from smtpav02.wdc07v.mail.ibm.com (smtpav02.wdc07v.mail.ibm.com [10.39.53.229]) by smtprelay03.dal12v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 588K1cYZ16122512 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 8 Sep 2025 20:01:38 GMT Received: from smtpav02.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 30CCD58058; Mon, 8 Sep 2025 20:01:38 +0000 (GMT) Received: from smtpav02.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 62BED5805C; Mon, 8 Sep 2025 20:01:37 +0000 (GMT) Received: from mglenn-KVM.. (unknown [9.10.239.198]) by smtpav02.wdc07v.mail.ibm.com (Postfix) with ESMTP; Mon, 8 Sep 2025 20:01:37 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=tmyZneTUF01bRMoiz CXwTR1Q6ib4smTEY2hiDRpjS3Y=; b=DpPyGP6kWLkZkSUCvnV1zl14z4VxZBl8X F8DReoiff+WQC3xdxm4IDgZJ5b4qUdNyyplHl+TZt+T1iPWO6HYF5oAcABhlP6xb a+nKEUvPpAlA99OsIFykJBC5fZSnrSxVz52Q89JZzhWoZxM8y+jnJV3MOxVo40dU SJRgsRmQQZp/9DTVxVJoP21/y4+UHrJ19WlU6n6Wc1Je4E43WJp/ce8EcN2+3Oe6 dUJ52hc4NJWWVFoYY+D9p0iJsKH44Hmulh4KSqviNLU+YrbK5RDh8K7s1pXZ+KO1 wprfH+sZEtSnZ5CXyUA2TUk78cOvQPTKpXiw/uGLGWQKMQR/S7saA== From: Glenn Miles To: qemu-devel@nongnu.org Cc: Glenn Miles , qemu-ppc@nongnu.org, clg@redhat.com, npiggin@gmail.com, harshpb@linux.ibm.com, thuth@redhat.com, rathc@linux.ibm.com, richard.henderson@linaro.org Subject: [PATCH v3 7/9] hw/ppc: Support for an IBM PPE42 CPU decrementer Date: Mon, 8 Sep 2025 15:00:17 -0500 Message-ID: <20250908200028.115789-8-milesg@linux.ibm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250908200028.115789-1-milesg@linux.ibm.com> References: <20250908200028.115789-1-milesg@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: zBPogh2rYBJMOfIcLfi71-TmqE8ELoTj X-Proofpoint-GUID: mA_GSaG2lUIsKPjga7YSBmU0ZUL9tonx X-Authority-Analysis: v=2.4 cv=EYDIQOmC c=1 sm=1 tr=0 ts=68bf3625 cx=c_pps a=GFwsV6G8L6GxiO2Y/PsHdQ==:117 a=GFwsV6G8L6GxiO2Y/PsHdQ==:17 a=yJojWOMRYYMA:10 a=VnNF1IyMAAAA:8 a=FSmKNcNrx3yT2pM3_rYA:9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDAyMCBTYWx0ZWRfX/1Bnp1piotLG ILvqbl3Z4XirnOhFr/7dIoWHZ7Nw1i/9bU1zWu2TE2Dgr53sFp3k4PninPPJaGMzyR/ZCql10cW K2tZObIb2AIwqpQIIBbUJGH33hyjv7k7DcFuwT8OUt0iUvm0VVvXAFvKqNkWnC16pOB2W8YrEvc wEy/25v3kXFijFX1RmwcQSQE+HL6k4jg9xQNr59x3f9APkqtCmFbEAKFRMoYSb+mMyHvPtb2Wcf rhilfFG67O2nucgQgd+FJEXpd7bMD55+A+/j7b8a4eAk86J7xAajQAtw7rPb7jhxO17k3bWZQp6 yKfHQhE84bJ97kmNZCX1DwMiSaCN6maiMOGJtRVKDvAIah9301Q3qBwRpqp8ZbSJmQoe7vclSQw MbKk0u7l X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-08_06,2025-09-08_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 suspectscore=0 spamscore=0 impostorscore=0 priorityscore=1501 phishscore=0 clxscore=1015 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060020 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=milesg@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1757361817562124100 Content-Type: text/plain; charset="utf-8" The IBM PPE42 processors support a 32-bit decrementer that can raise an external interrupt when DEC[0] transitions from a 0 to a 1 (a non-negative value to a negative value). It also continues decrementing even after this condition is met. The BookE timer is slightly different in that it raises an interrupt when the DEC value reaches 0 and stops decrementing at that point. Support a PPE42 version of the BookE timer by adding a new PPC_TIMER_PPE flag that has the timer code look for the transition from a non-negative value to a negative value and allows the value to continue decrementing. Signed-off-by: Glenn Miles --- Changes from v2: - Split out PPE42 decrementer support from v2 patch 3 hw/ppc/ppc_booke.c | 7 ++++++- include/hw/ppc/ppc.h | 1 + 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/ppc/ppc_booke.c b/hw/ppc/ppc_booke.c index 3872ae2822..13403a56b1 100644 --- a/hw/ppc/ppc_booke.c +++ b/hw/ppc/ppc_booke.c @@ -352,7 +352,12 @@ void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t f= req, uint32_t flags) booke_timer =3D g_new0(booke_timer_t, 1); =20 cpu->env.tb_env =3D tb_env; - tb_env->flags =3D flags | PPC_TIMER_BOOKE | PPC_DECR_ZERO_TRIGGERED; + if (flags & PPC_TIMER_PPE) { + /* PPE's use a modified version of the booke behavior */ + tb_env->flags =3D flags | PPC_DECR_UNDERFLOW_TRIGGERED; + } else { + tb_env->flags =3D flags | PPC_TIMER_BOOKE | PPC_DECR_ZERO_TRIGGERE= D; + } =20 tb_env->tb_freq =3D freq; tb_env->decr_freq =3D freq; diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h index 8a14d623f8..cb51d704c6 100644 --- a/include/hw/ppc/ppc.h +++ b/include/hw/ppc/ppc.h @@ -52,6 +52,7 @@ struct ppc_tb_t { #define PPC_DECR_UNDERFLOW_LEVEL (1 << 4) /* Decr interrupt active when * the most significant bit = is 1. */ +#define PPC_TIMER_PPE (1 << 5) /* Enable PPE support */ =20 uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offse= t); void cpu_ppc_tb_init(CPUPPCState *env, uint32_t freq); --=20 2.43.0 From nobody Wed Sep 10 01:55:30 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1757361906; cv=none; d=zohomail.com; s=zohoarc; b=nFL4xmfcgDhzDoeR9SI7sGCWvVEjJaoTn6YS0PBYdFssQF56h56AKuiV1h3KO/VBI4DXe3Z/77d2m4Y/OAj+dBdLtSJw9fviuZRex5YJfW7GUEWfUt9cbmnqwY8SwC8A0DGkj9UQ9txe1n/iXiPr3IQ9CWsyWYIYkEFl2cgWYlk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1757361906; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=fZOZoxg7igdwogfpAglTMT6Shj0FQyUQiuiOwaA1oeQ=; b=D390xe56E+OkiVYoS8q/PJTl/C2Z4F3Y0QRIoOmn82LffLTyvqR2kAlhXAG3NJgsm2EyrZO+vZTdDp/gnYaIB1EJDY2qOKfmF8o36AHyBAZiM1qvCtKYFFQJaoa0VnguaRxzrXBCGFzDYYOwzazNz4ArDPRD9UmcLFjhxyO8b5o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1757361906762441.5782439194079; Mon, 8 Sep 2025 13:05:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uvi3m-0001uA-JG; Mon, 08 Sep 2025 16:01:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uvi3j-0001sS-8P; Mon, 08 Sep 2025 16:01:51 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uvi3g-0006yK-5X; Mon, 08 Sep 2025 16:01:50 -0400 Received: from pps.filterd (m0360083.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 588JcIUU015555; Mon, 8 Sep 2025 20:01:45 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 490cff3q1x-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 20:01:44 +0000 (GMT) Received: from m0360083.ppops.net (m0360083.ppops.net [127.0.0.1]) by pps.reinject (8.18.1.12/8.18.0.8) with ESMTP id 588K1iMS004848; Mon, 8 Sep 2025 20:01:44 GMT Received: from ppma11.dal12v.mail.ibm.com (db.9e.1632.ip4.static.sl-reverse.com [50.22.158.219]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 490cff3q1r-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 20:01:44 +0000 (GMT) Received: from pps.filterd (ppma11.dal12v.mail.ibm.com [127.0.0.1]) by ppma11.dal12v.mail.ibm.com (8.18.1.2/8.18.1.2) with ESMTP id 588IJJok001156; Mon, 8 Sep 2025 20:01:43 GMT Received: from smtprelay07.dal12v.mail.ibm.com ([172.16.1.9]) by ppma11.dal12v.mail.ibm.com (PPS) with ESMTPS id 4912037e1q-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 20:01:43 +0000 Received: from smtpav02.wdc07v.mail.ibm.com (smtpav02.wdc07v.mail.ibm.com [10.39.53.229]) by smtprelay07.dal12v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 588K1g8A9176504 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 8 Sep 2025 20:01:42 GMT Received: from smtpav02.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5AE0058058; Mon, 8 Sep 2025 20:01:42 +0000 (GMT) Received: from smtpav02.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8D5E358059; Mon, 8 Sep 2025 20:01:41 +0000 (GMT) Received: from mglenn-KVM.. (unknown [9.10.239.198]) by smtpav02.wdc07v.mail.ibm.com (Postfix) with ESMTP; Mon, 8 Sep 2025 20:01:41 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pp1; bh=fZOZox g7igdwogfpAglTMT6Shj0FQyUQiuiOwaA1oeQ=; b=syWnllZX4qBj3J4NgcJwxl NDubR5QdwFNarFX62Elg1nl2nAx9CHknk5IgETzSi8IQQ0hemtO/zkRpgRGRsrHU /1NDzPQTlzwIwKelPJoQaP9t6gY3d/uLXlpnX63TfXnzvQwSSA3WTJFtk+02heXZ WYJRBfovDQ2Tm+eB4axtTMotakOr7GEj1cKPnHMV6QCmUISPFI9G6mWh57T2r2Cj XpbHlmLIfhF69ZjWic0wuWmMbF8jQF0vnGdM235QZaHAlyPRLxXDDBcYukWCNPSL zXrAE+uFDAAw8VCZCiRublz9jHQ+8bBxs/0xHuOnFMD9jDkPn5SIrT3fkaSTAWlg == From: Glenn Miles To: qemu-devel@nongnu.org Cc: Glenn Miles , qemu-ppc@nongnu.org, clg@redhat.com, npiggin@gmail.com, harshpb@linux.ibm.com, thuth@redhat.com, rathc@linux.ibm.com, richard.henderson@linaro.org Subject: [PATCH v3 8/9] hw/ppc: Add a test machine for the IBM PPE42 CPU Date: Mon, 8 Sep 2025 15:00:18 -0500 Message-ID: <20250908200028.115789-9-milesg@linux.ibm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250908200028.115789-1-milesg@linux.ibm.com> References: <20250908200028.115789-1-milesg@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: Ut1b7i_PhXw9d04VjZ03XIOnR7_3vMss X-Proofpoint-GUID: 0QyPqm9jp2HSoTSoftALthXVvo4ZIssi X-Authority-Analysis: v=2.4 cv=EYDIQOmC c=1 sm=1 tr=0 ts=68bf3629 cx=c_pps a=aDMHemPKRhS1OARIsFnwRA==:117 a=aDMHemPKRhS1OARIsFnwRA==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=VnNF1IyMAAAA:8 a=69wJf7TsAAAA:8 a=up-X0YpDAAAA:8 a=eFQqLMc9Qz5AkApmWogA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=Fg1AiH1G6rFz08G2ETeA:22 a=86FmjZgct7XXK6GGpxvI:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDAyMCBTYWx0ZWRfX51j1wj/h8t00 a1EjPi/WYlh7rpHhd5lbfcX26KerWkaExFYYMbFtwhB0LXfIDhlrnoNpPGOOY57LKACR0ZJCeER 7JCMwPPnBFQeI8aTygF+djLjOVnQRapJ8ss4y6TJJXIHR4v93pLkVTSoKXq/C6Iqkfvyf5maYJm 85dwCNxscbC6vO14Ii2e3b2KgSgUexMR0k2aMhhg26JzJXF+a0tPNOmcLJAzIkZP0b8DYvvIEZ4 YJsluVwcEkNjXCvcmQwRGB7Hswy9zrRdB7UXV0EOV3BJJGBS58K+bPnJXddHvvb4qPZg7Qu/NEe pJQzBHEMXCC0AHMMAE6vW1H/uvpMH0/kjQLVW6+an2gbJVB5MpIbpkrg/9TeqEcvWSX5gIY2E/c S515R+sU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-08_06,2025-09-08_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 suspectscore=0 spamscore=0 impostorscore=0 priorityscore=1501 phishscore=0 clxscore=1015 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060020 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=milesg@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1757361908017116600 Adds a test machine for the IBM PPE42 processor, including a DEC, FIT, WDT and 512 KiB of ram. The purpose of this machine is only to provide a generic platform for testing instructions of the recently added PPE42 processor model which is used extensively in the IBM Power9, Power10 and future Power server processors. Signed-off-by: Glenn Miles --- Changes from v2: - Moved decrementer changes to distinct commit - Introduced a specific MachineState for the ppe42 Machine - Use qdev_realize to create the machine - Use valid_cpu_types to determine validity of CPU - Changed machine ram limit from 2GB to 512KB MAINTAINERS | 6 +++ hw/ppc/Kconfig | 9 ++++ hw/ppc/meson.build | 2 + hw/ppc/ppe42_machine.c | 102 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 119 insertions(+) create mode 100644 hw/ppc/ppe42_machine.c diff --git a/MAINTAINERS b/MAINTAINERS index a07086ed76..52fa303e0a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1531,6 +1531,12 @@ F: include/hw/pci-host/grackle.h F: pc-bios/qemu_vga.ndrv F: tests/functional/test_ppc_mac.py =20 +PPE42 +M: Glenn Miles +L: qemu-ppc@nongnu.org +S: Odd Fixes +F: hw/ppc/ppe42_machine.c + PReP M: Herv=C3=A9 Poussineau L: qemu-ppc@nongnu.org diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig index ced6bbc740..3fdea5919c 100644 --- a/hw/ppc/Kconfig +++ b/hw/ppc/Kconfig @@ -44,6 +44,15 @@ config POWERNV select SSI_M25P80 select PNV_SPI =20 +config PPC405 + bool + default y + depends on PPC + select M48T59 + select PFLASH_CFI02 + select PPC4XX + select SERIAL + config PPC440 bool default y diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build index 9893f8adeb..170b90ae7d 100644 --- a/hw/ppc/meson.build +++ b/hw/ppc/meson.build @@ -57,6 +57,8 @@ ppc_ss.add(when: 'CONFIG_POWERNV', if_true: files( 'pnv_n1_chiplet.c', )) # PowerPC 4xx boards +ppc_ss.add(when: 'CONFIG_PPC405', if_true: files( + 'ppe42_machine.c')) ppc_ss.add(when: 'CONFIG_PPC440', if_true: files( 'ppc440_bamboo.c', 'ppc440_uc.c')) diff --git a/hw/ppc/ppe42_machine.c b/hw/ppc/ppe42_machine.c new file mode 100644 index 0000000000..2cfce2503f --- /dev/null +++ b/hw/ppc/ppe42_machine.c @@ -0,0 +1,102 @@ +/* + * Test Machine for the IBM PPE42 processor + * + * Copyright (c) 2025, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "qemu/error-report.h" +#include "system/address-spaces.h" +#include "hw/boards.h" +#include "hw/ppc/ppc.h" +#include "system/system.h" +#include "system/reset.h" +#include "system/kvm.h" +#include "qapi/error.h" + +#define TYPE_PPE42_MACHINE MACHINE_TYPE_NAME("ppe42_machine") +typedef MachineClass Ppe42MachineClass; +typedef struct Ppe42MachineState Ppe42MachineState; +DECLARE_OBJ_CHECKERS(Ppe42MachineState, Ppe42MachineClass, + PPE42_MACHINE, TYPE_PPE42_MACHINE) + +struct Ppe42MachineState { + MachineState parent_obj; + + PowerPCCPU cpu; +}; + +static void main_cpu_reset(void *opaque) +{ + PowerPCCPU *cpu =3D opaque; + + cpu_reset(CPU(cpu)); +} + +static void ppe42_machine_init(MachineState *machine) +{ + Ppe42MachineState *pms =3D PPE42_MACHINE(machine); + PowerPCCPU *cpu =3D &pms->cpu; + + if (kvm_enabled()) { + error_report("machine %s does not support the KVM accelerator", + MACHINE_GET_CLASS(machine)->name); + exit(EXIT_FAILURE); + } + + /* init CPU */ + object_initialize_child(OBJECT(pms), "cpu", cpu, machine->cpu_type); + if (!qdev_realize(DEVICE(cpu), NULL, &error_fatal)) { + return; + } + + qemu_register_reset(main_cpu_reset, cpu); + + /* This sets the decrementer timebase */ + ppc_booke_timers_init(cpu, 37500000, PPC_TIMER_PPE); + + /* RAM */ + if (machine->ram_size > 512 * KiB) { + error_report("RAM size more than 512 KiB is not supported"); + exit(1); + } + memory_region_add_subregion(get_system_memory(), 0xfff80000, machine->= ram); +} + + +static void ppe42_machine_class_init(ObjectClass *oc, const void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + static const char * const valid_cpu_types[] =3D { + POWERPC_CPU_TYPE_NAME("PPE42"), + POWERPC_CPU_TYPE_NAME("PPE42X"), + POWERPC_CPU_TYPE_NAME("PPE42XM"), + NULL, + }; + + mc->desc =3D "PPE42 Test Machine"; + mc->init =3D ppe42_machine_init; + mc->default_cpu_type =3D POWERPC_CPU_TYPE_NAME("PPE42XM"); + mc->valid_cpu_types =3D valid_cpu_types; + mc->default_ram_id =3D "ram"; + mc->default_ram_size =3D 512 * KiB; +} + +static const TypeInfo ppe42_machine_info =3D { + .name =3D TYPE_PPE42_MACHINE, + .parent =3D TYPE_MACHINE, + .instance_size =3D sizeof(Ppe42MachineState), + .class_init =3D ppe42_machine_class_init, + .class_size =3D sizeof(Ppe42MachineClass), +}; + +static void ppe42_machine_register_types(void) +{ + type_register_static(&ppe42_machine_info); +} + +type_init(ppe42_machine_register_types); + --=20 2.43.0 From nobody Wed Sep 10 01:55:30 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1757361859; cv=none; d=zohomail.com; s=zohoarc; b=lKMIsj1nlgEWBIBv3hQVT/84M0KnKutsRAd22eMpu/MpUSMPL947a6oULt4xHYtATbSgCocz+C2/VW5T4kmHQiiVkKhbULKCym9RYV9ANTITgXXt7C3/M8lIZ4zOnyC1cYSvUVarUZt5ilBaDyyoJvdxn9+4gcPTehQJeSA+Sjo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1757361859; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=51ZrNQuMDWHdTvuk8/+E6TuIjpvWDFA3qstEJOBXSNg=; b=Guq70oDuUpj8pfzO+rh7eMG+sH/akEnjtZmT4TXhujnpnDZAWrEY0wJ5HW+e48xILZ3ikkYJcSbw6q2fVt87UMh6RjMkvUiysvKDRQqdoKA9IkfLu+vsFjNtc7M4xNNktFzJ4JPFqBZJMStNiMvZ/Uro1J7LSRIbuOADMpm/G4c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1757361859709561.0364592433202; Mon, 8 Sep 2025 13:04:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uvi4A-0001xu-LT; Mon, 08 Sep 2025 16:02:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uvi3p-0001uh-UJ; Mon, 08 Sep 2025 16:01:58 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uvi3l-0006zX-7Z; Mon, 08 Sep 2025 16:01:57 -0400 Received: from pps.filterd (m0360083.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 588J5vLA030018; Mon, 8 Sep 2025 20:01:49 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 490cff3q2k-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 20:01:49 +0000 (GMT) Received: from m0360083.ppops.net (m0360083.ppops.net [127.0.0.1]) by pps.reinject (8.18.1.12/8.18.0.8) with ESMTP id 588Jx9PG000586; Mon, 8 Sep 2025 20:01:48 GMT Received: from ppma22.wdc07v.mail.ibm.com (5c.69.3da9.ip4.static.sl-reverse.com [169.61.105.92]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 490cff3q2f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 20:01:48 +0000 (GMT) Received: from pps.filterd (ppma22.wdc07v.mail.ibm.com [127.0.0.1]) by ppma22.wdc07v.mail.ibm.com (8.18.1.2/8.18.1.2) with ESMTP id 588G4htX020458; Mon, 8 Sep 2025 20:01:47 GMT Received: from smtprelay04.wdc07v.mail.ibm.com ([172.16.1.71]) by ppma22.wdc07v.mail.ibm.com (PPS) with ESMTPS id 490yp0qv0f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 20:01:47 +0000 Received: from smtpav02.wdc07v.mail.ibm.com (smtpav02.wdc07v.mail.ibm.com [10.39.53.229]) by smtprelay04.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 588K1kSR60621084 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 8 Sep 2025 20:01:46 GMT Received: from smtpav02.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 475CC5805C; Mon, 8 Sep 2025 20:01:46 +0000 (GMT) Received: from smtpav02.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 787A45805B; Mon, 8 Sep 2025 20:01:45 +0000 (GMT) Received: from mglenn-KVM.. (unknown [9.10.239.198]) by smtpav02.wdc07v.mail.ibm.com (Postfix) with ESMTP; Mon, 8 Sep 2025 20:01:45 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pp1; bh=51ZrNQ uMDWHdTvuk8/+E6TuIjpvWDFA3qstEJOBXSNg=; b=Yki88j1neleY197/5SBg5n SO3kVdMBXkJvFsBAFYPSiUWs5zmbrLDiSXsL5ITNXDk2suWdA9edtG+G1DI29dML 24hp1ungDOWWEfacqtfFYF9hOvgx40D1kRddEsPMQTSFvDZIdno5rKHpi1wDBxRj 2EPY1+yNnuGwl3QioIlTpL9c/tDtE72WQPBl1k6QUEynyF/duX0jqjxGZPX7S4LC uSnPyA++/G29rpXeQRxfp+1eUXZXsJl+UmS9qdDcP9tSpjmpkSlROYmsQJpHD10p Udp2D7ZBm0g80v+OCOBW18sMo997jbAg19isH3xndY63T+3RfgRyJYscWkc3x53w == From: Glenn Miles To: qemu-devel@nongnu.org Cc: Glenn Miles , qemu-ppc@nongnu.org, clg@redhat.com, npiggin@gmail.com, harshpb@linux.ibm.com, thuth@redhat.com, rathc@linux.ibm.com, richard.henderson@linaro.org Subject: [PATCH v3 9/9] tests/functional: Add test for IBM PPE42 instructions Date: Mon, 8 Sep 2025 15:00:19 -0500 Message-ID: <20250908200028.115789-10-milesg@linux.ibm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250908200028.115789-1-milesg@linux.ibm.com> References: <20250908200028.115789-1-milesg@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: EsCbkImBWDjgTtXbr3qlxjtklrPl4mmD X-Proofpoint-GUID: 2IBoCLmDbkicYToLjf7tnMDC4vfo2lzV X-Authority-Analysis: v=2.4 cv=EYDIQOmC c=1 sm=1 tr=0 ts=68bf362d cx=c_pps a=5BHTudwdYE3Te8bg5FgnPg==:117 a=5BHTudwdYE3Te8bg5FgnPg==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=NEAV23lmAAAA:8 a=VnNF1IyMAAAA:8 a=20KFwNOVAAAA:8 a=69wJf7TsAAAA:8 a=up-X0YpDAAAA:8 a=WP5zsaevAAAA:8 a=NUakdCcs51WeiAtREWwA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=Fg1AiH1G6rFz08G2ETeA:22 a=86FmjZgct7XXK6GGpxvI:22 a=t8Kx07QrZZTALmIZmm-o:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDAyMCBTYWx0ZWRfX6qNkw1qJJK4I aCduqnkE7p0Hp+fQeQZEvNV+rixSDPMMlgwcFHM5bAJne6J0EJ72ARQpHFC/+y+nLwFBCbZ6U/o HjwyMmj/StfFjvyN0tT6KYeWI+CJtGIO+5cWueVw8XAQfSKXfw4lVXpz19YvUM1BOymdxf+sF0j l6hHzGYikKjypqA1w0+u+smalBYP9hcOfFavH7LItqj4e8SSYfopQWx4Gtno3IWc2Ne6U1YN519 mpALcBlADvnuRBdLW8uOW38n4RGgAyJkLTwdpDzgIVpeSBsmLBdKkOLXEuVzvtjVfs945qsEF2O Yf5PN9cuOwkH4GaAC4w+35M5qLcwunIZeIhnrIcfiuxTN/b1nhxIzrx9jffyD08EalpPk0NxJ8/ OY8kPT0d X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-08_06,2025-09-08_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 suspectscore=0 spamscore=0 impostorscore=0 priorityscore=1501 phishscore=0 clxscore=1015 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060020 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=milesg@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1757361861455116600 Adds a functional test for the IBM PPE42 instructions which downloads a test image from a public github repo and then loads and executes the image. (see https://github.com/milesg-github/ppe42-tests for details) Test status is checked by periodically issuing 'info register' commands and checking the NIP value. If the NIP is 0xFFF80200 then the test successfully executed to completion. If the machine stops before the test completes or if a 90 second timeout is reached, then the test is marked as having failed. This test does not test any PowerPC instructions as it is expected that these instructions are well covered in other tests. Only instructions that are unique to the IBM PPE42 processor are tested. Signed-off-by: Glenn Miles Reviewed-by: Thomas Huth --- No changes from v2 patch 4 MAINTAINERS | 1 + tests/functional/meson.build | 1 + tests/functional/test_ppc_ppe42.py | 79 ++++++++++++++++++++++++++++++ 3 files changed, 81 insertions(+) create mode 100644 tests/functional/test_ppc_ppe42.py diff --git a/MAINTAINERS b/MAINTAINERS index 52fa303e0a..af412ad0ce 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1536,6 +1536,7 @@ M: Glenn Miles L: qemu-ppc@nongnu.org S: Odd Fixes F: hw/ppc/ppe42_machine.c +F: tests/functional/test_ppc_ppe42.py =20 PReP M: Herv=C3=A9 Poussineau diff --git a/tests/functional/meson.build b/tests/functional/meson.build index 311c6f1806..ddfef55bd2 100644 --- a/tests/functional/meson.build +++ b/tests/functional/meson.build @@ -233,6 +233,7 @@ tests_ppc_system_quick =3D [ ] =20 tests_ppc_system_thorough =3D [ + 'ppc_ppe42', 'ppc_40p', 'ppc_amiga', 'ppc_bamboo', diff --git a/tests/functional/test_ppc_ppe42.py b/tests/functional/test_ppc= _ppe42.py new file mode 100644 index 0000000000..26bbe11b2d --- /dev/null +++ b/tests/functional/test_ppc_ppe42.py @@ -0,0 +1,79 @@ +#!/usr/bin/env python3 +# +# Functional tests for the IBM PPE42 processor +# +# Copyright (c) 2025, IBM Corporation +# +# SPDX-License-Identifier: GPL-2.0-or-later + +from qemu_test import QemuSystemTest, Asset +import asyncio + +class Ppe42Machine(QemuSystemTest): + + timeout =3D 90 + poll_period =3D 1.0 + + ASSET_PPE42_TEST_IMAGE =3D Asset( + ('https://github.com/milesg-github/ppe42-tests/raw/refs/heads/main= /' + 'images/ppe42-test.out'), + '03c1ac0fb7f6c025102a02776a93b35101dae7c14b75e4eab36a337e39042ea8') + + def _test_completed(self): + self.log.info("Checking for test completion...") + try: + output =3D self.vm.cmd('human-monitor-command', + command_line=3D'info registers') + except Exception as err: + self.log.debug(f"'info registers' cmd failed due to {err=3D}," + " {type(err)=3D}") + raise + + self.log.info(output) + if "NIP fff80200" in output: + self.log.info("") + return True + else: + self.log.info("") + return False + + def _wait_pass_fail(self, timeout): + while not self._test_completed(): + if timeout >=3D self.poll_period: + timeout =3D timeout - self.poll_period + self.log.info(f"Waiting {self.poll_period} seconds for tes= t" + " to complete...") + e =3D None + try: + e =3D self.vm.event_wait('STOP', self.poll_period) + + except asyncio.TimeoutError: + self.log.info("Poll period ended.") + pass + + except Exception as err: + self.log.debug(f"event_wait() failed due to {err=3D}," + " {type(err)=3D}") + raise + + if e !=3D None: + self.log.debug(f"Execution stopped: {e}") + self.log.debug("Exiting due to test failure") + self.fail("Failure detected!") + break + else: + self.fail("Timed out waiting for test completion.") + + def test_ppe42_instructions(self): + self.set_machine('ppe42_machine') + self.require_accelerator("tcg") + image_path =3D self.ASSET_PPE42_TEST_IMAGE.fetch() + self.vm.add_args('-nographic') + self.vm.add_args('-device', f'loader,file=3D{image_path}') + self.vm.add_args('-device', 'loader,addr=3D0xfff80040,cpu-num=3D0') + self.vm.add_args('-action', 'panic=3Dpause') + self.vm.launch() + self._wait_pass_fail(self.timeout) + +if __name__ =3D=3D '__main__': + QemuSystemTest.main() --=20 2.43.0