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Mon, 08 Sep 2025 11:28:37 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG0tXNFx/lYlzA94gjiwydyD5BAk071KUchH4SJmXhdh+jUXu3XSmD3OX4wbFdpN4TydNnuZQ== X-Received: by 2002:a17:90b:48cc:b0:32b:d79e:58ac with SMTP id 98e67ed59e1d1-32d43f70faemr11329197a91.31.1757356116862; Mon, 08 Sep 2025 11:28:36 -0700 (PDT) From: Vacha Bhavsar To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , Thomas Huth , Vacha Bhavsar Subject: [PATCH v7 1/3] target/arm: Increase MAX_PACKET_LENGTH for SME ZA remote gdb debugging Date: Mon, 8 Sep 2025 18:28:32 +0000 Message-Id: <20250908182834.2476277-2-vacha.bhavsar@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908182834.2476277-1-vacha.bhavsar@oss.qualcomm.com> References: <20250908182834.2476277-1-vacha.bhavsar@oss.qualcomm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=Yv8PR5YX c=1 sm=1 tr=0 ts=68bf2057 cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=yJojWOMRYYMA:10 a=CCpqsmhAAAAA:8 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=XJBTR8SIO4LSYOdVysIA:9 a=_Vgx9l1VpLgwpw_dHYaR:22 a=ul9cdbp4aOFLsgKbc677:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: WEoxvGcAU1vsK2wa-JBGA6BRe6-ODnM6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDAxOCBTYWx0ZWRfXwR1GDdeo8l7+ aOcHfFYgkbBfasc7w3uRjyF+/re6xkHNYEQ0UW3MlYiSVEtELd0zptg+1eh3AAIz9AyFW+FDzhT sNvKBJfNaURdh81yj9dNX2OrhSlHI3yCLYSOqFuBncaiB/mJUelvY///5x3himkS+yH/oAXbqBt Q2mn1OVT1cYmBFVVF9lmT0xLGqR2qNhtF/cA6ypfKwcb9Gum2qLJ4A8x9mHbbuAb7QtKrbvDjcu P9Jcio7EOrqno0u3nK+BI15rpFL18btNf14nqJBiA5o6hcQcMQA5h4oLVcgHDg/ZX6AKXU4xbxc bz69zo1pK90Cz9CKw6ua5P5hiHNQBWvk34iHsdo+N04qMqt00crjA7irtGtIcFvWIW+WdRzLRjX VPCNNNsR X-Proofpoint-ORIG-GUID: WEoxvGcAU1vsK2wa-JBGA6BRe6-ODnM6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-08_06,2025-09-08_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 suspectscore=0 phishscore=0 clxscore=1015 spamscore=0 priorityscore=1501 impostorscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060018 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=vacha.bhavsar@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1757356255910124100 Content-Type: text/plain; charset="utf-8" This patch increases the value of the MAX_PACKET_LEGNTH to 131104 from 4096 to allow the GDBState.line_buf to be large enough to accommodate the full contents of the SME ZA storage when the vector length is maximal. This is in preparation for a related patch that allows SME register visibility through remote GDB debugging. Signed-off-by: Vacha Bhavsar Reviewed-by: Peter Maydell --- Changes since v4: - the value for MAX_PACKET_LENGTH is changed from 131100 to 131104 to align with a similar update made to gdbserver --- gdbstub/internals.h | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/gdbstub/internals.h b/gdbstub/internals.h index bf5a5c6302..87f64b6318 100644 --- a/gdbstub/internals.h +++ b/gdbstub/internals.h @@ -11,7 +11,27 @@ =20 #include "exec/cpu-common.h" =20 -#define MAX_PACKET_LENGTH 4096 +/* +* Most "large" transfers (e.g. memory reads, feature XML +* transfer) have mechanisms in the gdb protocol for splitting +* them. However, register values in particular cannot currently +* be split. This packet size must therefore be at least big enough +* for the worst-case register size. Currently that is Arm SME +* ZA storage with a 256x256 byte value. We also must account +* for the conversion from raw data to hex in gdb_memtohex(), +* which writes 2 * size bytes, and for other protocol overhead +* including command, register number and checksum which add +* another 4 bytes of overhead. However, to be consistent with +* the changes made in gdbserver to address this same requirement, +* we add a total of 32 bytes to account for protocol overhead +* (unclear why specifically 32 bytes), bringing the value of=20 +* MAX_PACKET_LENGTH to 2 * 256 * 256 + 32 =3D 131104. +* +* The commit making this change for gdbserver can be found here: +* https://sourceware.org/git/?p=3Dbinutils-gdb.git;a=3Dcommit;h=3D +* b816042e88583f280ad186ff124ab84d31fb592b +*/ +#define MAX_PACKET_LENGTH 131104 =20 /* * Shared structures and definitions --=20 2.34.1 From nobody Mon Feb 9 10:11:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1757356253; cv=none; d=zohomail.com; s=zohoarc; b=DUgc+vNXbu1QNtnwbuxHUZ68e6uox+La0eS6yWkr5JRYXmbnpOuajyQGjj8PDoCAUFqYa7IeXMB7YGG7Bnpjd6kZ8tvRwyxLQ0o6AaL/5VrMOc6SygK58KnIWIjQKJVuYKQ0lfCVIHKJjsQkMz3oy19EdtyRi9YoJR/C/GT46Do= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1757356253; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=z/urZLMPuM4d+XgtAOiLTf1NrHdA73jaMLOUSb5buQo=; b=Cxn7DAgpcvE2Z+HZWBH4+4VnSrurMbRm6m3BVT3zTlDXj/4bg4zXJxvrn09a/W/y+A15NuoM7aY4IDIDu7syzFkY9DdAGSWr+73q9s/LLzZtzgPLI+YCeugfN81Q9MRJ3btbgD2GYBMiZ7difOz/KY8rOivGP/n1EvFJuNPf4c4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1757356253786745.3983035490124; Mon, 8 Sep 2025 11:30:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uvgc5-000814-8p; Mon, 08 Sep 2025 14:29:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uvgbl-0007yO-3H for qemu-devel@nongnu.org; Mon, 08 Sep 2025 14:28:53 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uvgbb-0001BB-Qp for qemu-devel@nongnu.org; Mon, 08 Sep 2025 14:28:52 -0400 Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 588HYUMa012376 for ; Mon, 8 Sep 2025 18:28:40 GMT Received: from mail-pf1-f199.google.com (mail-pf1-f199.google.com [209.85.210.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 490cj0nkvh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Mon, 08 Sep 2025 18:28:39 +0000 (GMT) Received: by mail-pf1-f199.google.com with SMTP id d2e1a72fcca58-77288e1ce43so4814210b3a.1 for ; Mon, 08 Sep 2025 11:28:39 -0700 (PDT) Received: from admin15.qualcomm.com (i-global254.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=vacha.bhavsar@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1757356256030124100 Content-Type: text/plain; charset="utf-8" The QEMU GDB stub does not expose the ZA storage SME register to GDB via the remote serial protocol, which can be a useful functionality to debug SME code. To provide this functionality in Aarch64 target, this patch registers= the SME register set with the GDB stub. To do so, this patch implements the aarch64_gdb_get_sme_reg() and aarch64_gdb_set_sme_reg() functions to specify how to get and set the SME registers, and the arm_gen_dynamic_smereg_feature() function to generate the target description in XML format to indicate the target architecture supports SME. Finally, this patch includes a dyn_smereg_feature structure to hold this GDB XML description of the SME registers for each CPU. Note that according to the GDB documentation the ZA register is defined as a vector of bytes, however the target description xml retrieved when using gdb natively on a host with SME capabilities represents the ZA register as a ve= ctor of vectors of bytes. To remain consistent with this implementation this pat= ch also represents the ZA register as a vector of vectors of bytes as is done = by GDB here: https://github.com/bminor/binutils-gdb/blob/5cce2b7006daa7073b98e3d1a3b1761= 99d1381d7/gdb/features/aarch64-sme.c#L50 Signed-off-by: Vacha Bhavsar --- Changes since v6: - removed unnecessary comment - corrected indentation --- target/arm/cpu.h | 1 + target/arm/gdbstub.c | 9 +++- target/arm/gdbstub64.c | 119 +++++++++++++++++++++++++++++++++++++++++ target/arm/internals.h | 3 ++ 4 files changed, 131 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c15d79a106..92808c2fe6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -935,6 +935,7 @@ struct ArchCPU { =20 DynamicGDBFeatureInfo dyn_sysreg_feature; DynamicGDBFeatureInfo dyn_svereg_feature; + DynamicGDBFeatureInfo dyn_smereg_feature; DynamicGDBFeatureInfo dyn_m_systemreg_feature; DynamicGDBFeatureInfo dyn_m_secextreg_feature; =20 diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index ce4497ad7c..cfde7c3a46 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -527,7 +527,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) * registers so we don't need to include both. */ #ifdef TARGET_AARCH64 - if (isar_feature_aa64_sve(&cpu->isar)) { + if (isar_feature_aa64_sve(&cpu->isar) || isar_feature_aa64_sme(&cp= u->isar)) { GDBFeature *feature =3D arm_gen_dynamic_svereg_feature(cs, cs-= >gdb_num_regs); gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg, aarch64_gdb_set_sve_reg, feature, 0); @@ -537,6 +537,13 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cp= u) gdb_find_static_feature("aarch64-fpu.= xml"), 0); } + + if (isar_feature_aa64_sme(&cpu->isar)) { + GDBFeature *sme_feature =3D arm_gen_dynamic_smereg_feature(cs, + cs->g= db_num_regs); + gdb_register_coprocessor(cs, aarch64_gdb_get_sme_reg, + aarch64_gdb_set_sme_reg, sme_feature,= 0); + } /* * Note that we report pauth information via the feature name * org.gnu.gdb.aarch64.pauth_v2, not org.gnu.gdb.aarch64.pauth. diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 08e2858539..3bccde2bf2 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -249,6 +249,90 @@ int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf= , int reg) return 0; } =20 +int aarch64_gdb_get_sme_reg(CPUState *cs, GByteArray *buf, int reg) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + switch (reg) { + case 0: /* svg register */ + { + int vq =3D 0; + if (FIELD_EX64(env->svcr, SVCR, SM)) { + vq =3D sve_vqm1_for_el_sm(env, arm_current_el(env), + FIELD_EX64(env->svcr, SVCR, SM)) + 1; + } + /* svg =3D vector granules (2 * vector quardwords) in streaming mo= de */ + return gdb_get_reg64(buf, vq * 2); + } + case 1: /* svcr register */ + return gdb_get_reg64(buf, env->svcr); + case 2: /* za register */ + { + int len =3D 0; + int vq =3D cpu->sme_max_vq; + int svl =3D vq * 16; + for (int i =3D 0; i < svl; i++) { + for (int q =3D 0; q < vq; q++) { + len +=3D gdb_get_reg128(buf, + env->za_state.za[i].d[q * 2 + 1], + env->za_state.za[i].d[q * 2]); + } + } + return len; + } + default: + /* gdbstub asked for something out of range */ + qemu_log_mask(LOG_UNIMP, "%s: out of range register %d", __func__,= reg); + break; + } + + return 0; +} + +int aarch64_gdb_set_sme_reg(CPUState *cs, uint8_t *buf, int reg) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + switch (reg) { + case 0: /* svg register */ + /* cannot set svg via gdbstub */ + return 8; + case 1: /* svcr register */ + aarch64_set_svcr(env, ldq_le_p(buf), + R_SVCR_SM_MASK | R_SVCR_ZA_MASK); + return 8; + case 2: /* za register */ + { + int len =3D 0; + int vq =3D cpu->sme_max_vq; + int svl =3D vq * 16; + for (int i =3D 0; i < svl; i++) { + for (int q =3D 0; q < vq; q++) { + if (target_big_endian()) { + env->za_state.za[i].d[q * 2 + 1] =3D ldq_p(buf); + buf +=3D 8; + env->za_state.za[i].d[q * 2] =3D ldq_p(buf); + } else{ + env->za_state.za[i].d[q * 2] =3D ldq_p(buf); + buf +=3D 8; + env->za_state.za[i].d[q * 2 + 1] =3D ldq_p(buf); + } + buf +=3D 8; + len +=3D 16; + } + } + return len; + } + default: + /* gdbstub asked for something out of range */ + break; + } + + return 0; +} + int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int reg) { ARMCPU *cpu =3D ARM_CPU(cs); @@ -413,6 +497,41 @@ GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *c= s, int base_reg) return &cpu->dyn_svereg_feature.desc; } =20 +GDBFeature *arm_gen_dynamic_smereg_feature(CPUState *cs, int base_reg) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + int vq =3D cpu->sme_max_vq; + int svl =3D vq * 16; + GDBFeatureBuilder builder; + int reg =3D 0; + + gdb_feature_builder_init(&builder, &cpu->dyn_smereg_feature.desc, + "org.gnu.gdb.aarch64.sme", "sme-registers.xml= ", + base_reg); + + + /* Create the sme_bv vector type. */ + gdb_feature_builder_append_tag( + &builder, "", + svl); + + /* Create the sme_bvv vector type. */ + gdb_feature_builder_append_tag( + &builder, "", + svl); + + /* Define the svg, svcr, and za registers. */ + + gdb_feature_builder_append_reg(&builder, "svg", 64, reg++, "int", NULL= ); + gdb_feature_builder_append_reg(&builder, "svcr", 64, reg++, "int", NUL= L); + gdb_feature_builder_append_reg(&builder, "za", svl * svl * 8, reg++, + "sme_bvv", NULL); + + gdb_feature_builder_end(&builder); + + return &cpu->dyn_smereg_feature.desc; +} + #ifdef CONFIG_USER_ONLY int aarch64_gdb_get_tag_ctl_reg(CPUState *cs, GByteArray *buf, int reg) { diff --git a/target/arm/internals.h b/target/arm/internals.h index f5a1e75db3..df99a17448 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1820,8 +1820,11 @@ static inline uint64_t pmu_counter_mask(CPUARMState = *env) } =20 GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *cpu, int base_reg); +GDBFeature *arm_gen_dynamic_smereg_feature(CPUState *cpu, int base_reg); int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray *buf, int reg); int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf, int reg); +int aarch64_gdb_get_sme_reg(CPUState *cs, GByteArray *buf, int reg); +int aarch64_gdb_set_sme_reg(CPUState *cs, uint8_t *buf, int reg); int aarch64_gdb_get_fpu_reg(CPUState *cs, GByteArray *buf, int reg); int aarch64_gdb_set_fpu_reg(CPUState *cs, uint8_t *buf, int reg); int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int reg); --=20 2.34.1 From nobody Mon Feb 9 10:11:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1757356289; cv=none; d=zohomail.com; s=zohoarc; b=aPz49ZSz6Ka/6107FM5J/eIhp+XWpUu6j6UvvVn+KVi1+c+S5kYKuZ5ZXm/tRC2n7LprJ3KC+vA8X1tDCoic6LikN6BdW5gSjzjtqgD0nw4wEeFHG85LHMKBEXNZkskJdImZrg+pV4ilun7q74flEjZygll+oT58lMHXWdVQtWs= ARC-Message-Signature: i=1; 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Mon, 08 Sep 2025 11:28:39 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFum+csjEs7j5pwEm3dPD3XQBJuekdLEcDs89Ufxyf0P01sRmq1HZiknm8O7cElTbz9htywzw== X-Received: by 2002:a05:6a20:9184:b0:251:e4b4:7a37 with SMTP id adf61e73a8af0-2533fd956b8mr14460916637.19.1757356118804; Mon, 08 Sep 2025 11:28:38 -0700 (PDT) From: Vacha Bhavsar To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , Thomas Huth , Vacha Bhavsar Subject: [PATCH v7 3/3] target/arm: Added test case for SME register exposure to GDB Date: Mon, 8 Sep 2025 18:28:34 +0000 Message-Id: <20250908182834.2476277-4-vacha.bhavsar@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908182834.2476277-1-vacha.bhavsar@oss.qualcomm.com> References: <20250908182834.2476277-1-vacha.bhavsar@oss.qualcomm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=FN4bx/os c=1 sm=1 tr=0 ts=68bf2059 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=Z_9JEIKELzp6YBcrEJoA:9 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-ORIG-GUID: 6PLqvX07JmQ4gV7kGloOKvF9CPjKUGor X-Proofpoint-GUID: 6PLqvX07JmQ4gV7kGloOKvF9CPjKUGor X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA4MDA5NCBTYWx0ZWRfXyeck0vk27c/o eC3w77tj9QXrSGE+9LWBp/hG2oAfLbUOsCNY9qd20mJ8K3AXZGcl9+G4r4rNtwzgcS2G03SO6pj 0SjJ6rI4gAtG9cw3wyHAe73z6YGZk+X9ArUctdISyYoIxcgZd7mYI9OQnUxtbcEFBQeGiQbkQA7 ssWe7GtEcryHCtnMK9zDl+ejbekenGerZoRuwepMZqId0gm21qo/sYPkSzoOC9U8sT2cF+lW/YE IU49IN8y68O4M1MZwGaITDoH6pNYbsFMWBHLdo9B4LdQ4YeT9EZzRdhE/9+BavbjG85R8RjqtwT cdgxMlUv5+qwMJArRxmHynESyVUxeTsktSbEkDjpJWNdZVRGXfsLwqA4ENx0S1LZVW+KRlXCvPH AT+R+aXj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-08_06,2025-09-08_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 clxscore=1015 phishscore=0 adultscore=0 bulkscore=0 impostorscore=0 malwarescore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509080094 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=vacha.bhavsar@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1757356291530116600 Content-Type: text/plain; charset="utf-8" This patch adds a test case to test SME register exposure to a remote gdb debugging session. This test simply sets and reads SME registers. Signed-off-by: Vacha Bhavsar --- Changes since v6: - added functionality to skip ZA quadword and doubleword tile slice tests when the detected version of gdb does not support SME tile slices - added functionality to skip ZA quadword tile slice test when the detected version of gdb does not support casting gdb.Value to a 128bit python integer - cleaned up testcase and made it more compact with additional comments --- configure | 11 +++ tests/tcg/aarch64/Makefile.target | 51 +++++++++++ tests/tcg/aarch64/gdbstub/test-sme.py | 125 ++++++++++++++++++++++++++ 3 files changed, 187 insertions(+) create mode 100644 tests/tcg/aarch64/gdbstub/test-sme.py diff --git a/configure b/configure index 274a778764..8de18e755f 100755 --- a/configure +++ b/configure @@ -1839,6 +1839,17 @@ for target in $target_list; do echo "GDB=3D$gdb_bin" >> $config_target_mak fi =20 + if test "${gdb_arches#*$arch}" !=3D "$gdb_arches" && version_ge $gdb= _version 14.1; then + echo "GDB_HAS_SME_TILES=3Dy" >> $config_target_mak + if version_ge $gdb_version 16.1; then + echo "GDB_HAS_128BIT_INT_CAST_SUPPORT=3Dy" >> $config_target_m= ak + else + echo "GDB_HAS_128BIT_INT_CAST_SUPPORT=3Dn" >> $config_target_m= ak + fi + else + echo "GDB_HAS_SME_TILES=3Dn" >> $config_target_mak + fi + if test "${gdb_arches#*aarch64}" !=3D "$gdb_arches" && version_ge $g= db_version 15.1; then echo "GDB_HAS_MTE=3Dy" >> $config_target_mak fi diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile= .target index 16ddcf4f88..954bc3139a 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -134,6 +134,57 @@ run-gdbstub-sve-ioctls: sve-ioctls =20 EXTRA_RUNS +=3D run-gdbstub-sysregs run-gdbstub-sve-ioctls =20 +ifneq ($(CROSS_AS_HAS_ARMV9_SME),) +# SME gdbstub tests + +run-gdbstub-sysregs-sme: sysregs + $(call run-test, $@, $(GDB_SCRIPT) \ + --gdb $(GDB) \ + --qemu $(QEMU) --qargs "$(QEMU_OPTS)" \ + --bin $< --test $(AARCH64_SRC)/gdbstub/test-sme.py \ + -- test_sme --gdb_basic_za_test, \ + basic gdbstub SME support) + +ifeq ($(GDB_HAS_SME_TILES),y) +run-gdbstub-sysregs-sme-doubleword-tile-slice: sysregs + $(call run-test, $@, $(GDB_SCRIPT) \ + --gdb $(GDB) \ + --qemu $(QEMU) --qargs "$(QEMU_OPTS)" \ + --bin $< --test $(AARCH64_SRC)/gdbstub/test-sme.py \ + -- test_sme --gdb_doubleword_tile_slice_test, \ + gdbstub SME ZA doubleword tile slice support) + +ifeq ($(GDB_HAS_128BIT_INT_CAST_SUPPORT),y) +run-gdbstub-sysregs-sme-quadword-tile-slice: sysregs + $(call run-test, $@, $(GDB_SCRIPT) \ + --gdb $(GDB) \ + --qemu $(QEMU) --qargs "$(QEMU_OPTS)" \ + --bin $< --test $(AARCH64_SRC)/gdbstub/test-sme.py \ + -- test_sme --gdb_quadword_tile_slice_test, \ + gdbstub SME ZA quadword tile slice support)=09 + +else +run-gdbstub-sysregs-sme-quadword-tile-slice: sysregs + $(call skip-test,"gdbstub SME ZA quadword tile slice support", \ + "selected gdb ($(GDB)) does not support casting gdb.Value into 128bit pyt= hon integer") + +endif +else +run-gdbstub-sysregs-sme-doubleword-tile-slice: sysregs + $(call skip-test,"gdbstub SME ZA doubleword tile slice support", \ + "selected gdb ($(GDB)) does not support SME ZA tile slices") + +run-gdbstub-sysregs-sme-quadword-tile-slice: sysregs + $(call skip-test,"gdbstub SME ZA quadword tile slice support", \ + "selected gdb ($(GDB)) does not support SME ZA tile slices") + +endif + +EXTRA_RUNS +=3D run-gdbstub-sysregs-sme run-gdbstub-sysregs-sme-doubleword= -tile-slice \ + run-gdbstub-sysregs-sme-quadword-tile-slice + =20 +endif + ifeq ($(GDB_HAS_MTE),y) run-gdbstub-mte: mte-8 $(call run-test, $@, $(GDB_SCRIPT) \ diff --git a/tests/tcg/aarch64/gdbstub/test-sme.py b/tests/tcg/aarch64/gdbs= tub/test-sme.py new file mode 100644 index 0000000000..bad80f9925 --- /dev/null +++ b/tests/tcg/aarch64/gdbstub/test-sme.py @@ -0,0 +1,125 @@ +# +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# +# SPDX-License-Identifier: GPL-2.0-or-later + +from __future__ import print_function +# +# Test the SME registers are visible and changeable via gdbstub +# +# This is launched via tests/guest-debug/run-test.py +# + +import argparse +import gdb +from test_gdbstub import main, report + +MAGIC =3D 0x01020304 +BASIC_ZA_TEST =3D 0 +DOUBLEWORD_TILE_SLICE_TEST =3D 0 +QUADWORD_TILE_SLICE_TEST =3D 0 + +def run_test(): + =20 + # Run the requested test(s) for SME ZA gdbstub support + + if BASIC_ZA_TEST: + run_basic_sme_za_gdbstub_support_test() + if DOUBLEWORD_TILE_SLICE_TEST or QUADWORD_TILE_SLICE_TEST: + run_basic_sme_za_tile_slice_gdbstub_support_test() + +def run_basic_sme_za_gdbstub_support_test(): + + # This test will check for gdbstub support for correctly reading + # and writing to the SME ZA register at the byte level. + =20 + frame =3D gdb.selected_frame() + rname =3D "za" + za =3D frame.read_register(rname) + report(True, "Reading %s" % rname) + + # Writing to the ZA register, byte by byte. + for i in range(0, 16): + for j in range(0, 16): + cmd =3D "set $za[%d][%d] =3D 0x01" % (i, j) + gdb.execute(cmd) + report(True, "%s" % cmd) + + # Reading from the ZA register, byte by byte. + for i in range(0, 16): + for j in range(0, 16): + reg =3D "$za[%d][%d]" % (i, j) + v =3D gdb.parse_and_eval(reg) + report(str(v.type) =3D=3D "uint8_t", "size of %s" % (reg)) + report(int(v) =3D=3D 0x1, "%s is 0x%x" % (reg, 0x1)) + +def run_basic_sme_za_tile_slice_gdbstub_support_test(): + + # Test if SME ZA tile slices, both horizontal and vertical, + # can be correctly read and written to. The sizes to test + # depend on which tests are requested (QUADWORD_TILE_SLICE_TEST + # and/or DOUBLEWORD_TILE_SLICE_TEST). + + sizes =3D {} + if QUADWORD_TILE_SLICE_TEST: + sizes["q"] =3D "uint128_t" + if DOUBLEWORD_TILE_SLICE_TEST: + sizes["d"] =3D "uint64_t" + =20 + # Accessing requested sizes of elements of ZA + for size in sizes: + + # Accessing various ZA tiles + for i in range(0, 4): + + # Accessing various horizontal slices for each ZA tile + for j in range(0, 4): + # Writing to various elements in each tile slice + for k in range(0, 4): + cmd =3D "set $za%dh%c%d[%d] =3D 0x%x" % (i, size, j, k= , MAGIC) + gdb.execute(cmd) + report(True, "%s" % cmd) + + # Reading from the written elements in each tile slice + for k in range(0, 4): + reg =3D "$za%dh%c%d[%d]" % (i, size, j, k) + v =3D gdb.parse_and_eval(reg) + report(str(v.type) =3D=3D sizes[size], "size of %s" % = (reg)) + report(int(v) =3D=3D MAGIC, "%s is 0x%x" % (reg, MAGIC= )) + =20 + # Accessing various vertical slices for each ZA tile + for j in range(0, 4): + # Writing to various elements in each tile slice + for k in range(0, 4): + cmd =3D "set $za%dv%c%d[%d] =3D 0x%x" % (i, size, j, k= , MAGIC) + gdb.execute(cmd) + report(True, "%s" % cmd) + + # Reading from the written elements in each tile slice + for k in range(0, 4): + reg =3D "$za%dv%c%d[%d]" % (i, size, j, k) + v =3D gdb.parse_and_eval(reg) + report(str(v.type) =3D=3D sizes[size], "size of %s" % = (reg)) + report(int(v) =3D=3D MAGIC, "%s is 0x%x" % (reg, MAGIC= )) + + +parser =3D argparse.ArgumentParser(description=3D"A gdbstub test for SME s= upport") +parser.add_argument("--gdb_basic_za_test", + help=3D"Enable test for basic SME ZA support", + action=3D"store_true") +parser.add_argument("--gdb_doubleword_tile_slice_test", + help=3D"Enable test for ZA doubleword tile slice support", + action=3D"store_true") +parser.add_argument("--gdb_quadword_tile_slice_test", + help=3D"Enable test for ZA quadword tile slice support= ", + action=3D"store_true") +args =3D parser.parse_args() + +if args.gdb_basic_za_test: + BASIC_ZA_TEST =3D 1 +if args.gdb_doubleword_tile_slice_test: + DOUBLEWORD_TILE_SLICE_TEST =3D 1 +if args.gdb_quadword_tile_slice_test: + QUADWORD_TILE_SLICE_TEST =3D 1 + +main(run_test, expected_arch=3D"aarch64") --=20 2.34.1