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Signed-off-by: Richard Henderson --- target/sparc/translate.c | 24 +++++++++++++----------- target/sparc/insns.decode | 12 ++++++++++-- 2 files changed, 23 insertions(+), 13 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index c2ffd965d8..69d5883dec 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2865,22 +2865,24 @@ static bool do_rd_special(DisasContext *dc, bool pr= iv, int rd, return advance_pc(dc); } =20 -static TCGv do_rdy(DisasContext *dc, TCGv dst) +static TCGv do_rdy_1(DisasContext *dc, TCGv dst) { return cpu_y; } =20 -static bool trans_RDY(DisasContext *dc, arg_RDY *a) +static bool do_rdy(DisasContext *dc, int rd) { - /* - * TODO: Need a feature bit for sparcv8. In the meantime, treat all - * 32-bit cpus like sparcv7, which ignores the rs1 field. - * This matches after all other ASR, so Leon3 Asr17 is handled first. - */ - if (avail_64(dc) && a->rs1 !=3D 0) { - return false; - } - return do_rd_special(dc, true, a->rd, do_rdy); + return do_rd_special(dc, true, rd, do_rdy_1); +} + +static bool trans_RDY_v7(DisasContext *dc, arg_RDY_v7 *a) +{ + return avail_32(dc) && do_rdy(dc, a->rd); +} + +static bool trans_RDY_v9(DisasContext *dc, arg_RDY_v9 *a) +{ + return avail_64(dc) && do_rdy(dc, a->rd); } =20 static TCGv do_rd_leon3_config(DisasContext *dc, TCGv dst) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 1b1b85e9c2..74848996ae 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -91,6 +91,7 @@ CALL 01 i:s30 STBAR_v9 10 00000 101000 01111 0 0000000000000 MEMBAR 10 00000 101000 01111 1 000000 cmask:3 mmask:4 =20 + RDY_v9 10 rd:5 101000 00000 0 0000000000000 RDCCR 10 rd:5 101000 00010 0 0000000000000 RDASI 10 rd:5 101000 00011 0 0000000000000 RDTICK 10 rd:5 101000 00100 0 0000000000000 @@ -118,8 +119,15 @@ CALL 01 i:s30 # This confirms that bit 13 is ignored, as 0x8143c000 is STBAR. STBAR_v8 10 ----- 101000 01111 - ------------- =20 - # Before v8, all rs1 accepted; otherwise rs1=3D=3D0. - RDY 10 rd:5 101000 rs1:5 0 0000000000000 + # For v7, bits [18:0] are ignored. + # For v8, bits [18:14], aka rs1, are repurposed and rs1 =3D 0 is RDY, + # and other values are RDASR. However, the v8 manual explicitly + # says that rs1 in 1..14 yield undefined results and do not cause + # an illegal instruction trap, and rs1 in 16..31 are available for + # implementation specific usage. + # Implement not causing an illegal instruction trap for v8 by + # continuing to interpret unused values per v7, i.e. as RDY. + RDY_v7 10 rd:5 101000 ----- - ------------- } =20 { --=20 2.43.0