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According to the SPARC v8 architecture manual, whilst bits 13 and bits 12-0 of the "Read State Register Instructions" are notionally zero, they are marked as unused (i.e. ignored). Fixes: af25071c1d ("target/sparc: Move RDASR, STBAR, MEMBAR to decodetree") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3097 Signed-off-by: Richard Henderson --- target/sparc/translate.c | 12 +++++++++++- target/sparc/insns.decode | 13 ++++++++++++- 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index b922e53bf1..c2ffd965d8 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2823,12 +2823,22 @@ static bool trans_Tcc_i_v9(DisasContext *dc, arg_Tc= c_i_v9 *a) return do_tcc(dc, a->cond, a->cc, a->rs1, true, a->i); } =20 -static bool trans_STBAR(DisasContext *dc, arg_STBAR *a) +static bool do_stbar(DisasContext *dc) { tcg_gen_mb(TCG_MO_ST_ST | TCG_BAR_SC); return advance_pc(dc); } =20 +static bool trans_STBAR_v8(DisasContext *dc, arg_STBAR_v8 *a) +{ + return avail_32(dc) && do_stbar(dc); +} + +static bool trans_STBAR_v9(DisasContext *dc, arg_STBAR_v9 *a) +{ + return avail_64(dc) && do_stbar(dc); +} + static bool trans_MEMBAR(DisasContext *dc, arg_MEMBAR *a) { if (avail_32(dc)) { diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 9e39d23273..1b1b85e9c2 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -88,7 +88,7 @@ CALL 01 i:s30 =20 { [ - STBAR 10 00000 101000 01111 0 0000000000000 + STBAR_v9 10 00000 101000 01111 0 0000000000000 MEMBAR 10 00000 101000 01111 1 000000 cmask:3 mmask:4 =20 RDCCR 10 rd:5 101000 00010 0 0000000000000 @@ -107,6 +107,17 @@ CALL 01 i:s30 RDSTICK_CMPR 10 rd:5 101000 11001 0 0000000000000 RDSTRAND_STATUS 10 rd:5 101000 11010 0 0000000000000 ] + + # The v8 manual, section B.30 STBAR instruction, says + # bits [12:0] are ignored, but bit 13 must be 0. + # However, section B.28 Read State Register Instruction has a + # comment that RDASR with rs1 =3D 15, rd =3D 0 is STBAR. Here, + # bit 13 is also ignored and rd !=3D 0 is merely reserved. + # + # Solaris 8 executes v9 MEMBAR instruction 0x8143e008 during boot. + # This confirms that bit 13 is ignored, as 0x8143c000 is STBAR. + STBAR_v8 10 ----- 101000 01111 - ------------- + # Before v8, all rs1 accepted; otherwise rs1=3D=3D0. RDY 10 rd:5 101000 rs1:5 0 0000000000000 } --=20 2.43.0