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Thu, 4 Sep 2025 13:19:32 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout1.samsung.com 20250904131936epoutp0123486c39175fdd3055fa8a3c455840a1~iFuTeM7Ue1923219232epoutp01a DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1756991976; bh=D7gQOvXOEk210A7UWjNQyRXVMFCOm3z1WCU7GcGI7UE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZKXm9AuprXabKWVe9kpvZ+q+HCAjduU+NNzLdNPOhBTKiYHhL3itISbQ0Oo3IzEzM THzAkeId791RnEKh4kHQMbnVOGm7fsAGdwSUPmm7IsrsnOwDBVVMzl91apn9Tlnzw/ tI/K9rxMdvQWEkzK/Wv/zp8fUAIMTOLuulBLEENA= From: Arpit Kumar To: qemu-devel@nongnu.org Cc: gost.dev@samsung.com, linux-cxl@vger.kernel.org, dave@stgolabs.net, Jonathan.Cameron@huawei.com, vishak.g@samsung.com, krish.reddy@samsung.com, a.manzanares@samsung.com, alok.rathore@samsung.com, cpgs@samsung.com, Arpit Kumar Subject: [PATCH v3 1/2] hw/cxl: Refactored Identify Switch Device & Get Physical Port State Date: Thu, 4 Sep 2025 18:49:03 +0530 Message-Id: <20250904131904.725758-2-arpit1.kumar@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250904131904.725758-1-arpit1.kumar@samsung.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250904131933epcas5p2ab29fa060d8a7df32a222aad740fedc6 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P X-CPGSPASS: Y cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250904131933epcas5p2ab29fa060d8a7df32a222aad740fedc6 References: <20250904131904.725758-1-arpit1.kumar@samsung.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=203.254.224.24; envelope-from=arpit1.kumar@samsung.com; helo=mailout1.samsung.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @samsung.com) X-ZM-MESSAGEID: 1756992095815124100 -Storing physical ports info during enumeration. -Refactored changes using physical ports info for Identify Switch Device (Opcode 5100h) & Get Physical Port State (Opcode 5101h) physical switch FM-API command set. Signed-off-by: Arpit Kumar --- hw/cxl/cxl-mailbox-utils.c | 230 ++++++++++++---------- include/hw/cxl/cxl_device.h | 67 +++++++ include/hw/pci-bridge/cxl_upstream_port.h | 8 + 3 files changed, 198 insertions(+), 107 deletions(-) diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index c5177dfd92..cb36880f0b 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -435,16 +435,6 @@ static CXLRetCode cmd_set_response_msg_limit(const str= uct cxl_cmd *cmd, return CXL_MBOX_SUCCESS; } =20 -static void cxl_set_dsp_active_bm(PCIBus *b, PCIDevice *d, - void *private) -{ - uint8_t *bm =3D private; - if (object_dynamic_cast(OBJECT(d), TYPE_CXL_DSP)) { - uint8_t port =3D PCIE_PORT(d)->port; - bm[port / 8] |=3D 1 << (port % 8); - } -} - /* CXL r3.1 Section 7.6.7.1.1: Identify Switch Device (Opcode 5100h) */ static CXLRetCode cmd_identify_switch_device(const struct cxl_cmd *cmd, uint8_t *payload_in, @@ -453,9 +443,8 @@ static CXLRetCode cmd_identify_switch_device(const stru= ct cxl_cmd *cmd, size_t *len_out, CXLCCI *cci) { - PCIEPort *usp =3D PCIE_PORT(cci->d); - PCIBus *bus =3D &PCI_BRIDGE(cci->d)->sec_bus; - int num_phys_ports =3D pcie_count_ds_ports(bus); + CXLUpstreamPort *pp =3D CXL_USP(cci->d); + uint8_t num_phys_ports =3D pp->pports.num_ports; =20 struct cxl_fmapi_ident_switch_dev_resp_pl { uint8_t ingress_port_id; @@ -472,11 +461,11 @@ static CXLRetCode cmd_identify_switch_device(const st= ruct cxl_cmd *cmd, =20 out =3D (struct cxl_fmapi_ident_switch_dev_resp_pl *)payload_out; *out =3D (struct cxl_fmapi_ident_switch_dev_resp_pl) { - .num_physical_ports =3D num_phys_ports + 1, /* 1 USP */ + .num_physical_ports =3D num_phys_ports, .num_vcss =3D 1, /* Not yet support multiple VCS - potentially tri= cky */ .active_vcs_bitmask[0] =3D 0x1, - .total_vppbs =3D num_phys_ports + 1, - .bound_vppbs =3D num_phys_ports + 1, + .total_vppbs =3D num_phys_ports, + .bound_vppbs =3D num_phys_ports, .num_hdm_decoders_per_usp =3D 4, }; =20 @@ -488,16 +477,14 @@ static CXLRetCode cmd_identify_switch_device(const st= ruct cxl_cmd *cmd, out->ingress_port_id =3D 0; } =20 - pci_for_each_device_under_bus(bus, cxl_set_dsp_active_bm, - out->active_port_bitmask); - out->active_port_bitmask[usp->port / 8] |=3D (1 << usp->port % 8); - + memcpy(out->active_port_bitmask, pp->pports.active_port_bitmask, + sizeof(pp->pports.active_port_bitmask)); *len_out =3D sizeof(*out); =20 return CXL_MBOX_SUCCESS; } =20 -/* CXL r3.1 Section 7.6.7.1.2: Get Physical Port State (Opcode 5101h) */ +/* CXL r3.2 Section 7.6.7.1.2: Get Physical Port State (Opcode 5101h) */ static CXLRetCode cmd_get_physical_port_state(const struct cxl_cmd *cmd, uint8_t *payload_in, size_t len_in, @@ -505,44 +492,22 @@ static CXLRetCode cmd_get_physical_port_state(const s= truct cxl_cmd *cmd, size_t *len_out, CXLCCI *cci) { - /* CXL r3.1 Table 7-17: Get Physical Port State Request Payload */ + CXLUpstreamPort *pp =3D CXL_USP(cci->d); + size_t pl_size; + int i; + + /* CXL r3.2 Table 7-17: Get Physical Port State Request Payload */ struct cxl_fmapi_get_phys_port_state_req_pl { uint8_t num_ports; uint8_t ports[]; } QEMU_PACKED *in; =20 - /* - * CXL r3.1 Table 7-19: Get Physical Port State Port Information Block - * Format - */ - struct cxl_fmapi_port_state_info_block { - uint8_t port_id; - uint8_t config_state; - uint8_t connected_device_cxl_version; - uint8_t rsv1; - uint8_t connected_device_type; - uint8_t port_cxl_version_bitmask; - uint8_t max_link_width; - uint8_t negotiated_link_width; - uint8_t supported_link_speeds_vector; - uint8_t max_link_speed; - uint8_t current_link_speed; - uint8_t ltssm_state; - uint8_t first_lane_num; - uint16_t link_state; - uint8_t supported_ld_count; - } QEMU_PACKED; - - /* CXL r3.1 Table 7-18: Get Physical Port State Response Payload */ + /* CXL r3.2 Table 7-18: Get Physical Port State Response Payload */ struct cxl_fmapi_get_phys_port_state_resp_pl { uint8_t num_ports; uint8_t rsv1[3]; - struct cxl_fmapi_port_state_info_block ports[]; + CXLPhyPortInfo ports[]; } QEMU_PACKED *out; - PCIBus *bus =3D &PCI_BRIDGE(cci->d)->sec_bus; - PCIEPort *usp =3D PCIE_PORT(cci->d); - size_t pl_size; - int i; =20 in =3D (struct cxl_fmapi_get_phys_port_state_req_pl *)payload_in; out =3D (struct cxl_fmapi_get_phys_port_state_resp_pl *)payload_out; @@ -555,69 +520,20 @@ static CXLRetCode cmd_get_physical_port_state(const s= truct cxl_cmd *cmd, return CXL_MBOX_INVALID_INPUT; } =20 - /* For success there should be a match for each requested */ - out->num_ports =3D in->num_ports; + if (in->num_ports > pp->pports.num_ports) { + return CXL_MBOX_INVALID_INPUT; + } =20 + out->num_ports =3D in->num_ports; for (i =3D 0; i < in->num_ports; i++) { - struct cxl_fmapi_port_state_info_block *port; - /* First try to match on downstream port */ - PCIDevice *port_dev; - uint16_t lnkcap, lnkcap2, lnksta; + int pn =3D in->ports[i]; =20 - port =3D &out->ports[i]; - - port_dev =3D pcie_find_port_by_pn(bus, in->ports[i]); - if (port_dev) { /* DSP */ - PCIDevice *ds_dev =3D pci_bridge_get_sec_bus(PCI_BRIDGE(port_d= ev)) - ->devices[0]; - port->config_state =3D 3; - if (ds_dev) { - if (object_dynamic_cast(OBJECT(ds_dev), TYPE_CXL_TYPE3)) { - port->connected_device_type =3D 5; /* Assume MLD for n= ow */ - } else { - port->connected_device_type =3D 1; - } - } else { - port->connected_device_type =3D 0; - } - port->supported_ld_count =3D 3; - } else if (usp->port =3D=3D in->ports[i]) { /* USP */ - port_dev =3D PCI_DEVICE(usp); - port->config_state =3D 4; - port->connected_device_type =3D 0; - } else { + if (pp->pports.pport_info[pn].port_id !=3D pn) { return CXL_MBOX_INVALID_INPUT; } - - port->port_id =3D in->ports[i]; - /* Information on status of this port in lnksta, lnkcap */ - if (!port_dev->exp.exp_cap) { - return CXL_MBOX_INTERNAL_ERROR; - } - lnksta =3D port_dev->config_read(port_dev, - port_dev->exp.exp_cap + PCI_EXP_LNK= STA, - sizeof(lnksta)); - lnkcap =3D port_dev->config_read(port_dev, - port_dev->exp.exp_cap + PCI_EXP_LNK= CAP, - sizeof(lnkcap)); - lnkcap2 =3D port_dev->config_read(port_dev, - port_dev->exp.exp_cap + PCI_EXP_LN= KCAP2, - sizeof(lnkcap2)); - - port->max_link_width =3D (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4; - port->negotiated_link_width =3D (lnksta & PCI_EXP_LNKSTA_NLW) >> 4; - /* No definition for SLS field in linux/pci_regs.h */ - port->supported_link_speeds_vector =3D (lnkcap2 & 0xFE) >> 1; - port->max_link_speed =3D lnkcap & PCI_EXP_LNKCAP_SLS; - port->current_link_speed =3D lnksta & PCI_EXP_LNKSTA_CLS; - /* TODO: Track down if we can get the rest of the info */ - port->ltssm_state =3D 0x7; - port->first_lane_num =3D 0; - port->link_state =3D 0; - port->port_cxl_version_bitmask =3D 0x2; - port->connected_device_cxl_version =3D 0x2; + memcpy(&out->ports[i], &(pp->pports.pport_info[pn]), + sizeof(CXLPhyPortInfo)); } - pl_size =3D sizeof(*out) + sizeof(*out->ports) * in->num_ports; *len_out =3D pl_size; =20 @@ -4684,6 +4600,104 @@ void cxl_add_cci_commands(CXLCCI *cci, const struct= cxl_cmd (*cxl_cmd_set)[256], cxl_rebuild_cel(cci); } =20 +static CXLRetCode cxl_set_port_type(CXLUpstreamPort *ports, int pnum, + CXLCCI *cci) +{ + uint8_t current_port_config_state; + uint8_t connected_device_type; + uint8_t supported_ld_count; + uint16_t lnkcap, lnkcap2, lnksta; + PCIBus *bus; + PCIDevice *port_dev; + PCIEPort *usp =3D PCIE_PORT(cci->d); + + if (usp->port =3D=3D pnum) { + port_dev =3D PCI_DEVICE(usp); + current_port_config_state =3D CXL_PORT_CONFIG_STATE_USP; + connected_device_type =3D NO_DEVICE_DETECTED; + supported_ld_count =3D 0; + } else { + bus =3D &PCI_BRIDGE(cci->d)->sec_bus; + port_dev =3D pcie_find_port_by_pn(bus, pnum); + if (port_dev) { /* DSP */ + PCIDevice *ds_dev =3D pci_bridge_get_sec_bus(PCI_BRIDGE(port_d= ev)) + ->devices[0]; + current_port_config_state =3D CXL_PORT_CONFIG_STATE_DSP; + if (ds_dev) { + if (object_dynamic_cast(OBJECT(ds_dev), TYPE_CXL_TYPE3)) { + /* To-do: controllable */ + connected_device_type =3D CXL_TYPE_3_SLD; + } else { + connected_device_type =3D PCIE_DEVICE; + } + } else { + connected_device_type =3D NO_DEVICE_DETECTED; + } + supported_ld_count =3D 3; + } else { + return CXL_MBOX_INVALID_INPUT; + } + } + + if (!port_dev->exp.exp_cap) { + return CXL_MBOX_INTERNAL_ERROR; + } + lnksta =3D port_dev->config_read(port_dev, + port_dev->exp.exp_cap + PCI_EXP_LNKSTA, + sizeof(lnksta)); + lnkcap =3D port_dev->config_read(port_dev, + port_dev->exp.exp_cap + PCI_EXP_LNKCAP, + sizeof(lnkcap)); + lnkcap2 =3D port_dev->config_read(port_dev, + port_dev->exp.exp_cap + PCI_EXP_LNKCAP= 2, + sizeof(lnkcap2)); + + ports->pports.pport_info[pnum] =3D (CXLPhyPortInfo) { + .port_id =3D pnum, + .current_port_config_state =3D current_port_config_state, + .connected_device_mode =3D STANDARD_256B_FLIT_MODE, + .connected_device_type =3D connected_device_type, + .supported_cxl_modes =3D CXL_256B_FLIT_CAPABLE, + .max_link_width =3D (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4, + .negotiated_link_width =3D (lnksta & PCI_EXP_LNKSTA_NLW) >> 4, + .supported_link_speeds_vector =3D (lnkcap2 & 0xFE) >> 1, + .max_link_speed =3D lnkcap & PCI_EXP_LNKCAP_SLS, + .current_link_speed =3D lnksta & PCI_EXP_LNKSTA_CLS, + .ltssm_state =3D CXL_LTSSM_L2, + .first_negotiated_lane_num =3D 0, + .link_state_flags =3D 0, + .supported_ld_count =3D supported_ld_count, + }; + ports->pports.active_port_bitmask[pnum / 8] |=3D (1 << pnum % 8); + + return CXL_MBOX_SUCCESS; +} + +static void cxl_set_dsp_port(PCIBus *bus, PCIDevice *dev, void *opaque) +{ + CXLCCI *cci =3D (CXLCCI *)opaque; + CXLUpstreamPort *pp =3D CXL_USP(cci->d); + + if (object_dynamic_cast(OBJECT(dev), TYPE_CXL_DSP)) { + cxl_set_port_type(pp, PCIE_PORT(dev)->port, cci); + } +} + +static CXLRetCode cxl_set_phy_port_info(CXLCCI *cci) +{ + PCIEPort *usp =3D PCIE_PORT(cci->d); + PCIBus *bus =3D &PCI_BRIDGE(cci->d)->sec_bus; + CXLUpstreamPort *pp =3D CXL_USP(cci->d); + int num_phys_ports =3D pcie_count_ds_ports(bus) + 1; + pp->pports.num_ports =3D num_phys_ports; + uint8_t phy_port_num =3D usp->port; + + cxl_set_port_type(pp, phy_port_num, cci); /* USP */ + pci_for_each_device_under_bus(bus, cxl_set_dsp_port, cci); /* DSP */ + + return CXL_MBOX_SUCCESS; +} + void cxl_initialize_mailbox_swcci(CXLCCI *cci, DeviceState *intf, DeviceState *d, size_t payload_max) { @@ -4691,6 +4705,7 @@ void cxl_initialize_mailbox_swcci(CXLCCI *cci, Device= State *intf, cci->d =3D d; cci->intf =3D intf; cxl_init_cci(cci, payload_max); + cxl_set_phy_port_info(cci); } =20 void cxl_initialize_mailbox_t3(CXLCCI *cci, DeviceState *d, size_t payload= _max) @@ -4777,4 +4792,5 @@ void cxl_initialize_usp_mctpcci(CXLCCI *cci, DeviceSt= ate *d, DeviceState *intf, cci->d =3D d; cci->intf =3D intf; cxl_init_cci(cci, payload_max); + cxl_set_phy_port_info(cci); } diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index 068c20d61e..9fc720ec10 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -129,6 +129,73 @@ CXL_NUM_CPMU_INSTANCES * (1 << 16), \ (1 << 16)) =20 +#define CXL_MAX_PHY_PORTS 256 + +/* physical port control info - CXL r3.2 table 7-19 */ +#define CXL_PORT_CONFIG_STATE_DISABLED 0x0 +#define CXL_PORT_CONFIG_STATE_BIND_IN_PROGRESS 0x1 +#define CXL_PORT_CONFIG_STATE_UNBIND_IN_PROGRESS 0x2 +#define CXL_PORT_CONFIG_STATE_DSP 0x3 +#define CXL_PORT_CONFIG_STATE_USP 0x4 +#define CXL_PORT_CONFIG_STATE_FABRIC_PORT 0x5 +#define CXL_PORT_CONFIG_STATE_INVALID_PORT_ID 0xF + +#define NOT_CXL_OR_DISCONNECTED 0x00 +#define RCD_MODE 0x01 +#define CXL_68B_FLIT_AND_VH_MODE 0x02 +#define STANDARD_256B_FLIT_MODE 0x03 +#define CXL_LATENCY_OPTIMIZED_256B_FLIT_MODE 0x04 +#define PBR_MODE 0x05 + +#define NO_DEVICE_DETECTED 0 +#define PCIE_DEVICE 1 +#define CXL_TYPE_1_DEVICE 2 +#define CXL_TYPE_2_DEVICE_OR_HBR_SWITCH 3 +#define CXL_TYPE_3_SLD 4 +#define CXL_TYPE_3_MLD 5 +#define PBR_COMPONENT 6 + +#define CXL_RCD_MODE 0x00 +#define CXL_68B_FLIT_AND_VH_CAPABLE 0x01 +#define CXL_256B_FLIT_CAPABLE 0x02 +#define CXL_LATENCY_OPTIMIZED_256B_FLIT 0x03 +#define CXL_PBR_CAPABLE 0x04 + +#define CXL_LTSSM_DETECT 0x00 +#define CXL_LTSSM_POLLING 0x01 +#define CXL_LTSSM_CONFIGURATION 0x02 +#define CXL_LTSSM_RECOVERY 0x03 +#define CXL_LTSSM_L0 0x04 +#define CXL_LTSSM_L0S 0x05 +#define CXL_LTSSM_L1 0x06 +#define CXL_LTSSM_L2 0x07 +#define CXL_LTSSM_DISABLED 0x08 +#define CXL_LTSSM_LOOPBACK 0x09 +#define CXL_LTSSM_HOT_RESET 0x0A + +#define LINK_STATE_FLAG_LANE_REVERSED BIT(0) +#define LINK_STATE_FLAG_PERST_ASSERTED BIT(1) +#define LINK_STATE_FLAG_PRSNT BIT(2) +#define LINK_STATE_FLAG_POWER_OFF BIT(3) + +typedef struct CXLPhyPortInfo { + uint8_t port_id; + uint8_t current_port_config_state; + uint8_t connected_device_mode; + uint8_t rsv1; + uint8_t connected_device_type; + uint8_t supported_cxl_modes; + uint8_t max_link_width; + uint8_t negotiated_link_width; + uint8_t supported_link_speeds_vector; + uint8_t max_link_speed; + uint8_t current_link_speed; + uint8_t ltssm_state; + uint8_t first_negotiated_lane_num; + uint16_t link_state_flags; + uint8_t supported_ld_count; +} QEMU_PACKED CXLPhyPortInfo; + /* CXL r3.1 Table 8-34: Command Return Codes */ typedef enum { CXL_MBOX_SUCCESS =3D 0x0, diff --git a/include/hw/pci-bridge/cxl_upstream_port.h b/include/hw/pci-bri= dge/cxl_upstream_port.h index db1dfb6afd..3b7e72bfe0 100644 --- a/include/hw/pci-bridge/cxl_upstream_port.h +++ b/include/hw/pci-bridge/cxl_upstream_port.h @@ -4,6 +4,7 @@ #include "hw/pci/pcie.h" #include "hw/pci/pcie_port.h" #include "hw/cxl/cxl.h" +#include "include/hw/cxl/cxl_device.h" =20 typedef struct CXLUpstreamPort { /*< private >*/ @@ -23,6 +24,13 @@ typedef struct CXLUpstreamPort { =20 DOECap doe_cdat; uint64_t sn; + + /*< physical ports information >*/ + struct { + uint8_t num_ports; + uint8_t active_port_bitmask[CXL_MAX_PHY_PORTS / BITS_PER_BYTE]; + CXLPhyPortInfo pport_info[CXL_MAX_PHY_PORTS]; + } pports; } CXLUpstreamPort; =20 #endif /* CXL_SUP_H */ --=20 2.34.1 From nobody Sat Sep 6 14:41:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=samsung.com ARC-Seal: i=1; a=rsa-sha256; t=1756992089; cv=none; d=zohomail.com; s=zohoarc; b=UY7UkQVzsG+u9KHuFG1x6uWscNiPZjHWBM2gYqsp8jofvL/9bCL5n7jRn2MNTD/fpl2nLYZbLGnc4CwJHd8gb4qP5S665LIp5kFSeuL+BJXHLwlENJdL1GUgRhCGQHNGxB9PobhdvLCGuMEozJmsG92Ca06cIPtxzS1NMaDynZw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756992089; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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charset="utf-8" CMS-TYPE: 105P X-CPGSPASS: Y cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250904131944epcas5p351c0e073a975b1347c4a61aa0dd511f3 References: <20250904131904.725758-1-arpit1.kumar@samsung.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=203.254.224.34; envelope-from=arpit1.kumar@samsung.com; helo=mailout4.samsung.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @samsung.com) X-ZM-MESSAGEID: 1756992091129116600 -added assert-deassert PERST implementation for physical ports (both USP and DSP's). -assert PERST involves bg operation for holding 100ms. -reset PPB implementation for physical ports. Signed-off-by: Arpit Kumar --- hw/cxl/cxl-mailbox-utils.c | 138 ++++++++++++++++++++++ include/hw/cxl/cxl_device.h | 9 ++ include/hw/cxl/cxl_mailbox.h | 1 + include/hw/pci-bridge/cxl_upstream_port.h | 1 + 4 files changed, 149 insertions(+) diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index cb36880f0b..a0b76946a2 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -540,6 +540,120 @@ static CXLRetCode cmd_get_physical_port_state(const s= truct cxl_cmd *cmd, return CXL_MBOX_SUCCESS; } =20 +static void *bg_assertcb(void *opaque) +{ + CXLPhyPortPerst *perst =3D opaque; + + /* holding reset phase for 100ms */ + while (perst->asrt_time--) { + usleep(1000); + } + perst->issued_assert_perst =3D true; + return NULL; +} + +static CXLRetCode deassert_perst(Object *obj, uint8_t pn, CXLUpstreamPort = *pp) +{ + if (!pp->pports.perst[pn].issued_assert_perst) { + return CXL_MBOX_INTERNAL_ERROR; + } + + QEMU_LOCK_GUARD(&pp->pports.perst[pn].lock); + resettable_release_reset(obj, RESET_TYPE_COLD); + pp->pports.perst[pn].issued_assert_perst =3D false; + pp->pports.pport_info[pn].link_state_flags &=3D + ~LINK_STATE_FLAG_PERST_ASSERTED; + pp->pports.perst[pn].asrt_time =3D ASSERT_WAIT_TIME_MS; + + return CXL_MBOX_SUCCESS; +} + +static CXLRetCode assert_perst(Object *obj, uint8_t pn, CXLUpstreamPort *p= p) +{ + if (pp->pports.perst[pn].issued_assert_perst || + pp->pports.perst[pn].asrt_time < ASSERT_WAIT_TIME_MS) { + return CXL_MBOX_INTERNAL_ERROR; + } + + QEMU_LOCK_GUARD(&pp->pports.perst[pn].lock); + pp->pports.pport_info[pn].link_state_flags |=3D + LINK_STATE_FLAG_PERST_ASSERTED; + resettable_assert_reset(obj, RESET_TYPE_COLD); + qemu_thread_create(&pp->pports.perst[pn].asrt_thread, "assert_thread", + bg_assertcb, &pp->pports.perst[pn], QEMU_THREAD_DETACHED); + + return CXL_MBOX_SUCCESS; +} + +static struct PCIDevice *cxl_find_port_dev(uint8_t pn, CXLCCI *cci) +{ + CXLUpstreamPort *pp =3D CXL_USP(cci->d); + PCIBus *bus =3D &PCI_BRIDGE(cci->d)->sec_bus; + + if (pp->pports.pport_info[pn].current_port_config_state =3D=3D + CXL_PORT_CONFIG_STATE_USP) { + return pci_bridge_get_device(bus); + } + + if (pp->pports.pport_info[pn].current_port_config_state =3D=3D + CXL_PORT_CONFIG_STATE_DSP) { + return pcie_find_port_by_pn(bus, pn); + } + return NULL; +} + +/* CXL r3.2 Section 7.6.7.1.3: Get Physical Port Control (Opcode 5102h) */ +static CXLRetCode cmd_physical_port_control(const struct cxl_cmd *cmd, + uint8_t *payload_in, + size_t len_in, + uint8_t *payload_out, + size_t *len_out, + CXLCCI *cci) +{ + CXLUpstreamPort *pp =3D CXL_USP(cci->d); + PCIDevice *dev; + uint8_t pn; + uint8_t ret =3D CXL_MBOX_SUCCESS; + + struct cxl_fmapi_get_physical_port_control_req_pl { + uint8_t ppb_id; + uint8_t ports_op; + } QEMU_PACKED *in =3D (void *)payload_in; + + if (len_in < sizeof(*in)) { + return CXL_MBOX_INVALID_PAYLOAD_LENGTH; + } + + pn =3D in->ppb_id; + if (pp->pports.pport_info[pn].port_id !=3D pn) { + return CXL_MBOX_INTERNAL_ERROR; + } + + dev =3D cxl_find_port_dev(pn, cci); + if (!dev) { + return CXL_MBOX_INTERNAL_ERROR; + } + + switch (in->ports_op) { + case 0: + ret =3D assert_perst(OBJECT(&dev->qdev), pn, pp); + break; + case 1: + ret =3D deassert_perst(OBJECT(&dev->qdev), pn, pp); + break; + case 2: + if (pp->pports.perst[pn].issued_assert_perst || + pp->pports.perst[pn].asrt_time < ASSERT_WAIT_TIME_MS) { + return CXL_MBOX_INTERNAL_ERROR; + } + device_cold_reset(&dev->qdev); + break; + default: + return CXL_MBOX_INVALID_INPUT; + } + return ret; +} + /* CXL r3.1 Section 8.2.9.1.2: Background Operation Status (Opcode 0002h) = */ static CXLRetCode cmd_infostat_bg_op_sts(const struct cxl_cmd *cmd, uint8_t *payload_in, @@ -4781,6 +4895,8 @@ static const struct cxl_cmd cxl_cmd_set_usp_mctp[256]= [256] =3D { cmd_identify_switch_device, 0, 0 }, [PHYSICAL_SWITCH][GET_PHYSICAL_PORT_STATE] =3D { "SWITCH_PHYSICAL_PORT= _STATS", cmd_get_physical_port_state, ~0, 0 }, + [PHYSICAL_SWITCH][PHYSICAL_PORT_CONTROL] =3D { "SWITCH_PHYSICAL_PORT_C= ONTROL", + cmd_physical_port_control, 2, 0 }, [TUNNEL][MANAGEMENT_COMMAND] =3D { "TUNNEL_MANAGEMENT_COMMAND", cmd_tunnel_management_cmd, ~0, 0 }, }; @@ -4791,6 +4907,28 @@ void cxl_initialize_usp_mctpcci(CXLCCI *cci, DeviceS= tate *d, DeviceState *intf, cxl_copy_cci_commands(cci, cxl_cmd_set_usp_mctp); cci->d =3D d; cci->intf =3D intf; + CXLUpstreamPort *pp; + int pn =3D 0; cxl_init_cci(cci, payload_max); cxl_set_phy_port_info(cci); + /* physical port control */ + pp =3D CXL_USP(cci->d); + for (int byte_index =3D 0; byte_index < (CXL_MAX_PHY_PORTS / BITS_PER_= BYTE); + byte_index++) { + unsigned char byte =3D pp->pports.active_port_bitmask[byte_index]; + + for (int bit_index =3D 0; bit_index < 8; bit_index++, pn++) { + if (((byte) & (1 << bit_index)) !=3D 0) { + qemu_mutex_init(&pp->pports.perst[pn].lock); + pp->pports.perst[pn].issued_assert_perst =3D false; + /* + * Assert PERST involves physical port to be in + * hold reset phase for minimum 100ms. No other + * physcial port control requests are entertained + * until Deassert PERST command. + */ + pp->pports.perst[pn].asrt_time =3D ASSERT_WAIT_TIME_MS; + } + } + } } diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index 9fc720ec10..033d9bf11a 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -130,6 +130,7 @@ (1 << 16)) =20 #define CXL_MAX_PHY_PORTS 256 +#define ASSERT_WAIT_TIME_MS 100 /* Assert - Deassert PERST */ =20 /* physical port control info - CXL r3.2 table 7-19 */ #define CXL_PORT_CONFIG_STATE_DISABLED 0x0 @@ -196,6 +197,14 @@ typedef struct CXLPhyPortInfo { uint8_t supported_ld_count; } QEMU_PACKED CXLPhyPortInfo; =20 +/* Assert - Deassert PERST */ +typedef struct CXLPhyPortPerst { + bool issued_assert_perst; + QemuMutex lock; /* protecting assert-deassert reset request */ + uint64_t asrt_time; + QemuThread asrt_thread; /* thread for 100ms delay */ +} CXLPhyPortPerst; + /* CXL r3.1 Table 8-34: Command Return Codes */ typedef enum { CXL_MBOX_SUCCESS =3D 0x0, diff --git a/include/hw/cxl/cxl_mailbox.h b/include/hw/cxl/cxl_mailbox.h index 5c918c53a9..5c31023590 100644 --- a/include/hw/cxl/cxl_mailbox.h +++ b/include/hw/cxl/cxl_mailbox.h @@ -88,6 +88,7 @@ enum { PHYSICAL_SWITCH =3D 0x51, #define IDENTIFY_SWITCH_DEVICE 0x0 #define GET_PHYSICAL_PORT_STATE 0x1 + #define PHYSICAL_PORT_CONTROL 0X2 TUNNEL =3D 0x53, #define MANAGEMENT_COMMAND 0x0 MHD =3D 0x55, diff --git a/include/hw/pci-bridge/cxl_upstream_port.h b/include/hw/pci-bri= dge/cxl_upstream_port.h index 3b7e72bfe0..4b9da87d77 100644 --- a/include/hw/pci-bridge/cxl_upstream_port.h +++ b/include/hw/pci-bridge/cxl_upstream_port.h @@ -30,6 +30,7 @@ typedef struct CXLUpstreamPort { uint8_t num_ports; uint8_t active_port_bitmask[CXL_MAX_PHY_PORTS / BITS_PER_BYTE]; CXLPhyPortInfo pport_info[CXL_MAX_PHY_PORTS]; + CXLPhyPortPerst perst[CXL_MAX_PHY_PORTS]; } pports; } CXLUpstreamPort; =20 --=20 2.34.1