From nobody Sat Sep 6 17:18:29 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=yandex.ru ARC-Seal: i=1; a=rsa-sha256; t=1756906998; cv=none; d=zohomail.com; s=zohoarc; b=kdtX+puGgEnJ1Njs1aReVa58/sLg1fToyQDBwYZfZlFjQF6B7txT29vhNchTVKg4gSMysQSptk0ePdSdqDG6hw6kmvZf+PJ3/sZsDu2eabgocclXBc8kUptPQsg2g7u8WvmxLhdUxaxSfRLfSst70XemKL7+fjY1WN+raNwpSmM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756906998; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=O9hW0c4Ttcubk5ra00YW4qEl7dFasP/KlwU4xmJPyMw=; b=KPNhYAdHHhS0mGkbZ1Q11g4R7ZWiYR418plpunxEBV13KfhERfYMgI3y/Mw/frr5CefDIuPcjPMpCZ46sOsPpQcgdKOsELOwF5V/m/7AV9STVYDDo6uTlda4eUIAqGzKijpSBiREvsfU6MWm/ukN5B/NJCo4gsxuTBXvVgkWfjQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756906998327231.65262639983666; Wed, 3 Sep 2025 06:43:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1utnkT-00067S-8P; Wed, 03 Sep 2025 09:42:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1utnkP-00062g-Ec; Wed, 03 Sep 2025 09:42:01 -0400 Received: from forward103a.mail.yandex.net ([178.154.239.86]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1utnkJ-0007FN-Nc; Wed, 03 Sep 2025 09:42:01 -0400 Received: from mail-nwsmtp-smtp-production-main-54.vla.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-54.vla.yp-c.yandex.net [IPv6:2a02:6b8:c0d:400:0:640:80de:0]) by forward103a.mail.yandex.net (Yandex) with ESMTPS id E3F058075E; Wed, 03 Sep 2025 16:41:50 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-54.vla.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id kfgPGGxM54Y0-eeW9awNq; Wed, 03 Sep 2025 16:41:50 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=yandex.ru; s=mail; t=1756906910; bh=O9hW0c4Ttcubk5ra00YW4qEl7dFasP/KlwU4xmJPyMw=; h=Message-ID:Date:In-Reply-To:Cc:Subject:References:To:From; b=duYnDuEjm+qrj3fzvDH8s/Z71dWOPFBXXSKImmwF9MEy8ORSMu6NUOunvHVR8sb5T 4ZjTyqQpM3U5orhKbGV0kJ8NR+bU7yRIDlkWq9N2wNrZVOGNoINozBnKRA53dW0uof dn2zx6k6n+NM03yEes4vB7kPglShiVmjfBX0cpKI= Authentication-Results: mail-nwsmtp-smtp-production-main-54.vla.yp-c.yandex.net; dkim=pass header.i=@yandex.ru From: Danila Zhebryakov To: qemu-devel@nongnu.org Cc: Laurent Vivier , David Hildenbrand , Richard Henderson , Thomas Huth , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Ilya Leoshkevich , Nicholas Piggin , Chinmay Rath , Paolo Bonzini , Riku Voipio , Danila Zhebryakov Subject: [PATCH v2 2/4] target/ppc: refactor MMU helpers Date: Wed, 3 Sep 2025 16:41:44 +0300 Message-ID: <20250903134146.1487794-3-d.zhebryakov@yandex.ru> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250903134146.1487794-1-d.zhebryakov@yandex.ru> References: <20250903134146.1487794-1-d.zhebryakov@yandex.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=178.154.239.86; envelope-from=d.zhebryakov@yandex.ru; helo=forward103a.mail.yandex.net X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @yandex.ru) X-ZM-MESSAGEID: 1756907001133116600 Content-Type: text/plain; charset="utf-8" Changed most of the PPC MMU helpers to take CPUTLBEntryFull* instead of poi= nters to real address, prot and size. This is needed at least for booke206 MMU to support LE bits (which need to = set TLB_BSWAP in tlb_fill_flags), but also seems reasonable to do to other = MMUs for consistency. This should not change any behavior at all. Signed-off-by: Danila Zhebryakov --- target/ppc/internal.h | 3 +- target/ppc/mmu-booke.c | 63 +++++++++++++++++---------------- target/ppc/mmu-booke.h | 2 +- target/ppc/mmu-hash32.c | 30 +++++++++------- target/ppc/mmu-hash32.h | 3 +- target/ppc/mmu-hash64.c | 14 ++++---- target/ppc/mmu-hash64.h | 2 +- target/ppc/mmu-radix64.c | 20 +++++++---- target/ppc/mmu-radix64.h | 2 +- target/ppc/mmu_common.c | 75 ++++++++++++++++++++-------------------- target/ppc/mmu_helper.c | 15 ++++---- 11 files changed, 121 insertions(+), 108 deletions(-) diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 7723350227..81f9a9f2cf 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -246,8 +246,7 @@ static inline int check_prot_access_type(int prot, MMUA= ccessType access_type) /* PowerPC MMU emulation */ =20 bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type, - hwaddr *raddrp, int *psizep, int *protp, - int mmu_idx, bool guest_visible); + CPUTLBEntryFull *full, int mmu_idx, bool guest_visible); =20 /* Software driven TLB helpers */ int ppc6xx_tlb_getnum(CPUPPCState *env, target_ulong eaddr, diff --git a/target/ppc/mmu-booke.c b/target/ppc/mmu-booke.c index 55e5dd7c6b..10ba8052d4 100644 --- a/target/ppc/mmu-booke.c +++ b/target/ppc/mmu-booke.c @@ -23,6 +23,7 @@ #include "cpu.h" #include "internal.h" #include "mmu-booke.h" +#include "exec/tlb-flags.h" =20 /* Generic TLB check function for embedded PowerPC implementations */ static bool ppcemb_tlb_check(CPUPPCState *env, ppcemb_tlb_t *tlb, @@ -155,10 +156,10 @@ static bool mmubooke_check_pid(CPUPPCState *env, ppce= mb_tlb_t *tlb, } =20 static int mmubooke_check_tlb(CPUPPCState *env, ppcemb_tlb_t *tlb, - hwaddr *raddr, int *prot, target_ulong addre= ss, + CPUTLBEntryFull *full, target_ulong address, MMUAccessType access_type, int i) { - if (!mmubooke_check_pid(env, tlb, raddr, address, i)) { + if (!mmubooke_check_pid(env, tlb, &(full->phys_addr), address, i)) { qemu_log_mask(CPU_LOG_MMU, "%s: TLB entry not found\n", __func__); return -1; } @@ -172,21 +173,22 @@ static int mmubooke_check_tlb(CPUPPCState *env, ppcem= b_tlb_t *tlb, } =20 if (FIELD_EX64(env->msr, MSR, PR)) { - *prot =3D tlb->prot & 0xF; + full->prot =3D tlb->prot & 0xF; } else { - *prot =3D (tlb->prot >> 4) & 0xF; + full->prot =3D (tlb->prot >> 4) & 0xF; } - if (check_prot_access_type(*prot, access_type)) { + if (check_prot_access_type(full->prot, access_type)) { qemu_log_mask(CPU_LOG_MMU, "%s: good TLB!\n", __func__); return 0; } =20 - qemu_log_mask(CPU_LOG_MMU, "%s: no prot match: %x\n", __func__, *prot); + qemu_log_mask(CPU_LOG_MMU, "%s: no prot match: %x\n", __func__, full->= prot); return access_type =3D=3D MMU_INST_FETCH ? -3 : -2; } =20 -static int mmubooke_get_physical_address(CPUPPCState *env, hwaddr *raddr, - int *prot, target_ulong address, +static int mmubooke_get_physical_address(CPUPPCState *env, + CPUTLBEntryFull *full, + target_ulong address, MMUAccessType access_type) { ppcemb_tlb_t *tlb; @@ -194,7 +196,7 @@ static int mmubooke_get_physical_address(CPUPPCState *e= nv, hwaddr *raddr, =20 for (i =3D 0; i < env->nb_tlb; i++) { tlb =3D &env->tlb.tlbe[i]; - ret =3D mmubooke_check_tlb(env, tlb, raddr, prot, address, + ret =3D mmubooke_check_tlb(env, tlb, full, address, access_type, i); if (ret !=3D -1) { break; @@ -203,7 +205,8 @@ static int mmubooke_get_physical_address(CPUPPCState *e= nv, hwaddr *raddr, qemu_log_mask(CPU_LOG_MMU, "%s: access %s " TARGET_FMT_lx " =3D> " HWADDR_FMT_plx " %d %d\n", __func__, ret < 0 ? "refused" : "granted", - address, ret < 0 ? -1 : *raddr, ret =3D=3D -1 ? 0 : *pro= t, ret); + address, ret < 0 ? -1 : full->phys_addr, + ret =3D=3D -1 ? 0 : full->prot, ret); return ret; } =20 @@ -307,8 +310,7 @@ static bool mmubooke206_get_as(CPUPPCState *env, =20 /* Check if the tlb found by hashing really matches */ static int mmubooke206_check_tlb(CPUPPCState *env, ppcmas_tlb_t *tlb, - hwaddr *raddr, int *prot, - target_ulong address, + CPUTLBEntryFull *full, target_ulong addre= ss, MMUAccessType access_type, int mmu_idx) { uint32_t epid; @@ -316,24 +318,25 @@ static int mmubooke206_check_tlb(CPUPPCState *env, pp= cmas_tlb_t *tlb, bool use_epid =3D mmubooke206_get_as(env, mmu_idx, &epid, &as, &pr); =20 if (!use_epid) { - if (ppcmas_tlb_check(env, tlb, raddr, address, + if (ppcmas_tlb_check(env, tlb, &(full->phys_addr), address, env->spr[SPR_BOOKE_PID]) >=3D 0) { goto found_tlb; } =20 if (env->spr[SPR_BOOKE_PID1] && - ppcmas_tlb_check(env, tlb, raddr, address, + ppcmas_tlb_check(env, tlb, &(full->phys_addr), address, env->spr[SPR_BOOKE_PID1]) >=3D 0) { goto found_tlb; } =20 if (env->spr[SPR_BOOKE_PID2] && - ppcmas_tlb_check(env, tlb, raddr, address, + ppcmas_tlb_check(env, tlb, &(full->phys_addr), address, env->spr[SPR_BOOKE_PID2]) >=3D 0) { goto found_tlb; } } else { - if (ppcmas_tlb_check(env, tlb, raddr, address, epid) >=3D 0) { + if (ppcmas_tlb_check(env, tlb, &(full->phys_addr), + address, epid) >=3D 0) { goto found_tlb; } } @@ -356,7 +359,9 @@ found_tlb: return -1; } =20 + uint8_t *prot =3D &(full->prot); *prot =3D 0; + if (pr) { if (tlb->mas7_3 & MAS3_UR) { *prot |=3D PAGE_READ; @@ -387,8 +392,9 @@ found_tlb: return access_type =3D=3D MMU_INST_FETCH ? -3 : -2; } =20 -static int mmubooke206_get_physical_address(CPUPPCState *env, hwaddr *radd= r, - int *prot, target_ulong addres= s, +static int mmubooke206_get_physical_address(CPUPPCState *env, + CPUTLBEntryFull *full, + target_ulong address, MMUAccessType access_type, int mmu_idx) { @@ -402,7 +408,7 @@ static int mmubooke206_get_physical_address(CPUPPCState= *env, hwaddr *raddr, if (!tlb) { continue; } - ret =3D mmubooke206_check_tlb(env, tlb, raddr, prot, address, + ret =3D mmubooke206_check_tlb(env, tlb, full, address, access_type, mmu_idx); if (ret !=3D -1) { goto found_tlb; @@ -415,7 +421,8 @@ found_tlb: qemu_log_mask(CPU_LOG_MMU, "%s: access %s " TARGET_FMT_lx " =3D> " HWADDR_FMT_plx " %d %d\n", __func__, ret < 0 ? "refused" : "granted", address, - ret < 0 ? -1 : *raddr, ret =3D=3D -1 ? 0 : *prot, ret); + ret < 0 ? -1 : full->phys_addr, + ret =3D=3D -1 ? 0 : full->prot, ret); return ret; } =20 @@ -474,27 +481,25 @@ static void booke206_update_mas_tlb_miss(CPUPPCState = *env, target_ulong address, } =20 bool ppc_booke_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_ty= pe, - hwaddr *raddrp, int *psizep, int *protp, int mmu_idx, + CPUTLBEntryFull *full, int mmu_idx, bool guest_visible) { CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; - hwaddr raddr; - int prot, ret; + int ret; =20 if (env->mmu_model =3D=3D POWERPC_MMU_BOOKE206) { - ret =3D mmubooke206_get_physical_address(env, &raddr, &prot, eaddr, + ret =3D mmubooke206_get_physical_address(env, full, eaddr, access_type, mmu_idx); } else { - ret =3D mmubooke_get_physical_address(env, &raddr, &prot, eaddr, - access_type); + ret =3D mmubooke_get_physical_address(env, full, eaddr, access_typ= e); } if (ret =3D=3D 0) { - *raddrp =3D raddr; - *protp =3D prot; - *psizep =3D TARGET_PAGE_BITS; + full->lg_page_size =3D TARGET_PAGE_BITS; return true; } else if (!guest_visible) { + full->prot =3D 0; + full->phys_addr =3D 0; return false; } =20 diff --git a/target/ppc/mmu-booke.h b/target/ppc/mmu-booke.h index f972843bbb..4d15ddd176 100644 --- a/target/ppc/mmu-booke.h +++ b/target/ppc/mmu-booke.h @@ -11,7 +11,7 @@ hwaddr booke206_tlb_to_page_size(CPUPPCState *env, ppcmas= _tlb_t *tlb); int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb, hwaddr *raddrp, target_ulong address, uint32_t pid); bool ppc_booke_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_ty= pe, - hwaddr *raddrp, int *psizep, int *protp, int mmu_idx, + CPUTLBEntryFull *full, int mmu_idx, bool guest_visible); =20 #endif diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c index 8b980a5aa9..469ebbc883 100644 --- a/target/ppc/mmu-hash32.c +++ b/target/ppc/mmu-hash32.c @@ -292,7 +292,7 @@ static hwaddr ppc_hash32_htab_lookup(PowerPCCPU *cpu, } =20 bool ppc_hash32_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_t= ype, - hwaddr *raddrp, int *psizep, int *protp, int mmu_idx, + CPUTLBEntryFull *full, int mmu_idx, bool guest_visible) { CPUState *cs =3D CPU(cpu); @@ -301,24 +301,26 @@ bool ppc_hash32_xlate(PowerPCCPU *cpu, vaddr eaddr, M= MUAccessType access_type, hwaddr pte_offset, raddr; ppc_hash_pte32_t pte; bool key; - int prot; + int prot =3D 0; =20 /* There are no hash32 large pages. */ - *psizep =3D TARGET_PAGE_BITS; + full->lg_page_size =3D TARGET_PAGE_BITS; =20 /* 1. Handle real mode accesses */ if (mmuidx_real(mmu_idx)) { /* Translation is off */ - *raddrp =3D eaddr; - *protp =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + full->phys_addr =3D eaddr; + full->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; return true; } =20 /* 2. Check Block Address Translation entries (BATs) */ if (env->nb_BATs !=3D 0) { - raddr =3D ppc_hash32_bat_lookup(cpu, eaddr, access_type, protp, mm= u_idx); + raddr =3D ppc_hash32_bat_lookup(cpu, eaddr, access_type, &prot, mm= u_idx); + full->prot =3D prot; + if (raddr !=3D -1) { - if (!check_prot_access_type(*protp, access_type)) { + if (!check_prot_access_type(full->prot, access_type)) { if (guest_visible) { if (access_type =3D=3D MMU_INST_FETCH) { cs->exception_index =3D POWERPC_EXCP_ISI; @@ -336,7 +338,7 @@ bool ppc_hash32_xlate(PowerPCCPU *cpu, vaddr eaddr, MMU= AccessType access_type, } return false; } - *raddrp =3D raddr; + full->phys_addr =3D raddr; return true; } } @@ -347,7 +349,9 @@ bool ppc_hash32_xlate(PowerPCCPU *cpu, vaddr eaddr, MMU= AccessType access_type, /* 4. Handle direct store segments */ if (sr & SR32_T) { return ppc_hash32_direct_store(cpu, sr, eaddr, access_type, - raddrp, protp, mmu_idx, guest_visib= le); + &(full->phys_addr), &prot, mmu_idx, + guest_visible); + full->prot =3D prot; } =20 /* 5. Check for segment level no-execute violation */ @@ -425,11 +429,11 @@ bool ppc_hash32_xlate(PowerPCCPU *cpu, vaddr eaddr, M= MUAccessType access_type, prot &=3D ~PAGE_WRITE; } } - *protp =3D prot; + full->prot =3D prot; =20 /* 9. Determine the real address from the PTE */ - *raddrp =3D pte.pte1 & HPTE32_R_RPN; - *raddrp &=3D TARGET_PAGE_MASK; - *raddrp |=3D eaddr & ~TARGET_PAGE_MASK; + full->phys_addr =3D pte.pte1 & HPTE32_R_RPN; + full->phys_addr &=3D TARGET_PAGE_MASK; + full->phys_addr |=3D eaddr & ~TARGET_PAGE_MASK; return true; } diff --git a/target/ppc/mmu-hash32.h b/target/ppc/mmu-hash32.h index 04c23ea75e..dd9da7729b 100644 --- a/target/ppc/mmu-hash32.h +++ b/target/ppc/mmu-hash32.h @@ -6,8 +6,7 @@ #include "system/memory.h" =20 bool ppc_hash32_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_t= ype, - hwaddr *raddrp, int *psizep, int *protp, int mmu_idx, - bool guest_visible); + CPUTLBEntryFull *full, int mmu_idx, bool guest_visib= le); =20 /* * Segment register definitions diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index dd337558aa..2927be8144 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -980,7 +980,7 @@ static int build_vrma_slbe(PowerPCCPU *cpu, ppc_slb_t *= slb) } =20 bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_t= ype, - hwaddr *raddrp, int *psizep, int *protp, int mmu_idx, + CPUTLBEntryFull *full, int mmu_idx, bool guest_visible) { CPUState *cs =3D CPU(cpu); @@ -1063,9 +1063,9 @@ bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, M= MUAccessType access_type, raddr |=3D env->spr[SPR_RMOR]; } =20 - *raddrp =3D raddr; - *protp =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - *psizep =3D TARGET_PAGE_BITS; + full->phys_addr =3D raddr; + full->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + full->lg_page_size =3D TARGET_PAGE_BITS; return true; } =20 @@ -1201,9 +1201,9 @@ bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, M= MUAccessType access_type, =20 /* 7. Determine the real address from the PTE */ =20 - *raddrp =3D deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, eaddr); - *protp =3D prot; - *psizep =3D apshift; + full->phys_addr =3D deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, ead= dr); + full->prot =3D prot; + full->lg_page_size =3D apshift; return true; } =20 diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h index ae8d4b37ae..8e51b220a8 100644 --- a/target/ppc/mmu-hash64.h +++ b/target/ppc/mmu-hash64.h @@ -8,7 +8,7 @@ void dump_slb(PowerPCCPU *cpu); int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot, target_ulong esid, target_ulong vsid); bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_t= ype, - hwaddr *raddrp, int *psizep, int *protp, int mmu_idx, + CPUTLBEntryFull *full, int mmu_idx, bool guest_visible); void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong pte_index, diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c index 33ac341290..b358f724e3 100644 --- a/target/ppc/mmu-radix64.c +++ b/target/ppc/mmu-radix64.c @@ -820,20 +820,26 @@ static bool ppc_radix64_xlate_impl(PowerPCCPU *cpu, v= addr eaddr, } =20 bool ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_= type, - hwaddr *raddrp, int *psizep, int *protp, int mmu_id= x, + CPUTLBEntryFull *full, int mmu_idx, bool guest_visible) { - bool ret =3D ppc_radix64_xlate_impl(cpu, eaddr, access_type, raddrp, - psizep, protp, mmu_idx, guest_visibl= e); + int prot =3D 0, psize =3D 0; + hwaddr raddr =3D 0; + bool ret =3D ppc_radix64_xlate_impl(cpu, eaddr, access_type, &raddr, + &psize, &prot, mmu_idx, guest_visibl= e); + + full->phys_addr =3D raddr; + full->prot =3D prot; + full->lg_page_size =3D psize; =20 qemu_log_mask(CPU_LOG_MMU, "%s for %s @0x%"VADDR_PRIx " mmu_idx %u (prot %c%c%c) -> 0x%"HWADDR_PRIx"\n", __func__, access_str(access_type), eaddr, mmu_idx, - *protp & PAGE_READ ? 'r' : '-', - *protp & PAGE_WRITE ? 'w' : '-', - *protp & PAGE_EXEC ? 'x' : '-', - *raddrp); + prot & PAGE_READ ? 'r' : '-', + prot & PAGE_WRITE ? 'w' : '-', + prot & PAGE_EXEC ? 'x' : '-', + raddr); =20 return ret; } diff --git a/target/ppc/mmu-radix64.h b/target/ppc/mmu-radix64.h index 6620b3d648..ef7a125efe 100644 --- a/target/ppc/mmu-radix64.h +++ b/target/ppc/mmu-radix64.h @@ -15,7 +15,7 @@ #define R_EADDR_QUADRANT3 0xC000000000000000 =20 bool ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_= type, - hwaddr *raddr, int *psizep, int *protp, int mmu_idx, + CPUTLBEntryFull *full, int mmu_idx, bool guest_visible); =20 #endif /* TARGET_PPC64 */ diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index 52d48615ac..6ec74e61e8 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -85,7 +85,7 @@ int ppc6xx_tlb_getnum(CPUPPCState *env, target_ulong eadd= r, =20 /* Software driven TLB helpers */ =20 -static int ppc6xx_tlb_check(CPUPPCState *env, hwaddr *raddr, int *prot, +static int ppc6xx_tlb_check(CPUPPCState *env, hwaddr *raddr, uint8_t *prot, target_ulong eaddr, MMUAccessType access_type, target_ulong ptem, bool key, bool nx) { @@ -187,7 +187,7 @@ static int ppc6xx_tlb_check(CPUPPCState *env, hwaddr *r= addr, int *prot, return ret; } =20 -static int get_bat_6xx_tlb(CPUPPCState *env, hwaddr *raddr, int *prot, +static int get_bat_6xx_tlb(CPUPPCState *env, hwaddr *raddr, uint8_t *prot, target_ulong eaddr, MMUAccessType access_type, bool pr) { @@ -259,7 +259,7 @@ static int get_bat_6xx_tlb(CPUPPCState *env, hwaddr *ra= ddr, int *prot, } =20 static int mmu6xx_get_physical_address(CPUPPCState *env, hwaddr *raddr, - int *prot, target_ulong eaddr, + uint8_t *prot, target_ulong eaddr, hwaddr *hashp, bool *keyp, MMUAccessType access_type, int type) { @@ -583,15 +583,15 @@ void dump_mmu(CPUPPCState *env) =20 static bool ppc_real_mode_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type, - hwaddr *raddrp, int *psizep, int *protp) + CPUTLBEntryFull *full) { CPUPPCState *env =3D &cpu->env; =20 if (access_type =3D=3D MMU_INST_FETCH ? !FIELD_EX64(env->msr, MSR, IR) : !FIELD_EX64(env->msr, MSR, DR)) { - *raddrp =3D eaddr; - *protp =3D PAGE_RWX; - *psizep =3D TARGET_PAGE_BITS; + full->phys_addr =3D eaddr; + full->prot =3D PAGE_RWX; + full->lg_page_size =3D TARGET_PAGE_BITS; return true; } else if (env->mmu_model =3D=3D POWERPC_MMU_REAL) { cpu_abort(CPU(cpu), "PowerPC in real mode shold not do translation= \n"); @@ -600,21 +600,24 @@ static bool ppc_real_mode_xlate(PowerPCCPU *cpu, vadd= r eaddr, } =20 static bool ppc_40x_xlate(PowerPCCPU *cpu, vaddr eaddr, - MMUAccessType access_type, - hwaddr *raddrp, int *psizep, int *protp, + MMUAccessType access_type, CPUTLBEntryFull *full, int mmu_idx, bool guest_visible) { CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; int ret; =20 - if (ppc_real_mode_xlate(cpu, eaddr, access_type, raddrp, psizep, protp= )) { + if (ppc_real_mode_xlate(cpu, eaddr, access_type, full)) { return true; } =20 - ret =3D mmu40x_get_physical_address(env, raddrp, protp, eaddr, access_= type); + int prot =3D 0; + ret =3D mmu40x_get_physical_address(env, &(full->phys_addr), &prot, + eaddr, access_type); + full->prot =3D prot; + if (ret =3D=3D 0) { - *psizep =3D TARGET_PAGE_BITS; + full->lg_page_size =3D TARGET_PAGE_BITS; return true; } else if (!guest_visible) { return false; @@ -668,8 +671,7 @@ static bool ppc_40x_xlate(PowerPCCPU *cpu, vaddr eaddr, } =20 static bool ppc_6xx_xlate(PowerPCCPU *cpu, vaddr eaddr, - MMUAccessType access_type, - hwaddr *raddrp, int *psizep, int *protp, + MMUAccessType access_type, CPUTLBEntryFull *full, int mmu_idx, bool guest_visible) { CPUState *cs =3D CPU(cpu); @@ -678,7 +680,7 @@ static bool ppc_6xx_xlate(PowerPCCPU *cpu, vaddr eaddr, bool key; int type, ret; =20 - if (ppc_real_mode_xlate(cpu, eaddr, access_type, raddrp, psizep, protp= )) { + if (ppc_real_mode_xlate(cpu, eaddr, access_type, full)) { return true; } =20 @@ -692,10 +694,10 @@ static bool ppc_6xx_xlate(PowerPCCPU *cpu, vaddr eadd= r, type =3D ACCESS_INT; } =20 - ret =3D mmu6xx_get_physical_address(env, raddrp, protp, eaddr, &hash, = &key, - access_type, type); + ret =3D mmu6xx_get_physical_address(env, &(full->phys_addr), &(full->p= rot), + eaddr, &hash, &key, access_type, typ= e); if (ret =3D=3D 0) { - *psizep =3D TARGET_PAGE_BITS; + full->lg_page_size =3D TARGET_PAGE_BITS; return true; } else if (!guest_visible) { return false; @@ -806,15 +808,14 @@ tlb_miss: /*************************************************************************= ****/ =20 bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type, - hwaddr *raddrp, int *psizep, int *protp, - int mmu_idx, bool guest_visible) + CPUTLBEntryFull *full, int mmu_idx, bool guest_visible) { switch (cpu->env.mmu_model) { #if defined(TARGET_PPC64) case POWERPC_MMU_3_00: if (ppc64_v3_radix(cpu)) { - return ppc_radix64_xlate(cpu, eaddr, access_type, raddrp, - psizep, protp, mmu_idx, guest_visible= ); + return ppc_radix64_xlate(cpu, eaddr, access_type, + full, mmu_idx, guest_visible); } /* fall through */ case POWERPC_MMU_64B: @@ -822,25 +823,24 @@ bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAcces= sType access_type, case POWERPC_MMU_2_06: case POWERPC_MMU_2_07: return ppc_hash64_xlate(cpu, eaddr, access_type, - raddrp, psizep, protp, mmu_idx, guest_visi= ble); + full, mmu_idx, guest_visible); #endif =20 case POWERPC_MMU_32B: - return ppc_hash32_xlate(cpu, eaddr, access_type, raddrp, - psizep, protp, mmu_idx, guest_visible); + return ppc_hash32_xlate(cpu, eaddr, access_type, full, + mmu_idx, guest_visible); case POWERPC_MMU_BOOKE: case POWERPC_MMU_BOOKE206: - return ppc_booke_xlate(cpu, eaddr, access_type, raddrp, - psizep, protp, mmu_idx, guest_visible); + return ppc_booke_xlate(cpu, eaddr, access_type, + full, mmu_idx, guest_visible); case POWERPC_MMU_SOFT_4xx: - return ppc_40x_xlate(cpu, eaddr, access_type, raddrp, - psizep, protp, mmu_idx, guest_visible); + return ppc_40x_xlate(cpu, eaddr, access_type, + full, mmu_idx, guest_visible); case POWERPC_MMU_SOFT_6xx: - return ppc_6xx_xlate(cpu, eaddr, access_type, raddrp, - psizep, protp, mmu_idx, guest_visible); + return ppc_6xx_xlate(cpu, eaddr, access_type, + full, mmu_idx, guest_visible); case POWERPC_MMU_REAL: - return ppc_real_mode_xlate(cpu, eaddr, access_type, raddrp, psizep, - protp); + return ppc_real_mode_xlate(cpu, eaddr, access_type, full); case POWERPC_MMU_MPC8xx: cpu_abort(env_cpu(&cpu->env), "MPC8xx MMU model is not implemented= \n"); default: @@ -851,19 +851,18 @@ bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAcces= sType access_type, hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); - hwaddr raddr; - int s, p; + CPUTLBEntryFull full; =20 /* * Some MMUs have separate TLBs for code and data. If we only * try an MMU_DATA_LOAD, we may not be able to read instructions * mapped by code TLBs, so we also try a MMU_INST_FETCH. */ - if (ppc_xlate(cpu, addr, MMU_DATA_LOAD, &raddr, &s, &p, + if (ppc_xlate(cpu, addr, MMU_DATA_LOAD, &full, ppc_env_mmu_index(&cpu->env, false), false) || - ppc_xlate(cpu, addr, MMU_INST_FETCH, &raddr, &s, &p, + ppc_xlate(cpu, addr, MMU_INST_FETCH, &full, ppc_env_mmu_index(&cpu->env, true), false)) { - return raddr & TARGET_PAGE_MASK; + return full.phys_addr & TARGET_PAGE_MASK; } return -1; } diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index ac60705402..85815196eb 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -1363,13 +1363,14 @@ bool ppc_cpu_tlb_fill(CPUState *cs, vaddr eaddr, in= t size, bool probe, uintptr_t retaddr) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); - hwaddr raddr; - int page_size, prot; - - if (ppc_xlate(cpu, eaddr, access_type, &raddr, - &page_size, &prot, mmu_idx, !probe)) { - tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MAS= K, - prot, mmu_idx, 1UL << page_size); + CPUTLBEntryFull full =3D { + .attrs =3D MEMTXATTRS_UNSPECIFIED + }; + + if (ppc_xlate(cpu, eaddr, access_type, + &full, mmu_idx, !probe)) { + full.phys_addr &=3D TARGET_PAGE_MASK; + tlb_set_page_full(cs, mmu_idx, eaddr & TARGET_PAGE_MASK, &full); return true; } if (probe) { --=20 2.47.2