From nobody Sat Sep 6 17:21:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756889407163117.81299462924153; Wed, 3 Sep 2025 01:50:07 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1utjAZ-0003Ld-GH; Wed, 03 Sep 2025 04:48:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1utjAW-0003Ja-VL for qemu-devel@nongnu.org; Wed, 03 Sep 2025 04:48:41 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1utjAU-0007NQ-RJ for qemu-devel@nongnu.org; Wed, 03 Sep 2025 04:48:40 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8BxH9PkALhoKycGAA--.12671S3; Wed, 03 Sep 2025 16:48:36 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJDxbMHcALhoc916AA--.5293S7; Wed, 03 Sep 2025 16:48:35 +0800 (CST) From: Bibo Mao To: Song Gao , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v3 05/12] target/loongarch: Fix page size set issue with CSR_STLBPS Date: Wed, 3 Sep 2025 16:48:20 +0800 Message-Id: <20250903084827.3085911-6-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250903084827.3085911-1-maobibo@loongson.cn> References: <20250903084827.3085911-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJDxbMHcALhoc916AA--.5293S7 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1756889408952124100 Content-Type: text/plain; charset="utf-8" When modify register CSR_STLBPS, the page size should come from input parameter rather than old value. Signed-off-by: Bibo Mao --- target/loongarch/cpu-csr.h | 1 + target/loongarch/tcg/csr_helper.c | 5 +++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h index 0834e91f30..1a311bf06a 100644 --- a/target/loongarch/cpu-csr.h +++ b/target/loongarch/cpu-csr.h @@ -106,6 +106,7 @@ FIELD(CSR_PWCH, DIR4_WIDTH, 18, 6) =20 #define LOONGARCH_CSR_STLBPS 0x1e /* Stlb page size */ FIELD(CSR_STLBPS, PS, 0, 5) +FIELD(CSR_STLBPS, RESERVE, 5, 27) =20 #define LOONGARCH_CSR_RVACFG 0x1f /* Reduced virtual address confi= g */ FIELD(CSR_RVACFG, RBITS, 0, 4) diff --git a/target/loongarch/tcg/csr_helper.c b/target/loongarch/tcg/csr_h= elper.c index 0d99e2c92b..eb60fefa82 100644 --- a/target/loongarch/tcg/csr_helper.c +++ b/target/loongarch/tcg/csr_helper.c @@ -26,13 +26,14 @@ target_ulong helper_csrwr_stlbps(CPULoongArchState *env= , target_ulong val) * The real hardware only supports the min tlb_ps is 12 * tlb_ps=3D0 may cause undefined-behavior. */ - uint8_t tlb_ps =3D FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS); + uint8_t tlb_ps =3D FIELD_EX64(val, CSR_STLBPS, PS); if (!check_ps(env, tlb_ps)) { qemu_log_mask(LOG_GUEST_ERROR, "Attempted set ps %d\n", tlb_ps); } else { /* Only update PS field, reserved bit keeps zero */ - env->CSR_STLBPS =3D FIELD_DP64(old_v, CSR_STLBPS, PS, tlb_ps); + val =3D FIELD_DP64(val, CSR_STLBPS, RESERVE, 0); + env->CSR_STLBPS =3D val; } =20 return old_v; --=20 2.39.3