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[123.253.189.97]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2490370298dsm149002635ad.4.2025.09.02.21.25.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Sep 2025 21:25:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1756873533; x=1757478333; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Y8yvSBFdg6/w+t6lod7oj6WNKUXqjZ+id/3TLdUhnCs=; b=L4bsZ8I442jDydCuXwfsVf9YCbGA5i198oZhVjT92kgD1zM0Fm1LMsIMg0Ui1fWu4T KVSvN/yKPPA0HaEXBYGh2gap/mMcv/H+V3FbHq6+FQk0ICFCmhUU/BiB7mfoOPF1hQjy 11XYlLHJ8XZhu49arpvhbMwyQ/sNlBOfseN+1LroY6rtn8dECWZYUsqJKPnr8YHlm98J QDnDXY/+IV577rHaxaxgeIaUf3/Z9TWZQ8Ui19FUcVxKfiuN1oJzIooWwKeQ2NFwDAbI rrPt6T0uWOAR16UWSavTNGYD5y8DA5/QLN6fZMsqnVmxqWXOI+1XyMmge1eYYZcffrfS o08w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756873533; x=1757478333; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Y8yvSBFdg6/w+t6lod7oj6WNKUXqjZ+id/3TLdUhnCs=; b=dPHX1Z4e9MwXsjq7HKAH9jlTnlcNDac8hqqz4UdzMXCtqDWRpsARoD4oEywFQfyGwM lbDoD1VSNLCgf4MvEheKpUZskC3ftWHnysrUFhtePH0WDryjDDR2YWV5+XRAZLMnjn+c 9Caj+2tptz7vOVw+hLIvLW2wfN6bc5kLszg9dZ/OoO2c62fkezwdUJQAgp5jmE0PIHCZ 3PG7XwDtnwRrK2JTep1EpLTl/CSMNmhNLXMtW6t+QQ2gh7ZzT2t4boyASZ9+3SmXoM8K GBF8M8TBqH4qYIWIXZCx1PyIten7Iq2tcWyAtFFKFW+meS+SsdPxEfqX5ntDPVIK9oCc 5nmA== X-Forwarded-Encrypted: i=1; AJvYcCV/yarPALllg+bQj0k8bRb15zC0SYxZH2lWOnm7l5tsG4My37ipXQQUNQQmYJNHXadRjwCOsI7Rp4FH@nongnu.org X-Gm-Message-State: AOJu0YyuGIJMStMcIJi12mZVNlcuJWXq5D1dWS8GFoSGFzUKkK6KKzQ3 xRL8rQVsjnqf25ovX/44OfkxUSN2QvybsRiiLKuy8mFNR8M29J18lCV8wuDcHQ== X-Gm-Gg: ASbGncsIuj23riV5fI7gdueggfxpJ4M/oR6UBYmNzWC7tcIQyTG2C7x4kGVAoRbh0DB LGU1kj48XWdlvokHTLUyppHpya+CkcEr0YcNTbXd4fi8pzaE7GgYtWyXs9gF1kRW3AFgLlzwKOW u7lBAVq9Vl2moJuDsGQNb9/9caD392mjSqrQaHf3iNI/JvfjucmOinUGeP8KArc/1EXS9l9aO72 wGj/jkzCfFQNFTNf4A9L9VLVeCCDMMFnQfLanOF2ZPc3/XOwSfPQu050On0s/CSP6pXbFucdrIR 6B9USWOtsy1sLknKcqGFa5yi5Qej6fCFbfM7kbfr4lkTEyjWtjRpTxT8CLIoYYV4cc4ffmEzP8V VaVGACcXx58x6MCFH1SNNpBW62fCgAT5qArfm+7jpFloJPWCZkLv4NJqFJ6DbYcM5tS/1qLsd5z rH743nT5Vg X-Google-Smtp-Source: AGHT+IHtuNwOvoBTT5SGZuqpaQC5EEEJbEf96E99MlGiBH2A6KyQ273VgYmw344Uu5pp1SIs5XtHvQ== X-Received: by 2002:a17:903:1a85:b0:24c:a269:b6e4 with SMTP id d9443c01a7336-24ca269ba8emr37835ad.19.1756873532857; Tue, 02 Sep 2025 21:25:32 -0700 (PDT) From: Nicholas Piggin To: qemu-riscv@nongnu.org Cc: Nicholas Piggin , Laurent Vivier , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-devel@nongnu.org Subject: [PATCH 1/4] tests/tcg/riscv64: Add a user signal handling test Date: Wed, 3 Sep 2025 14:25:07 +1000 Message-ID: <20250903042510.279954-2-npiggin@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250903042510.279954-1-npiggin@gmail.com> References: <20250903042510.279954-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=npiggin@gmail.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1756873644856116600 Content-Type: text/plain; charset="utf-8" Add a few basic signal handling tests for user emulation. Signed-off-by: Nicholas Piggin --- tests/tcg/riscv64/Makefile.target | 5 + tests/tcg/riscv64/test-signal-handling.c | 303 +++++++++++++++++++++++ 2 files changed, 308 insertions(+) create mode 100644 tests/tcg/riscv64/test-signal-handling.c diff --git a/tests/tcg/riscv64/Makefile.target b/tests/tcg/riscv64/Makefile= .target index 8f4690ac57..0c89c46c4f 100644 --- a/tests/tcg/riscv64/Makefile.target +++ b/tests/tcg/riscv64/Makefile.target @@ -5,6 +5,11 @@ VPATH +=3D $(SRC_PATH)/tests/tcg/riscv64 TESTS +=3D test-div TESTS +=3D noexec =20 +# Test signal handling. +TESTS +=3D test-signal-handling +test-signal-handling: CFLAGS +=3D -march=3Drv64gcv +run-test-signal-handling: QEMU_OPTS +=3D -cpu rv64,v=3Don + # Disable compressed instructions for test-noc TESTS +=3D test-noc test-noc: LDFLAGS =3D -nostdlib -static diff --git a/tests/tcg/riscv64/test-signal-handling.c b/tests/tcg/riscv64/t= est-signal-handling.c new file mode 100644 index 0000000000..e9c0170c74 --- /dev/null +++ b/tests/tcg/riscv64/test-signal-handling.c @@ -0,0 +1,303 @@ +/* + * Test for linux-user signal handling. + * + * This ensures that integer and fp register values are + * saved as expected in the sigcontext, created by a SIGILL. + * + * TODO: Register restore is not explicitly verified, except + * for advancing pc, and the restoring of registers that were + * clobbered by the compiler in the signal handler. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#define _GNU_SOURCE +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * This horrible hack seems to be required when including + * signal.h and asm/sigcontext.h, to prevent sigcontext + * redefinition by bits/sigcontext.h :( + * + * bits/sigcontext.h does not have the extended state or + * RISCV_V_MAGIC, etc. It could have just been introduced + * as a new type. + */ +#define _BITS_SIGCONTEXT_H 1 +#include + +static uint64_t *initial_gvalues; +static uint64_t *final_gvalues; +static uint64_t *signal_gvalues; +static double *initial_fvalues; +static double *final_fvalues; +static double *signal_fvalues; + +extern unsigned long unimp_addr[]; + +static bool got_signal =3D false; + +#define BT_BUF_SIZE 100 + +static void *find_callchain_root(void) +{ + int nptrs; + void *buffer[BT_BUF_SIZE]; + + nptrs =3D backtrace(buffer, BT_BUF_SIZE); + + return buffer[nptrs - 1]; +} + +static void *callchain_root; + +static void ILL_handler(int signo, siginfo_t *info, void *context) +{ + ucontext_t *uc =3D context; + struct sigcontext *sc =3D (struct sigcontext *)&uc->uc_mcontext; + + got_signal =3D true; + + assert(unimp_addr =3D=3D info->si_addr); + assert(sc->sc_regs.pc =3D=3D (unsigned long)info->si_addr); + + /* Ensure stack unwind through the signal frame is not broken */ + assert(callchain_root =3D=3D find_callchain_root()); + + for (int i =3D 0; i < 31; i++) { + ((uint64_t *)signal_gvalues)[i] =3D ((unsigned long *)&sc->sc_regs= .ra)[i]; + } + + for (int i =3D 0; i < 32; i++) { + ((uint64_t *)signal_fvalues)[i] =3D sc->sc_fpregs.d.f[i]; + } + /* Test sc->sc_fpregs.d.fcsr ? */ + + sc->sc_regs.pc +=3D 4; +} + +static void init_test(void) +{ + int i; + + callchain_root =3D find_callchain_root(); + + initial_gvalues =3D malloc(8 * 31); + memset(initial_gvalues, 0, 8 * 31); + final_gvalues =3D malloc(8 * 31); + memset(final_gvalues, 0, 8 * 31); + signal_gvalues =3D malloc(8 * 31); + memset(signal_gvalues, 0, 8 * 31); + + initial_fvalues =3D malloc(8 * 32); + memset(initial_fvalues, 0, 8 * 32); + for (i =3D 0; i < 32 ; i++) { + initial_fvalues[i] =3D 3.142 * (i + 1); + } + final_fvalues =3D malloc(8 * 32); + memset(final_fvalues, 0, 8 * 32); + signal_fvalues =3D malloc(8 * 32); + memset(signal_fvalues, 0, 8 * 32); +} + +static void run_test(void) +{ + asm volatile( + /* Save initial values from gp registers */ +" mv t0, %[initial_gvalues] \n" +" sd x1, 0x0(t0) \n" +" sd x2, 0x8(t0) \n" +" sd x3, 0x10(t0) \n" +" sd x4, 0x18(t0) \n" +" sd x5, 0x20(t0) \n" +" sd x6, 0x28(t0) \n" +" sd x7, 0x30(t0) \n" +" sd x8, 0x38(t0) \n" +" sd x9, 0x40(t0) \n" +" sd x10, 0x48(t0) \n" +" sd x11, 0x50(t0) \n" +" sd x12, 0x58(t0) \n" +" sd x13, 0x60(t0) \n" +" sd x14, 0x68(t0) \n" +" sd x15, 0x70(t0) \n" +" sd x16, 0x78(t0) \n" +" sd x17, 0x80(t0) \n" +" sd x18, 0x88(t0) \n" +" sd x19, 0x90(t0) \n" +" sd x20, 0x98(t0) \n" +" sd x21, 0xa0(t0) \n" +" sd x22, 0xa8(t0) \n" +" sd x23, 0xb0(t0) \n" +" sd x24, 0xb8(t0) \n" +" sd x25, 0xc0(t0) \n" +" sd x26, 0xc8(t0) \n" +" sd x27, 0xd0(t0) \n" +" sd x28, 0xd8(t0) \n" +" sd x29, 0xe0(t0) \n" +" sd x30, 0xe8(t0) \n" +" sd x31, 0xf0(t0) \n" + /* Load initial values into float registers */ +" mv t0, %[initial_fvalues] \n" +" fld f0, 0x0(t0) \n" +" fld f1, 0x8(t0) \n" +" fld f2, 0x10(t0) \n" +" fld f3, 0x18(t0) \n" +" fld f4, 0x20(t0) \n" +" fld f5, 0x28(t0) \n" +" fld f6, 0x30(t0) \n" +" fld f7, 0x38(t0) \n" +" fld f8, 0x40(t0) \n" +" fld f9, 0x48(t0) \n" +" fld f10, 0x50(t0) \n" +" fld f11, 0x58(t0) \n" +" fld f12, 0x60(t0) \n" +" fld f13, 0x68(t0) \n" +" fld f14, 0x70(t0) \n" +" fld f15, 0x78(t0) \n" +" fld f16, 0x80(t0) \n" +" fld f17, 0x88(t0) \n" +" fld f18, 0x90(t0) \n" +" fld f19, 0x98(t0) \n" +" fld f20, 0xa0(t0) \n" +" fld f21, 0xa8(t0) \n" +" fld f22, 0xb0(t0) \n" +" fld f23, 0xb8(t0) \n" +" fld f24, 0xc0(t0) \n" +" fld f25, 0xc8(t0) \n" +" fld f26, 0xd0(t0) \n" +" fld f27, 0xd8(t0) \n" +" fld f28, 0xe0(t0) \n" +" fld f29, 0xe8(t0) \n" +" fld f30, 0xf0(t0) \n" +" fld f31, 0xf8(t0) \n" + /* Trigger the SIGILL */ +".global unimp_addr \n" +"unimp_addr: \n" +" unimp \n" +" nop \n" + /* Save final values from gp registers */ +" mv t0, %[final_gvalues] \n" +" sd x1, 0x0(t0) \n" +" sd x2, 0x8(t0) \n" +" sd x3, 0x10(t0) \n" +" sd x4, 0x18(t0) \n" +" sd x5, 0x20(t0) \n" +" sd x6, 0x28(t0) \n" +" sd x7, 0x30(t0) \n" +" sd x8, 0x38(t0) \n" +" sd x9, 0x40(t0) \n" +" sd x10, 0x48(t0) \n" +" sd x11, 0x50(t0) \n" +" sd x12, 0x58(t0) \n" +" sd x13, 0x60(t0) \n" +" sd x14, 0x68(t0) \n" +" sd x15, 0x70(t0) \n" +" sd x16, 0x78(t0) \n" +" sd x17, 0x80(t0) \n" +" sd x18, 0x88(t0) \n" +" sd x19, 0x90(t0) \n" +" sd x20, 0x98(t0) \n" +" sd x21, 0xa0(t0) \n" +" sd x22, 0xa8(t0) \n" +" sd x23, 0xb0(t0) \n" +" sd x24, 0xb8(t0) \n" +" sd x25, 0xc0(t0) \n" +" sd x26, 0xc8(t0) \n" +" sd x27, 0xd0(t0) \n" +" sd x28, 0xd8(t0) \n" +" sd x29, 0xe0(t0) \n" +" sd x30, 0xe8(t0) \n" +" sd x31, 0xf0(t0) \n" + /* Save final values from float registers */ +" mv t0, %[final_fvalues] \n" +" fsd f0, 0x0(t0) \n" +" fsd f1, 0x8(t0) \n" +" fsd f2, 0x10(t0) \n" +" fsd f3, 0x18(t0) \n" +" fsd f4, 0x20(t0) \n" +" fsd f5, 0x28(t0) \n" +" fsd f6, 0x30(t0) \n" +" fsd f7, 0x38(t0) \n" +" fsd f8, 0x40(t0) \n" +" fsd f9, 0x48(t0) \n" +" fsd f10, 0x50(t0) \n" +" fsd f11, 0x58(t0) \n" +" fsd f12, 0x60(t0) \n" +" fsd f13, 0x68(t0) \n" +" fsd f14, 0x70(t0) \n" +" fsd f15, 0x78(t0) \n" +" fsd f16, 0x80(t0) \n" +" fsd f17, 0x88(t0) \n" +" fsd f18, 0x90(t0) \n" +" fsd f19, 0x98(t0) \n" +" fsd f20, 0xa0(t0) \n" +" fsd f21, 0xa8(t0) \n" +" fsd f22, 0xb0(t0) \n" +" fsd f23, 0xb8(t0) \n" +" fsd f24, 0xc0(t0) \n" +" fsd f25, 0xc8(t0) \n" +" fsd f26, 0xd0(t0) \n" +" fsd f27, 0xd8(t0) \n" +" fsd f28, 0xe0(t0) \n" +" fsd f29, 0xe8(t0) \n" +" fsd f30, 0xf0(t0) \n" +" fsd f31, 0xf8(t0) \n" + : "=3Dm" (initial_gvalues), + "=3Dm" (final_gvalues), + "=3Dm" (final_fvalues) + : "m" (initial_fvalues), + [initial_gvalues] "r" (initial_gvalues), + [initial_fvalues] "r" (initial_fvalues), + [final_gvalues] "r" (final_gvalues), + [final_fvalues] "r" (final_fvalues) + : "t0", + "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", + "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", + "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", + "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"); + + assert(got_signal); + + /* + * x4 / t0 is used in the asm so it has to be handled specially + * and is not a simple equality. + */ + assert(initial_gvalues[4] =3D=3D (unsigned long)initial_gvalues); + assert(signal_gvalues[4] =3D=3D (unsigned long)initial_fvalues); + assert(final_gvalues[4] =3D=3D (unsigned long)final_gvalues); + initial_gvalues[4] =3D final_gvalues[4] =3D signal_gvalues[4] =3D 0; + + /* + * Ensure registers match before, inside, and after signal + * handler. + */ + assert(!memcmp(initial_gvalues, final_gvalues, 8 * 31)); + assert(!memcmp(initial_gvalues, signal_gvalues, 8 * 31)); + assert(!memcmp(initial_fvalues, final_fvalues, 8 * 32)); + assert(!memcmp(initial_fvalues, signal_fvalues, 8 * 32)); +} + +int main(void) +{ + struct sigaction act =3D { 0 }; + + act.sa_flags =3D SA_SIGINFO; + act.sa_sigaction =3D &ILL_handler; + if (sigaction(SIGILL, &act, NULL) =3D=3D -1) { + perror("sigaction"); + exit(EXIT_FAILURE); + } + + init_test(); + + run_test(); +} --=20 2.51.0 From nobody Mon Sep 8 09:47:37 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Update the linux-user signal handling to this new structure. Signed-off-by: Nicholas Piggin --- linux-user/riscv/signal.c | 71 ++++++++++++++++++++++++++----- linux-user/riscv/vdso-asmoffset.h | 2 +- 2 files changed, 62 insertions(+), 11 deletions(-) diff --git a/linux-user/riscv/signal.c b/linux-user/riscv/signal.c index 358fa1d82d..4ef55d0848 100644 --- a/linux-user/riscv/signal.c +++ b/linux-user/riscv/signal.c @@ -31,14 +31,43 @@ =20 The code below is qemu re-implementation of arch/riscv/kernel/signal.c = */ =20 -struct target_sigcontext { +struct target_gp_state { abi_long pc; abi_long gpr[31]; /* x0 is not present, so all offsets must be -1 */ +}; + +struct target_fp_state { uint64_t fpr[32]; uint32_t fcsr; +}; + +/* The Magic number for signal context frame header. */ +#define END_MAGIC 0x0 + +/* The size of END signal context header. */ +#define END_HDR_SIZE 0x0 + +struct target_ctx_hdr { + uint32_t magic; + uint32_t size; +}; + +struct target_extra_ext_header { + uint32_t __padding[129] __attribute__((aligned(16))); + uint32_t reserved; + struct target_ctx_hdr hdr; +}; + +struct target_sigcontext { + struct target_gp_state sc_regs; + union { + struct target_fp_state sc_fpregs; + struct target_extra_ext_header sc_extdesc; + }; }; /* cf. riscv-linux:arch/riscv/include/uapi/asm/ptrace.h */ =20 -QEMU_BUILD_BUG_ON(offsetof(struct target_sigcontext, fpr) !=3D offsetof_fr= eg0); +QEMU_BUILD_BUG_ON(offsetof(struct target_sigcontext, sc_fpregs.fpr) !=3D + offsetof_freg0); =20 struct target_ucontext { abi_ulong uc_flags; @@ -79,19 +108,25 @@ static abi_ulong get_sigframe(struct target_sigaction = *ka, =20 static void setup_sigcontext(struct target_sigcontext *sc, CPURISCVState *= env) { + struct target_ctx_hdr *hdr; int i; =20 - __put_user(env->pc, &sc->pc); + __put_user(env->pc, &sc->sc_regs.pc); =20 for (i =3D 1; i < 32; i++) { - __put_user(env->gpr[i], &sc->gpr[i - 1]); + __put_user(env->gpr[i], &sc->sc_regs.gpr[i - 1]); } for (i =3D 0; i < 32; i++) { - __put_user(env->fpr[i], &sc->fpr[i]); + __put_user(env->fpr[i], &sc->sc_fpregs.fpr[i]); } =20 uint32_t fcsr =3D riscv_csr_read(env, CSR_FCSR); - __put_user(fcsr, &sc->fcsr); + __put_user(fcsr, &sc->sc_fpregs.fcsr); + + __put_user(0, &sc->sc_extdesc.reserved); + hdr =3D &sc->sc_extdesc.hdr; + __put_user(END_MAGIC, &hdr->magic); + __put_user(END_HDR_SIZE, &hdr->size); } =20 static void setup_ucontext(struct target_ucontext *uc, @@ -146,20 +181,36 @@ badframe: =20 static void restore_sigcontext(CPURISCVState *env, struct target_sigcontex= t *sc) { + struct target_ctx_hdr *hdr; int i; =20 - __get_user(env->pc, &sc->pc); + __get_user(env->pc, &sc->sc_regs.pc); =20 for (i =3D 1; i < 32; ++i) { - __get_user(env->gpr[i], &sc->gpr[i - 1]); + __get_user(env->gpr[i], &sc->sc_regs.gpr[i - 1]); } for (i =3D 0; i < 32; ++i) { - __get_user(env->fpr[i], &sc->fpr[i]); + __get_user(env->fpr[i], &sc->sc_fpregs.fpr[i]); } =20 uint32_t fcsr; - __get_user(fcsr, &sc->fcsr); + __get_user(fcsr, &sc->sc_fpregs.fcsr); riscv_csr_write(env, CSR_FCSR, fcsr); + + hdr =3D &sc->sc_extdesc.hdr; + uint32_t rsv; + __get_user(rsv, &sc->sc_extdesc.reserved); + if (rsv !=3D 0) { + qemu_log_mask(LOG_GUEST_ERROR, "signal: sigcontext reserved field = is " + "non-zero. Attempting restore anywa= y."); + } + + uint32_t magic; + __get_user(magic, &hdr->magic); + if (magic !=3D END_MAGIC) { + qemu_log_mask(LOG_UNIMP, "signal: unknown extended context header:= " + "0x%08x, ignoring", magic); + } } =20 static void restore_ucontext(CPURISCVState *env, struct target_ucontext *u= c) diff --git a/linux-user/riscv/vdso-asmoffset.h b/linux-user/riscv/vdso-asmo= ffset.h index 123902ef61..7d14228fb3 100644 --- a/linux-user/riscv/vdso-asmoffset.h +++ b/linux-user/riscv/vdso-asmoffset.h @@ -3,7 +3,7 @@ # define offsetof_uc_mcontext 0x120 # define offsetof_freg0 0x80 #else -# define sizeof_rt_sigframe 0x340 +# define sizeof_rt_sigframe 0x440 # define offsetof_uc_mcontext 0x130 # define offsetof_freg0 0x100 #endif --=20 2.51.0 From nobody Mon Sep 8 09:47:37 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1756873608; cv=none; d=zohomail.com; s=zohoarc; b=auIEq09bK3AMrElGOMerdoZlxQXVr0+3+P94B70MUZfVs/NiGoh70oaoVdT9J6EPF4Inl0jUNEEPJngyysD14t2/5tZ5nnfvuH0mB7c1596bYIRKHm7RhtDW5yYwR737IndnZmx3LDDM0PRmbZasw0fGrA6590dEZwZYU5APXl0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756873608; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=CQUkmVWzELLsrd5LFWN5qjCWWbc7bLPOMntiNkwPBtU=; b=NaTebNv5uGe/9CHpYctKbADvs5NRS8TgrVTc3hfbu4+53LDM6O4xBdBBFRnWrhiGx62K1f/SnxgKBcNjMfgrYID9KhtDfJm5QFmFlb3z1Zmq4CPWkBfnKQmAoODqvG5cCqEGN+sxg4oehEGqSPzpK8quM0A04d+2ZtE6f0Q+NZE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756873608713918.3420976153476; Tue, 2 Sep 2025 21:26:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1utf46-0005f5-Ro; Wed, 03 Sep 2025 00:25:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1utf45-0005en-Br; Wed, 03 Sep 2025 00:25:45 -0400 Received: from mail-pg1-x52e.google.com ([2607:f8b0:4864:20::52e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1utf43-0004M0-HT; Wed, 03 Sep 2025 00:25:45 -0400 Received: by mail-pg1-x52e.google.com with SMTP id 41be03b00d2f7-b4c3d8bd21eso3886155a12.2; Tue, 02 Sep 2025 21:25:42 -0700 (PDT) Received: from lima-default (123.253.189.97.qld.leaptel.network. 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Signed-off-by: Nicholas Piggin --- linux-user/riscv/signal.c | 130 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 126 insertions(+), 4 deletions(-) diff --git a/linux-user/riscv/signal.c b/linux-user/riscv/signal.c index 4ef55d0848..4acbabcbc9 100644 --- a/linux-user/riscv/signal.c +++ b/linux-user/riscv/signal.c @@ -41,7 +41,17 @@ struct target_fp_state { uint32_t fcsr; }; =20 +struct target_v_ext_state { + target_ulong vstart; + target_ulong vl; + target_ulong vtype; + target_ulong vcsr; + target_ulong vlenb; + target_ulong datap; +} __attribute__((aligned(16))); + /* The Magic number for signal context frame header. */ +#define RISCV_V_MAGIC 0x53465457 #define END_MAGIC 0x0 =20 /* The size of END signal context header. */ @@ -106,6 +116,88 @@ static abi_ulong get_sigframe(struct target_sigaction = *ka, return sp; } =20 +static unsigned int get_v_state_size(CPURISCVState *env) +{ + RISCVCPU *cpu =3D env_archcpu(env); + + return sizeof(struct target_ctx_hdr) + + sizeof(struct target_v_ext_state) + + cpu->cfg.vlenb * 32; +} + +static struct target_ctx_hdr *save_v_state(CPURISCVState *env, + struct target_ctx_hdr *hdr) +{ + RISCVCPU *cpu =3D env_archcpu(env); + target_ulong vlenb =3D cpu->cfg.vlenb; + uint32_t riscv_v_sc_size =3D get_v_state_size(env); + struct target_v_ext_state *vs; + uint64_t *vdatap; + int i; + + __put_user(RISCV_V_MAGIC, &hdr->magic); + __put_user(riscv_v_sc_size, &hdr->size); + + vs =3D (struct target_v_ext_state *)(hdr + 1); + vdatap =3D (uint64_t *)(vs + 1); + + __put_user(env->vstart, &vs->vstart); + __put_user(env->vl, &vs->vl); + __put_user(env->vtype, &vs->vtype); + target_ulong vcsr =3D riscv_csr_read(env, CSR_VCSR); + __put_user(vcsr, &vs->vcsr); + __put_user(vlenb, &vs->vlenb); + __put_user((target_ulong)vdatap, &vs->datap); + + for (i =3D 0; i < 32; i++) { + int j; + for (j =3D 0; j < vlenb; j +=3D 8) { + size_t idx =3D (i * vlenb + j) / 8; + __put_user(env->vreg[idx], vdatap + idx); + } + } + + return (void *)hdr + riscv_v_sc_size; +} + +static void restore_v_state(CPURISCVState *env, + struct target_ctx_hdr *hdr) +{ + RISCVCPU *cpu =3D env_archcpu(env); + target_ulong vlenb =3D cpu->cfg.vlenb; + struct target_v_ext_state *vs; + uint64_t *vdatap; + int i; + + uint32_t size; + __get_user(size, &hdr->size); + if (size !=3D get_v_state_size(env)) { + g_assert_not_reached(); + /* XXX: warn, bail */ + } + + vs =3D (struct target_v_ext_state *)(hdr + 1); + + __get_user(env->vstart, &vs->vstart); + __get_user(env->vl, &vs->vl); + __get_user(env->vtype, &vs->vtype); + target_ulong vcsr; + __get_user(vcsr, &vs->vcsr); + riscv_csr_write(env, CSR_VCSR, vcsr); + __get_user(vlenb, &vs->vlenb); + target_ulong __vdatap; + __get_user(__vdatap, &vs->datap); + vdatap =3D (uint64_t *)__vdatap; + + for (i =3D 0; i < 32; i++) { + int j; + for (j =3D 0; j < vlenb; j +=3D 8) { + size_t idx =3D (i * vlenb + j) / 8; + __get_user(env->vreg[idx], vdatap + idx); + } + } +} + static void setup_sigcontext(struct target_sigcontext *sc, CPURISCVState *= env) { struct target_ctx_hdr *hdr; @@ -124,7 +216,11 @@ static void setup_sigcontext(struct target_sigcontext = *sc, CPURISCVState *env) __put_user(fcsr, &sc->sc_fpregs.fcsr); =20 __put_user(0, &sc->sc_extdesc.reserved); + hdr =3D &sc->sc_extdesc.hdr; + if (riscv_has_ext(env, RVV)) { + hdr =3D save_v_state(env, hdr); + } __put_user(END_MAGIC, &hdr->magic); __put_user(END_HDR_SIZE, &hdr->size); } @@ -151,8 +247,13 @@ void setup_rt_frame(int sig, struct target_sigaction *= ka, { abi_ulong frame_addr; struct target_rt_sigframe *frame; + size_t frame_size =3D sizeof(*frame); =20 - frame_addr =3D get_sigframe(ka, env, sizeof(*frame)); + if (riscv_has_ext(env, RVV)) { + frame_size +=3D get_v_state_size(env); + } + + frame_addr =3D get_sigframe(ka, env, frame_size); trace_user_setup_rt_frame(env, frame_addr); =20 if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0)) { @@ -207,9 +308,30 @@ static void restore_sigcontext(CPURISCVState *env, str= uct target_sigcontext *sc) =20 uint32_t magic; __get_user(magic, &hdr->magic); - if (magic !=3D END_MAGIC) { - qemu_log_mask(LOG_UNIMP, "signal: unknown extended context header:= " - "0x%08x, ignoring", magic); + while (magic !=3D END_MAGIC) { + if (magic =3D=3D RISCV_V_MAGIC) { + if (riscv_has_ext(env, RVV)) { + restore_v_state(env, hdr); + } else { + qemu_log_mask(LOG_GUEST_ERROR, "signal: sigcontext has V s= tate " + "but CPU does not."); + } + } else { + qemu_log_mask(LOG_GUEST_ERROR, "signal: unknown extended state= in " + "sigcontext magic=3D0x%08x", ma= gic); + } + + if (hdr->size =3D=3D 0) { + qemu_log_mask(LOG_GUEST_ERROR, "signal: extended state in sigc= ontext " + "has size 0"); + } + hdr =3D (void *)hdr + hdr->size; + __get_user(magic, &hdr->magic); + } + + if (hdr->size !=3D END_HDR_SIZE) { + qemu_log_mask(LOG_GUEST_ERROR, "signal: extended state end header = has " + "size=3D%u (should be 0)", hdr->siz= e); } } =20 --=20 2.51.0 From nobody Mon Sep 8 09:47:37 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1756873608; cv=none; d=zohomail.com; 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'A')) +#endif =20 /* * This horrible hack seems to be required when including @@ -41,6 +48,10 @@ static uint64_t *signal_gvalues; static double *initial_fvalues; static double *final_fvalues; static double *signal_fvalues; +static size_t vlenb; +static uint8_t *initial_vvalues; +static uint8_t *final_vvalues; +static uint8_t *signal_vvalues; =20 extern unsigned long unimp_addr[]; =20 @@ -64,6 +75,8 @@ static void ILL_handler(int signo, siginfo_t *info, void = *context) { ucontext_t *uc =3D context; struct sigcontext *sc =3D (struct sigcontext *)&uc->uc_mcontext; + struct __riscv_ctx_hdr *sc_ext =3D &sc->sc_extdesc.hdr; + bool found_v =3D false; =20 got_signal =3D true; =20 @@ -82,12 +95,47 @@ static void ILL_handler(int signo, siginfo_t *info, voi= d *context) } /* Test sc->sc_fpregs.d.fcsr ? */ =20 + assert(sc->sc_extdesc.reserved =3D=3D 0); + while (sc_ext->magic !=3D END_MAGIC) { + assert(sc_ext->size !=3D 0); + + if (sc_ext->magic =3D=3D RISCV_V_MAGIC) { + struct __sc_riscv_v_state *sc_v_state =3D (struct __sc_riscv_v= _state *)(sc_ext + 1); + struct __riscv_v_ext_state *v_state =3D &sc_v_state->v_state; + + found_v =3D true; + + assert(getauxval(AT_HWCAP) & COMPAT_HWCAP_ISA_V); + + assert(v_state->vlenb =3D=3D vlenb); + assert(v_state->vtype =3D=3D 0xc0); /* vma, vta */ + assert(v_state->vl =3D=3D vlenb); + assert(v_state->vstart =3D=3D 0); + assert(v_state->vcsr =3D=3D 0); + + uint64_t *vregs =3D v_state->datap; + for (int i =3D 0; i < 32; i++) { + for (int j =3D 0; j < vlenb; j +=3D 8) { + size_t idx =3D (i * vlenb + j) / 8; + ((uint64_t *)signal_vvalues)[idx] =3D vregs[idx]; + } + } + } + + sc_ext =3D (void *)sc_ext + sc_ext->size; + } + + assert(sc_ext->size =3D=3D 0); + if (getauxval(AT_HWCAP) & COMPAT_HWCAP_ISA_V) { + assert(found_v); + } + sc->sc_regs.pc +=3D 4; } =20 static void init_test(void) { - int i; + int i, j; =20 callchain_root =3D find_callchain_root(); =20 @@ -107,6 +155,19 @@ static void init_test(void) memset(final_fvalues, 0, 8 * 32); signal_fvalues =3D malloc(8 * 32); memset(signal_fvalues, 0, 8 * 32); + + vlenb =3D __riscv_vlenb(); + initial_vvalues =3D malloc(vlenb * 32); + memset(initial_vvalues, 0, vlenb * 32); + for (i =3D 0; i < 32 ; i++) { + for (j =3D 0; j < vlenb; j++) { + initial_vvalues[i * vlenb + j] =3D i * vlenb + j; + } + } + final_vvalues =3D malloc(vlenb * 32); + memset(final_vvalues, 0, vlenb * 32); + signal_vvalues =3D malloc(vlenb * 32); + memset(signal_vvalues, 0, vlenb * 32); } =20 static void run_test(void) @@ -179,6 +240,72 @@ static void run_test(void) " fld f29, 0xe8(t0) \n" " fld f30, 0xf0(t0) \n" " fld f31, 0xf8(t0) \n" + /* Load initial values into vector registers */ +" mv t0, %[initial_vvalues] \n" +" vsetvli x0,%[vlenb],e8,m1,ta,ma \n" +" vle8.v v0, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vle8.v v1, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vle8.v v2, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vle8.v v3, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vle8.v v4, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vle8.v v5, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vle8.v v6, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vle8.v v7, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vle8.v v8, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vle8.v v9, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vle8.v v10, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vle8.v v11, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vle8.v v12, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vle8.v v13, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vle8.v v14, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vle8.v v15, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vle8.v v16, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vle8.v v17, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vle8.v v18, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vle8.v v19, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vle8.v v20, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vle8.v v21, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vle8.v v22, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vle8.v v23, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vle8.v v24, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vle8.v v25, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vle8.v v26, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vle8.v v27, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vle8.v v28, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vle8.v v29, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vle8.v v30, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vle8.v v31, (t0) \n" /* Trigger the SIGILL */ ".global unimp_addr \n" "unimp_addr: \n" @@ -251,19 +378,93 @@ static void run_test(void) " fsd f29, 0xe8(t0) \n" " fsd f30, 0xf0(t0) \n" " fsd f31, 0xf8(t0) \n" + /* Save final values from vector registers */ +" mv t0, %[final_vvalues] \n" +" vse8.v v0, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vse8.v v1, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vse8.v v2, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vse8.v v3, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vse8.v v4, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vse8.v v5, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vse8.v v6, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vse8.v v7, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vse8.v v8, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vse8.v v9, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vse8.v v10, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vse8.v v11, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vse8.v v12, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vse8.v v13, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vse8.v v14, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vse8.v v15, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vse8.v v16, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vse8.v v17, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vse8.v v18, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vse8.v v19, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vse8.v v20, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vse8.v v21, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vse8.v v22, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vse8.v v23, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vse8.v v24, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vse8.v v25, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vse8.v v26, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vse8.v v27, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vse8.v v28, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vse8.v v29, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vse8.v v30, (t0) \n" +" add t0, t0, %[vlenb] \n" +" vse8.v v31, (t0) \n" : "=3Dm" (initial_gvalues), "=3Dm" (final_gvalues), - "=3Dm" (final_fvalues) - : "m" (initial_fvalues), + "=3Dm" (final_fvalues), + "=3Dm" (final_vvalues) + : [vlenb] "r" (vlenb), + "m" (initial_fvalues), + "m" (initial_vvalues), [initial_gvalues] "r" (initial_gvalues), [initial_fvalues] "r" (initial_fvalues), + [initial_vvalues] "r" (initial_vvalues), [final_gvalues] "r" (final_gvalues), - [final_fvalues] "r" (final_fvalues) + [final_fvalues] "r" (final_fvalues), + [final_vvalues] "r" (final_vvalues) : "t0", "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", - "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"); + "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", + "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", + "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", + "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", + "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"); =20 assert(got_signal); =20 @@ -272,7 +473,7 @@ static void run_test(void) * and is not a simple equality. */ assert(initial_gvalues[4] =3D=3D (unsigned long)initial_gvalues); - assert(signal_gvalues[4] =3D=3D (unsigned long)initial_fvalues); + assert(signal_gvalues[4] =3D=3D (unsigned long)initial_vvalues + 31 * = vlenb); assert(final_gvalues[4] =3D=3D (unsigned long)final_gvalues); initial_gvalues[4] =3D final_gvalues[4] =3D signal_gvalues[4] =3D 0; =20 @@ -284,6 +485,8 @@ static void run_test(void) assert(!memcmp(initial_gvalues, signal_gvalues, 8 * 31)); assert(!memcmp(initial_fvalues, final_fvalues, 8 * 32)); assert(!memcmp(initial_fvalues, signal_fvalues, 8 * 32)); + assert(!memcmp(initial_vvalues, signal_vvalues, vlenb * 32)); + assert(!memcmp(initial_vvalues, final_vvalues, vlenb * 32)); } =20 int main(void) --=20 2.51.0