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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1756785300307124100 From: Sid Manning Co-authored-by: Matheus Tavares Bernardino Co-authored-by: Damien Hedde Signed-off-by: Brian Cain --- MAINTAINERS | 2 + docs/devel/hexagon-l2vic.rst | 59 +++++ docs/devel/index-internals.rst | 1 + include/hw/intc/l2vic.h | 38 +++ hw/intc/l2vic.c | 421 +++++++++++++++++++++++++++++++++ hw/hexagon/Kconfig | 1 + hw/intc/Kconfig | 3 + hw/intc/meson.build | 2 + hw/intc/trace-events | 4 + 9 files changed, 531 insertions(+) create mode 100644 docs/devel/hexagon-l2vic.rst create mode 100644 include/hw/intc/l2vic.h create mode 100644 hw/intc/l2vic.c diff --git a/MAINTAINERS b/MAINTAINERS index 4f7748679b..228b5b672f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -233,6 +233,7 @@ F: hw/hexagon/ F: hw/timer/qct-qtimer.c F: include/hw/hexagon/ F: include/hw/timer/qct-qtimer.h +F: hw/intc/l2vic.[ch] X: target/hexagon/idef-parser/ X: target/hexagon/gen_idef_parser_funcs.py F: linux-user/hexagon/ @@ -245,6 +246,7 @@ F: gdb-xml/hexagon*.xml F: docs/system/target-hexagon.rst F: docs/system/hexagon/cdsp.rst F: docs/devel/hexagon-sys.rst +F: docs/devel/hexagon-l2vic.rst T: git https://github.com/quic/qemu.git hex-next =20 Hexagon idef-parser diff --git a/docs/devel/hexagon-l2vic.rst b/docs/devel/hexagon-l2vic.rst new file mode 100644 index 0000000000..0885636274 --- /dev/null +++ b/docs/devel/hexagon-l2vic.rst @@ -0,0 +1,59 @@ +Hexagon L2 Vectored Interrupt Controller +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + + +.. code-block:: none + + +-------+ + | | +----------------+ + | l2vic | | hexagon core | + | | | | + | +-----| | | + ------> |VID0 >------------->irq2 -\ | + ------> | | | | | + ... > | | | | | + ------> | | | | + | +-----| | / | | \ | + | ... | | | | | | | + | +-----| | t0 t1 t2 t3 ...| + ------> |VIDN | | | + ------> | | | | + ------> | | | | + ------> | | | | + | +-----| | | + | | |Global SREG File| + | State | | | + | [ ]|<=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D|=3D>[VID ] = | + | [ ]|<=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D|=3D>[VID1] = | + | [ ]| | | + | [ ]| | | + | | | | + +-------+ +----------------+ + +L2VIC/Core Integration +---------------------- + +* hexagon core supports 8 external interrupt sources +* l2vic supports 1024 input interrupts mapped among 4 output interrupts +* l2vic has four output signals: { VID0, VID1, VID2, VID3 } +* l2vic device has a bank of registers per-VID that can be used to query + the status or assert new interrupts. +* Interrupts are 'steered' to threads based on { thread priority, 'EX' sta= te, + thread interrupt mask, thread interrupt enable, global interrupt enable, + etc. }. +* Any hardware thread could conceivably handle any input interrupt, depend= ent + on state. +* The system register transfer instruction can read the VID0-VID3 values f= rom + the l2vic when reading from hexagon core system registers "VID" and "VID= 1". +* When l2vic VID0 has multiple active interrupts, it pulses the VID0 output + IRQ and stores the IRQ number for the VID0 register field. Only after t= his + interrupt is cleared can the l2vic pulse the VID0 output IRQ again and p= rovide + the next interrupt number on the VID0 register. +* The ``ciad`` instruction clears the l2vic input interrupt and un-disable= s the + core interrupt. If some/an l2vic VID0 interrupt is pending when this oc= curs, + the next interrupt should fire and any subseqeunt reads of the VID regis= ter + should reflect the newly raised interrupt. +* In QEMU, on an external interrupt or an unmasked-pending interrupt, + all vCPUs are triggered (has_work=3D=3Dtrue) and each will grab the IO l= ock + while considering the steering logic to determine whether they're the th= read + that must handle the interrupt. diff --git a/docs/devel/index-internals.rst b/docs/devel/index-internals.rst index 0471db8064..6620497595 100644 --- a/docs/devel/index-internals.rst +++ b/docs/devel/index-internals.rst @@ -15,6 +15,7 @@ Details about QEMU's various subsystems including how to = add features to them. clocks ebpf_rss hexagon-sys + hexagon-l2vic migration/index multi-process reset diff --git a/include/hw/intc/l2vic.h b/include/hw/intc/l2vic.h new file mode 100644 index 0000000000..be845e360c --- /dev/null +++ b/include/hw/intc/l2vic.h @@ -0,0 +1,38 @@ +/* + * QEMU L2VIC Interrupt Controller + * + * Copyright(c) 2020-2025 Qualcomm Innovation Center, Inc. All Rights Rese= rved. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#define L2VIC_VID_GRP_0 0x0 /* Read */ +#define L2VIC_VID_GRP_1 0x4 /* Read */ +#define L2VIC_VID_GRP_2 0x8 /* Read */ +#define L2VIC_VID_GRP_3 0xC /* Read */ +#define L2VIC_VID_0 0x10 /* Read SOFTWARE DEFINED */ +#define L2VIC_VID_1 0x14 /* Read SOFTWARE DEFINED NOT YET USED */ +#define L2VIC_INT_ENABLEn 0x100 /* Read/Write */ +#define L2VIC_INT_ENABLE_CLEARn 0x180 /* Write */ +#define L2VIC_INT_ENABLE_SETn 0x200 /* Write */ +#define L2VIC_INT_TYPEn 0x280 /* Read/Write */ +#define L2VIC_INT_STATUSn 0x380 /* Read */ +#define L2VIC_INT_CLEARn 0x400 /* Write */ +#define L2VIC_SOFT_INTn 0x480 /* Write */ +#define L2VIC_INT_PENDINGn 0x500 /* Read */ +#define L2VIC_INT_GRPn_0 0x600 /* Read/Write */ +#define L2VIC_INT_GRPn_1 0x680 /* Read/Write */ +#define L2VIC_INT_GRPn_2 0x700 /* Read/Write */ +#define L2VIC_INT_GRPn_3 0x780 /* Read/Write */ + +#define L2VIC_INTERRUPT_MAX 1024 +#define L2VIC_CIAD_INSTRUCTION -1 +#define L2VIC_NO_PENDING 0xffffffff +/* + * Note about l2vic groups: + * Each interrupt to L2VIC can be configured to associate with one of + * four groups. + * Group 0 interrupts go to IRQ2 via VID 0 (SSR: 0xC2, the default) + * Group 1 interrupts go to IRQ3 via VID 1 (SSR: 0xC3) + * Group 2 interrupts go to IRQ4 via VID 2 (SSR: 0xC4) + * Group 3 interrupts go to IRQ5 via VID 3 (SSR: 0xC5) + */ diff --git a/hw/intc/l2vic.c b/hw/intc/l2vic.c new file mode 100644 index 0000000000..9753ba2d25 --- /dev/null +++ b/hw/intc/l2vic.c @@ -0,0 +1,421 @@ +/* + * QEMU L2VIC Interrupt Controller + * + * Arm PrimeCell PL190 Vector Interrupt Controller was used as a reference. + * Copyright(c) 2020-2025 Qualcomm Innovation Center, Inc. All Rights Rese= rved. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/irq.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "hw/intc/l2vic.h" +#include "trace.h" + +#define L2VICA(s, n) (s[(n) >> 2]) + +#define TYPE_L2VIC "l2vic" +OBJECT_DECLARE_SIMPLE_TYPE(L2VICState, L2VIC) + +#define SLICE_MAX (L2VIC_INTERRUPT_MAX / 32) + +typedef struct L2VICState { + SysBusDevice parent_obj; + + QemuMutex active; + MemoryRegion iomem; + MemoryRegion fast_iomem; + uint32_t level; + /* + * offset 0:vid group 0 etc, 10 bits in each group + * are used: + */ + uint32_t vid_group[4]; + uint32_t vid0; + /* Clear Status of Active Edge interrupt, not used: */ + uint32_t int_clear[SLICE_MAX] QEMU_ALIGNED(16); + /* Enable interrupt source */ + uint32_t int_enable[SLICE_MAX] QEMU_ALIGNED(16); + /* Clear (set to 0) corresponding bit in int_enable */ + uint32_t int_enable_clear; + /* Set (to 1) corresponding bit in int_enable */ + uint32_t int_enable_set; + /* Present for debugging, not used */ + uint32_t int_pending[SLICE_MAX] QEMU_ALIGNED(16); + /* Generate an interrupt */ + uint32_t int_soft; + /* Which enabled interrupt is active */ + uint32_t int_status[SLICE_MAX] QEMU_ALIGNED(16); + /* Edge or Level interrupt */ + uint32_t int_type[SLICE_MAX] QEMU_ALIGNED(16); + /* L2 interrupt group 0-3 0x600-0x7FF */ + uint32_t int_group_n0[SLICE_MAX] QEMU_ALIGNED(16); + uint32_t int_group_n1[SLICE_MAX] QEMU_ALIGNED(16); + uint32_t int_group_n2[SLICE_MAX] QEMU_ALIGNED(16); + uint32_t int_group_n3[SLICE_MAX] QEMU_ALIGNED(16); + qemu_irq irq[8]; +} L2VICState; + + +/* + * Find out if this irq is associated with a group other than + * the default group + */ +static uint32_t *get_int_group(L2VICState *s, int irq) +{ + int n =3D irq & 0x1f; + if (n < 8) { + return s->int_group_n0; + } + if (n < 16) { + return s->int_group_n1; + } + if (n < 24) { + return s->int_group_n2; + } + return s->int_group_n3; +} + +static int find_slice(int irq) +{ + return irq / 32; +} + +static int get_vid(L2VICState *s, int irq) +{ + uint32_t *group =3D get_int_group(s, irq); + uint32_t slice =3D group[find_slice(irq)]; + /* Mask with 0x7 to remove the GRP:EN bit */ + uint32_t val =3D slice >> ((irq & 0x7) * 4); + if (val & 0x8) { + return val & 0x7; + } else { + return 0; + } +} + +static inline bool vid_active(L2VICState *s) + +{ + /* scan all 1024 bits in int_status arrary */ + const int size =3D sizeof(s->int_status) * CHAR_BIT; + const int active_irq =3D find_first_bit((unsigned long *)s->int_status= , size); + return ((active_irq !=3D size)) ? true : false; +} + +static bool l2vic_update(L2VICState *s, int irq) +{ + if (vid_active(s)) { + return true; + } + + bool pending =3D test_bit(irq, (unsigned long *)s->int_pending); + bool enable =3D test_bit(irq, (unsigned long *)s->int_enable); + if (pending && enable) { + int vid =3D get_vid(s, irq); + set_bit(irq, (unsigned long *)s->int_status); + clear_bit(irq, (unsigned long *)s->int_pending); + clear_bit(irq, (unsigned long *)s->int_enable); + /* ensure the irq line goes low after going high */ + s->vid0 =3D irq; + s->vid_group[get_vid(s, irq)] =3D irq; + + /* already low: now call pulse */ + /* pulse: calls qemu_upper() and then qemu_lower()) */ + qemu_irq_pulse(s->irq[vid + 2]); + trace_l2vic_delivered(irq, vid); + return true; + } + return false; +} + +static void l2vic_update_all(L2VICState *s) +{ + for (int i =3D 0; i < L2VIC_INTERRUPT_MAX; i++) { + if (l2vic_update(s, i) =3D=3D true) { + /* once vid is active, no-one else can set it until ciad */ + return; + } + } +} + +static void l2vic_set_irq(void *opaque, int irq, int level) +{ + L2VICState *s =3D (L2VICState *)opaque; + if (level) { + qemu_mutex_lock(&s->active); + set_bit(irq, (unsigned long *)s->int_pending); + qemu_mutex_unlock(&s->active); + } + l2vic_update(s, irq); +} + +static void l2vic_write(void *opaque, hwaddr offset, uint64_t val, + unsigned size) +{ + L2VICState *s =3D (L2VICState *)opaque; + qemu_mutex_lock(&s->active); + trace_l2vic_reg_write((unsigned)offset, (uint32_t)val); + + if (offset =3D=3D L2VIC_VID_0) { + if ((int)val !=3D L2VIC_CIAD_INSTRUCTION) { + s->vid0 =3D val; + } else { + /* ciad issued: clear int_status */ + clear_bit(s->vid0, (unsigned long *)s->int_status); + } + } else if (offset >=3D L2VIC_INT_ENABLEn && + offset < (L2VIC_INT_ENABLE_CLEARn)) { + L2VICA(s->int_enable, offset - L2VIC_INT_ENABLEn) =3D val; + } else if (offset >=3D L2VIC_INT_ENABLE_CLEARn && + offset < L2VIC_INT_ENABLE_SETn) { + L2VICA(s->int_enable, offset - L2VIC_INT_ENABLE_CLEARn) &=3D ~val; + } else if (offset >=3D L2VIC_INT_ENABLE_SETn && offset < L2VIC_INT_TYP= En) { + L2VICA(s->int_enable, offset - L2VIC_INT_ENABLE_SETn) |=3D val; + } else if (offset >=3D L2VIC_INT_TYPEn && offset < L2VIC_INT_TYPEn + 0= x80) { + L2VICA(s->int_type, offset - L2VIC_INT_TYPEn) =3D val; + } else if (offset >=3D L2VIC_INT_STATUSn && offset < L2VIC_INT_CLEARn)= { + L2VICA(s->int_status, offset - L2VIC_INT_STATUSn) =3D val; + } else if (offset >=3D L2VIC_INT_CLEARn && offset < L2VIC_SOFT_INTn) { + L2VICA(s->int_clear, offset - L2VIC_INT_CLEARn) =3D val; + } else if (offset >=3D L2VIC_INT_PENDINGn && + offset < L2VIC_INT_PENDINGn + 0x80) { + L2VICA(s->int_pending, offset - L2VIC_INT_PENDINGn) =3D val; + } else if (offset >=3D L2VIC_SOFT_INTn && offset < L2VIC_INT_PENDINGn)= { + L2VICA(s->int_enable, offset - L2VIC_SOFT_INTn) |=3D val; + /* + * Need to reverse engineer the actual irq number. + */ + int irq =3D find_first_bit((unsigned long *)&val, + sizeof(s->int_enable[0]) * CHAR_BIT); + hwaddr byteoffset =3D offset - L2VIC_SOFT_INTn; + g_assert(irq !=3D sizeof(s->int_enable[0]) * CHAR_BIT); + irq +=3D byteoffset * 8; + + /* The soft-int interface only works with edge-triggered interrupt= s */ + if (test_bit(irq, (unsigned long *)s->int_type)) { + qemu_mutex_unlock(&s->active); + l2vic_set_irq(opaque, irq, 1); + qemu_mutex_lock(&s->active); + } + } else if (offset >=3D L2VIC_INT_GRPn_0 && offset < L2VIC_INT_GRPn_1) { + L2VICA(s->int_group_n0, offset - L2VIC_INT_GRPn_0) =3D val; + } else if (offset >=3D L2VIC_INT_GRPn_1 && offset < L2VIC_INT_GRPn_2) { + L2VICA(s->int_group_n1, offset - L2VIC_INT_GRPn_1) =3D val; + } else if (offset >=3D L2VIC_INT_GRPn_2 && offset < L2VIC_INT_GRPn_3) { + L2VICA(s->int_group_n2, offset - L2VIC_INT_GRPn_2) =3D val; + } else if (offset >=3D L2VIC_INT_GRPn_3 && offset < L2VIC_INT_GRPn_3 += 0x80) { + L2VICA(s->int_group_n3, offset - L2VIC_INT_GRPn_3) =3D val; + } else { + qemu_log_mask(LOG_UNIMP, + "%s: offset %" PRIx32 " unimplemented\n", __func__, + (int)offset); + } + l2vic_update_all(s); + qemu_mutex_unlock(&s->active); + return; +} + +static uint64_t l2vic_read(void *opaque, hwaddr offset, unsigned size) +{ + uint64_t value; + L2VICState *s =3D (L2VICState *)opaque; + qemu_mutex_lock(&s->active); + + if (offset =3D=3D L2VIC_VID_GRP_0) { + value =3D s->vid_group[0]; + } else if (offset =3D=3D L2VIC_VID_GRP_1) { + value =3D s->vid_group[1]; + } else if (offset =3D=3D L2VIC_VID_GRP_2) { + value =3D s->vid_group[2]; + } else if (offset =3D=3D L2VIC_VID_GRP_3) { + value =3D s->vid_group[3]; + } else if (offset =3D=3D L2VIC_VID_0) { + value =3D s->vid0; + } else if (offset >=3D L2VIC_INT_ENABLEn && + offset < L2VIC_INT_ENABLE_CLEARn) { + value =3D L2VICA(s->int_enable, offset - L2VIC_INT_ENABLEn); + } else if (offset >=3D L2VIC_INT_ENABLE_CLEARn && + offset < L2VIC_INT_ENABLE_SETn) { + value =3D 0; + } else if (offset >=3D L2VIC_INT_ENABLE_SETn && offset < L2VIC_INT_TYP= En) { + value =3D 0; + } else if (offset >=3D L2VIC_INT_TYPEn && offset < L2VIC_INT_TYPEn + 0= x80) { + value =3D L2VICA(s->int_type, offset - L2VIC_INT_TYPEn); + } else if (offset >=3D L2VIC_INT_STATUSn && offset < L2VIC_INT_CLEARn)= { + value =3D L2VICA(s->int_status, offset - L2VIC_INT_STATUSn); + } else if (offset >=3D L2VIC_INT_CLEARn && offset < L2VIC_SOFT_INTn) { + value =3D L2VICA(s->int_clear, offset - L2VIC_INT_CLEARn); + } else if (offset >=3D L2VIC_SOFT_INTn && offset < L2VIC_INT_PENDINGn)= { + value =3D 0; + } else if (offset >=3D L2VIC_INT_PENDINGn && + offset < L2VIC_INT_PENDINGn + 0x80) { + value =3D L2VICA(s->int_pending, offset - L2VIC_INT_PENDINGn); + } else if (offset >=3D L2VIC_INT_GRPn_0 && offset < L2VIC_INT_GRPn_1) { + value =3D L2VICA(s->int_group_n0, offset - L2VIC_INT_GRPn_0); + } else if (offset >=3D L2VIC_INT_GRPn_1 && offset < L2VIC_INT_GRPn_2) { + value =3D L2VICA(s->int_group_n1, offset - L2VIC_INT_GRPn_1); + } else if (offset >=3D L2VIC_INT_GRPn_2 && offset < L2VIC_INT_GRPn_3) { + value =3D L2VICA(s->int_group_n2, offset - L2VIC_INT_GRPn_2); + } else if (offset >=3D L2VIC_INT_GRPn_3 && offset < L2VIC_INT_GRPn_3 += 0x80) { + value =3D L2VICA(s->int_group_n3, offset - L2VIC_INT_GRPn_3); + } else { + value =3D 0; + qemu_log_mask(LOG_GUEST_ERROR, + "L2VIC: %s: offset 0x%" PRIx32 "\n", __func__, + (int)offset); + } + + trace_l2vic_reg_read((unsigned)offset, value); + qemu_mutex_unlock(&s->active); + + return value; +} + +static const MemoryRegionOps l2vic_ops =3D { + .read =3D l2vic_read, + .write =3D l2vic_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, + .valid.unaligned =3D false, +}; + +#define FASTL2VIC_ENABLE 0x0 +#define FASTL2VIC_DISABLE 0x1 +#define FASTL2VIC_INT 0x2 + +static void fastl2vic_write(void *opaque, hwaddr offset, uint64_t val, + unsigned size) +{ + if (offset =3D=3D 0) { + uint32_t cmd =3D (val >> 16) & 0x3; + uint32_t irq =3D val & 0x3ff; + uint32_t slice =3D (irq / 32) * 4; + val =3D 1 << (irq % 32); + + if (cmd =3D=3D FASTL2VIC_ENABLE) { + l2vic_write(opaque, L2VIC_INT_ENABLE_SETn + slice, val, size); + } else if (cmd =3D=3D FASTL2VIC_DISABLE) { + l2vic_write(opaque, L2VIC_INT_ENABLE_CLEARn + slice, val, size= ); + } else if (cmd =3D=3D FASTL2VIC_INT) { + l2vic_write(opaque, L2VIC_SOFT_INTn + slice, val, size); + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid write cmd %" PRId32 "\n", + __func__, cmd); + } + return; + } + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid write offset 0x%08" HWADDR= _PRIx + "\n", __func__, offset); +} + +static const MemoryRegionOps fastl2vic_ops =3D { + .write =3D fastl2vic_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, + .valid.unaligned =3D false, +}; + +static void l2vic_reset_hold(Object *obj, G_GNUC_UNUSED ResetType res_type) +{ + L2VICState *s =3D L2VIC(obj); + memset(s->int_clear, 0, sizeof(s->int_clear)); + memset(s->int_enable, 0, sizeof(s->int_enable)); + memset(s->int_pending, 0, sizeof(s->int_pending)); + memset(s->int_status, 0, sizeof(s->int_status)); + memset(s->int_type, 0, sizeof(s->int_type)); + memset(s->int_group_n0, 0, sizeof(s->int_group_n0)); + memset(s->int_group_n1, 0, sizeof(s->int_group_n1)); + memset(s->int_group_n2, 0, sizeof(s->int_group_n2)); + memset(s->int_group_n3, 0, sizeof(s->int_group_n3)); + s->int_soft =3D 0; + s->vid0 =3D 0; + + l2vic_update_all(s); +} + + +static void reset_irq_handler(void *opaque, int irq, int level) +{ + L2VICState *s =3D (L2VICState *)opaque; + Object *obj =3D OBJECT(opaque); + if (level) { + l2vic_reset_hold(obj, RESET_TYPE_COLD); + } + l2vic_update_all(s); +} + +static void l2vic_init(Object *obj) +{ + DeviceState *dev =3D DEVICE(obj); + L2VICState *s =3D L2VIC(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + int i; + + memory_region_init_io(&s->iomem, obj, &l2vic_ops, s, "l2vic", 0x1000); + sysbus_init_mmio(sbd, &s->iomem); + memory_region_init_io(&s->fast_iomem, obj, &fastl2vic_ops, s, "fast", + 0x10000); + sysbus_init_mmio(sbd, &s->fast_iomem); + + qdev_init_gpio_in(dev, l2vic_set_irq, L2VIC_INTERRUPT_MAX); + qdev_init_gpio_in_named(dev, reset_irq_handler, "reset", 1); + for (i =3D 0; i < 8; i++) { + sysbus_init_irq(sbd, &s->irq[i]); + } + qemu_mutex_init(&s->active); /* TODO: Remove this is an experiment */ +} + +static const VMStateDescription vmstate_l2vic =3D { + .name =3D "l2vic", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D + (VMStateField[]){ + VMSTATE_UINT32(level, L2VICState), + VMSTATE_UINT32_ARRAY(vid_group, L2VICState, 4), + VMSTATE_UINT32(vid0, L2VICState), + VMSTATE_UINT32_ARRAY(int_enable, L2VICState, SLICE_MAX), + VMSTATE_UINT32(int_enable_clear, L2VICState), + VMSTATE_UINT32(int_enable_set, L2VICState), + VMSTATE_UINT32_ARRAY(int_type, L2VICState, SLICE_MAX), + VMSTATE_UINT32_ARRAY(int_status, L2VICState, SLICE_MAX), + VMSTATE_UINT32_ARRAY(int_clear, L2VICState, SLICE_MAX), + VMSTATE_UINT32(int_soft, L2VICState), + VMSTATE_UINT32_ARRAY(int_pending, L2VICState, SLICE_MAX), + VMSTATE_UINT32_ARRAY(int_group_n0, L2VICState, SLICE_MAX), + VMSTATE_UINT32_ARRAY(int_group_n1, L2VICState, SLICE_MAX), + VMSTATE_UINT32_ARRAY(int_group_n2, L2VICState, SLICE_MAX), + VMSTATE_UINT32_ARRAY(int_group_n3, L2VICState, SLICE_MAX), + VMSTATE_END_OF_LIST() } +}; + +static void l2vic_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + dc->vmsd =3D &vmstate_l2vic; + rc->phases.hold =3D l2vic_reset_hold; +} + +static const TypeInfo l2vic_info =3D { + .name =3D TYPE_L2VIC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(L2VICState), + .instance_init =3D l2vic_init, + .class_init =3D l2vic_class_init, +}; + +static void l2vic_register_types(void) +{ + type_register_static(&l2vic_info); +} + +type_init(l2vic_register_types) diff --git a/hw/hexagon/Kconfig b/hw/hexagon/Kconfig index dc74751d21..f51c381a12 100644 --- a/hw/hexagon/Kconfig +++ b/hw/hexagon/Kconfig @@ -3,6 +3,7 @@ config HEX_DSP default y depends on HEXAGON && TCG imply PTIMER + select L2VIC =20 config HEX_VIRT bool diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index 7547528f2c..a5b136e2fa 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -8,6 +8,9 @@ config I8259 config PL190 bool =20 +config L2VIC + bool + config IOAPIC bool select I8259 diff --git a/hw/intc/meson.build b/hw/intc/meson.build index 3137521a4a..9a5e0b3a73 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -67,6 +67,8 @@ specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('x= ics_spapr.c', 'spapr_xi specific_ss.add(when: 'CONFIG_XIVE', if_true: files('xive.c')) specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'], if_true: files('spapr_xive_kvm.c')) + +specific_ss.add(when: 'CONFIG_L2VIC', if_true: files('l2vic.c')) specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c')) specific_ss.add(when: 'CONFIG_LOONGSON_IPI_COMMON', if_true: files('loongs= on_ipi_common.c')) specific_ss.add(when: 'CONFIG_LOONGSON_IPI', if_true: files('loongson_ipi.= c')) diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 018c609ca5..327514f498 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -314,6 +314,10 @@ sh_intc_register(const char *s, int id, unsigned short= v, int c, int m) "%s %u - sh_intc_read(unsigned size, uint64_t offset, unsigned long val) "size %u 0= x%" PRIx64 " -> 0x%lx" sh_intc_write(unsigned size, uint64_t offset, unsigned long val) "size %u = 0x%" PRIx64 " <- 0x%lx" sh_intc_set(int id, int enable) "setting interrupt group %d to %d" +# l2vic.c +l2vic_reg_write(unsigned int addr, uint32_t value) "addr: 0x%03x value: 0x= %08"PRIx32 +l2vic_reg_read(unsigned int addr, uint32_t value) "addr: 0x%03x value: 0x%= 08"PRIx32 +l2vic_delivered(int irq, int vid) "l2vic: delivered %d (vid %d)" =20 # loongson_ipi.c loongson_ipi_read(unsigned size, uint64_t addr, uint64_t val) "size: %u ad= dr: 0x%"PRIx64 "val: 0x%"PRIx64 --=20 2.34.1