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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1756785075711116600 From: Brian Cain Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/cpu.c | 134 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 133 insertions(+), 1 deletion(-) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 0445146f2b..2ae6874841 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -37,6 +37,8 @@ #include "hex_interrupts.h" #include "hexswi.h" #include "exec/cpu-interrupt.h" +#include "exec/target_page.h" +#include "hw/hexagon/hexagon_globalreg.h" #endif =20 static void hexagon_v66_cpu_init(Object *obj) { } @@ -490,7 +492,136 @@ static void hexagon_cpu_init(Object *obj) #endif } =20 -#ifndef CONFIG_USER_ONLY +#if !defined(CONFIG_USER_ONLY) +static bool get_physical_address(CPUHexagonState *env, hwaddr *phys, int *= prot, + int *size, int32_t *excp, target_ulong ad= dress, + MMUAccessType access_type, int mmu_idx) + +{ + if (hexagon_cpu_mmu_enabled(env)) { + return hex_tlb_find_match(env, address, access_type, phys, prot, s= ize, + excp, mmu_idx); + } else { + *phys =3D address & 0xFFFFFFFF; + *prot =3D PAGE_VALID | PAGE_READ | PAGE_WRITE | PAGE_EXEC; + *size =3D TARGET_PAGE_SIZE; + return true; + } +} + +/* qemu seems to only want to know about TARGET_PAGE_SIZE pages */ +static void find_qemu_subpage(vaddr *addr, hwaddr *phys, int page_size) +{ + vaddr page_start =3D *addr & ~((vaddr)(page_size - 1)); + vaddr offset =3D ((*addr - page_start) / TARGET_PAGE_SIZE) * TARGET_PA= GE_SIZE; + *addr =3D page_start + offset; + *phys +=3D offset; +} + + +#define INVALID_BADVA 0xbadabada + +static void set_badva_regs(CPUHexagonState *env, target_ulong VA, int slot, + MMUAccessType access_type) +{ + arch_set_system_reg(env, HEX_SREG_BADVA, VA); + + if (access_type =3D=3D MMU_INST_FETCH || slot =3D=3D 0) { + arch_set_system_reg(env, HEX_SREG_BADVA0, VA); + arch_set_system_reg(env, HEX_SREG_BADVA1, INVALID_BADVA); + SET_SSR_FIELD(env, SSR_V0, 1); + SET_SSR_FIELD(env, SSR_V1, 0); + SET_SSR_FIELD(env, SSR_BVS, 0); + } else if (slot =3D=3D 1) { + arch_set_system_reg(env, HEX_SREG_BADVA0, INVALID_BADVA); + arch_set_system_reg(env, HEX_SREG_BADVA1, VA); + SET_SSR_FIELD(env, SSR_V0, 0); + SET_SSR_FIELD(env, SSR_V1, 1); + SET_SSR_FIELD(env, SSR_BVS, 1); + } else { + g_assert_not_reached(); + } +} + +static void raise_tlbmiss_exception(CPUState *cs, target_ulong VA, int slo= t, + MMUAccessType access_type) +{ + CPUHexagonState *env =3D cpu_env(cs); + + set_badva_regs(env, VA, slot, access_type); + + switch (access_type) { + case MMU_INST_FETCH: + cs->exception_index =3D HEX_EVENT_TLB_MISS_X; + if ((VA & ~TARGET_PAGE_MASK) =3D=3D 0) { + env->cause_code =3D HEX_CAUSE_TLBMISSX_CAUSE_NEXTPAGE; + } else { + env->cause_code =3D HEX_CAUSE_TLBMISSX_CAUSE_NORMAL; + } + break; + case MMU_DATA_LOAD: + cs->exception_index =3D HEX_EVENT_TLB_MISS_RW; + env->cause_code =3D HEX_CAUSE_TLBMISSRW_CAUSE_READ; + break; + case MMU_DATA_STORE: + cs->exception_index =3D HEX_EVENT_TLB_MISS_RW; + env->cause_code =3D HEX_CAUSE_TLBMISSRW_CAUSE_WRITE; + break; + } +} + +static void raise_perm_exception(CPUState *cs, target_ulong VA, int slot, + MMUAccessType access_type, int32_t excp) +{ + CPUHexagonState *env =3D cpu_env(cs); + + set_badva_regs(env, VA, slot, access_type); + cs->exception_index =3D excp; +} + +static const char *access_type_names[] =3D { "MMU_DATA_LOAD ", "MMU_DATA_S= TORE", + "MMU_INST_FETCH" }; + +static const char *mmu_idx_names[] =3D { "MMU_USER_IDX", "MMU_GUEST_IDX", + "MMU_KERNEL_IDX" }; + +static bool hexagon_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, bool = probe, + uintptr_t retaddr) +{ + CPUHexagonState *env =3D cpu_env(cs); + static int slot =3D 0 /* This is always zero for now */; + hwaddr phys; + int prot =3D 0; + int page_size =3D 0; + int32_t excp =3D 0; + bool ret =3D 0; + + qemu_log_mask( + CPU_LOG_MMU, + "%s: tid =3D 0x%x, pc =3D 0x%08" PRIx32 ", vaddr =3D 0x%08" VADDR_= PRIx + ", size =3D %d, %s,\tprobe =3D %d, %s\n", + __func__, env->threadId, env->gpr[HEX_REG_PC], address, size, + access_type_names[access_type], probe, mmu_idx_names[mmu_idx]); + ret =3D get_physical_address(env, &phys, &prot, &page_size, &excp, add= ress, + access_type, mmu_idx); + if (ret) { + if (!excp) { + find_qemu_subpage(&address, &phys, page_size); + tlb_set_page(cs, address, phys, prot, mmu_idx, TARGET_PAGE_SIZ= E); + return ret; + } else { + raise_perm_exception(cs, address, slot, access_type, excp); + do_raise_exception(env, cs->exception_index, env->gpr[HEX_REG_= PC], + retaddr); + } + } + if (probe) { + return false; + } + raise_tlbmiss_exception(cs, address, slot, access_type); + do_raise_exception(env, cs->exception_index, env->gpr[HEX_REG_PC], ret= addr); +} =20 static bool hexagon_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { @@ -533,6 +664,7 @@ static const TCGCPUOps hexagon_tcg_ops =3D { .cpu_exec_interrupt =3D hexagon_cpu_exec_interrupt, .pointer_wrap =3D hexagon_pointer_wrap, .cpu_exec_reset =3D cpu_reset, + .tlb_fill =3D hexagon_tlb_fill, #endif /* !CONFIG_USER_ONLY */ }; =20 --=20 2.34.1