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Mon, 01 Sep 2025 20:48:54 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEZc4gmHzBH5eRJe0dCYApeyLBYkIMx99Kr1745pCi4mfNF3cKiID/FUt46KOkjk1XteJpLEA== X-Received: by 2002:a17:90b:3e8b:b0:329:d50e:2f10 with SMTP id 98e67ed59e1d1-329d51d739emr2510399a91.22.1756784933608; Mon, 01 Sep 2025 20:48:53 -0700 (PDT) From: Brian Cain To: qemu-devel@nongnu.org Cc: brian.cain@oss.qualcomm.com, richard.henderson@linaro.org, philmd@linaro.org, matheus.bernardino@oss.qualcomm.com, ale@rev.ng, anjo@rev.ng, marco.liebel@oss.qualcomm.com, ltaylorsimpson@gmail.com, alex.bennee@linaro.org, quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com, Brian Cain Subject: [PATCH v2 01/39] target/hexagon: Implement ciad helper Date: Mon, 1 Sep 2025 20:48:09 -0700 Message-Id: <20250902034847.1948010-2-brian.cain@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250902034847.1948010-1-brian.cain@oss.qualcomm.com> References: <20250902034847.1948010-1-brian.cain@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1756784996629116600 From: Brian Cain ciad is the clear interrupt auto disable instruction. Signed-off-by: Brian Cain --- target/hexagon/op_helper.c | 45 +++++++++++++++++++++++++++++++++----- 1 file changed, 39 insertions(+), 6 deletions(-) diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index a03fd078be..c38107d5a8 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -34,6 +34,12 @@ #include "op_helper.h" #include "cpu_helper.h" #include "translate.h" +#ifndef CONFIG_USER_ONLY +#include "hw/hexagon/hexagon_globalreg.h" +#include "hex_mmu.h" +#include "hw/intc/l2vic.h" +#include "hex_interrupts.h" +#endif =20 #define SF_BIAS 127 #define SF_MANTBITS 23 @@ -1338,9 +1344,41 @@ void HELPER(vwhist128qm)(CPUHexagonState *env, int32= _t uiV) } =20 #ifndef CONFIG_USER_ONLY +static void hexagon_set_vid(CPUHexagonState *env, uint32_t offset, uint32_= t val) +{ + g_assert((offset =3D=3D L2VIC_VID_0) || (offset =3D=3D L2VIC_VID_1)); + CPUState *cs =3D env_cpu(env); + HexagonCPU *cpu =3D HEXAGON_CPU(cs); + const hwaddr pend_mem =3D cpu->l2vic_base_addr + offset; + cpu_physical_memory_write(pend_mem, &val, sizeof(val)); +} + +static void hexagon_clear_last_irq(CPUHexagonState *env, uint32_t offset) +{ + hexagon_set_vid(env, offset, L2VIC_CIAD_INSTRUCTION); +} + +/* + * ciad - clear interrupt auto disable + * - When taking an interrupt the hardware will set ipend.iad to + * prevent another thread from servicing the interrupt. At the complet= ion + * of service software uses ciad to clear the bit indicating the + * interrupt can be accepted again. + * - ciad also handshakes with the l2vic allowing a new vid on the vector + * port. + */ void HELPER(ciad)(CPUHexagonState *env, uint32_t mask) { - g_assert_not_reached(); + uint32_t ipendad; + uint32_t iad; + + BQL_LOCK_GUARD(); + ipendad =3D READ_SREG(HEX_SREG_IPENDAD); + iad =3D fGET_FIELD(ipendad, IPENDAD_IAD); + fSET_FIELD(ipendad, IPENDAD_IAD, iad & ~(mask)); + arch_set_system_reg(env, HEX_SREG_IPENDAD, ipendad); + hexagon_clear_last_irq(env, L2VIC_VID_0); + hex_interrupt_update(env); } =20 void HELPER(siad)(CPUHexagonState *env, uint32_t mask) @@ -1416,11 +1454,6 @@ static void modify_syscfg(CPUHexagonState *env, uint= 32_t val) g_assert_not_reached(); } =20 -static void hexagon_set_vid(CPUHexagonState *env, uint32_t offset, int val) -{ - g_assert_not_reached(); -} - static uint32_t hexagon_find_last_irq(CPUHexagonState *env, uint32_t vid) { g_assert_not_reached(); --=20 2.34.1