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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1756785977328116600 From: Brian Cain Co-authored-by: Sid Manning Signed-off-by: Brian Cain --- target/hexagon/cpu_helper.h | 8 ++ target/hexagon/cpu.c | 1 - target/hexagon/cpu_helper.c | 37 +++++++++ target/hexagon/op_helper.c | 152 +++++++++++++++++++++++++++++++++++- 4 files changed, 193 insertions(+), 5 deletions(-) diff --git a/target/hexagon/cpu_helper.h b/target/hexagon/cpu_helper.h index 194bcbf451..5f5f15149a 100644 --- a/target/hexagon/cpu_helper.h +++ b/target/hexagon/cpu_helper.h @@ -7,6 +7,14 @@ #ifndef HEXAGON_CPU_HELPER_H #define HEXAGON_CPU_HELPER_H =20 +uint32_t hexagon_get_pmu_counter(CPUHexagonState *cur_env, int index); +uint64_t hexagon_get_sys_pcycle_count(CPUHexagonState *env); +uint32_t hexagon_get_sys_pcycle_count_low(CPUHexagonState *env); +uint32_t hexagon_get_sys_pcycle_count_high(CPUHexagonState *env); +void hexagon_set_sys_pcycle_count(CPUHexagonState *env, uint64_t); +void hexagon_set_sys_pcycle_count_low(CPUHexagonState *env, uint32_t); +void hexagon_set_sys_pcycle_count_high(CPUHexagonState *env, uint32_t); + static inline void arch_set_thread_reg(CPUHexagonState *env, uint32_t reg, uint32_t val) { diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 39b45e6452..bdc9d18395 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -329,7 +329,6 @@ static void hexagon_cpu_realize(DeviceState *dev, Error= **errp) =20 qemu_init_vcpu(cs); cpu_reset(cs); - mcc->parent_realize(dev, errp); } =20 diff --git a/target/hexagon/cpu_helper.c b/target/hexagon/cpu_helper.c index 01fdd6b28d..4b8697de65 100644 --- a/target/hexagon/cpu_helper.c +++ b/target/hexagon/cpu_helper.c @@ -29,10 +29,47 @@ =20 #ifndef CONFIG_USER_ONLY =20 +uint32_t hexagon_get_pmu_counter(CPUHexagonState *cur_env, int index) +{ + g_assert_not_reached(); +} + uint32_t arch_get_system_reg(CPUHexagonState *env, uint32_t reg) { g_assert_not_reached(); } =20 +uint64_t hexagon_get_sys_pcycle_count(CPUHexagonState *env) +{ + g_assert_not_reached(); +} + +uint32_t hexagon_get_sys_pcycle_count_high(CPUHexagonState *env) +{ + g_assert_not_reached(); +} + +uint32_t hexagon_get_sys_pcycle_count_low(CPUHexagonState *env) +{ + g_assert_not_reached(); +} + +void hexagon_set_sys_pcycle_count_high(CPUHexagonState *env, + uint32_t cycles_hi) +{ + g_assert_not_reached(); +} + +void hexagon_set_sys_pcycle_count_low(CPUHexagonState *env, + uint32_t cycles_lo) +{ + g_assert_not_reached(); +} + +void hexagon_set_sys_pcycle_count(CPUHexagonState *env, uint64_t cycles) +{ + g_assert_not_reached(); +} + =20 #endif diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 0aa9b91f85..7851f43475 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -19,6 +19,7 @@ #include "qemu/log.h" #include "accel/tcg/cpu-ldst.h" #include "accel/tcg/probe.h" +#include "qemu/main-loop.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" #include "cpu.h" @@ -1397,25 +1398,168 @@ void HELPER(setimask)(CPUHexagonState *env, uint32= _t pred, uint32_t imask) g_assert_not_reached(); } =20 +static bool handle_pmu_sreg_write(CPUHexagonState *env, uint32_t reg, + uint32_t val) +{ + if (reg =3D=3D HEX_SREG_PMUSTID0 || reg =3D=3D HEX_SREG_PMUSTID1 + || reg =3D=3D HEX_SREG_PMUCFG || reg =3D=3D HEX_SREG_PMUEVTCFG + || reg =3D=3D HEX_SREG_PMUEVTCFG1 + || (reg >=3D HEX_SREG_PMUCNT4 && reg <=3D HEX_SREG_PMUCNT3)) { + qemu_log_mask(LOG_UNIMP, "PMU registers not yet implemented"); + return true; + } + return false; +} + +static void modify_syscfg(CPUHexagonState *env, uint32_t val) +{ + g_assert_not_reached(); +} + +static void hexagon_set_vid(CPUHexagonState *env, uint32_t offset, int val) +{ + g_assert_not_reached(); +} + +static uint32_t hexagon_find_last_irq(CPUHexagonState *env, uint32_t vid) +{ + g_assert_not_reached(); +} + +static void hexagon_read_timer(CPUHexagonState *env, uint32_t *low, + uint32_t *high) +{ + qemu_log_mask(LOG_UNIMP, "reading timer_hi/lo not yet supported\n"); +} + +static inline QEMU_ALWAYS_INLINE void sreg_write(CPUHexagonState *env, + uint32_t reg, uint32_t va= l) + +{ + g_assert(bql_locked()); + if ((reg =3D=3D HEX_SREG_VID) || (reg =3D=3D HEX_SREG_VID1)) { + if (val !=3D L2VIC_NO_PENDING) { + hexagon_set_vid(env, + (reg =3D=3D HEX_SREG_VID) ? L2VIC_VID_0 : L2VI= C_VID_1, + val); + arch_set_system_reg(env, reg, val); + } + } else if (reg =3D=3D HEX_SREG_SYSCFG) { + modify_syscfg(env, val); + } else if (reg =3D=3D HEX_SREG_IMASK) { + val =3D GET_FIELD(IMASK_MASK, val); + arch_set_system_reg(env, reg, val); + } else if (reg =3D=3D HEX_SREG_PCYCLELO) { + hexagon_set_sys_pcycle_count_low(env, val); + } else if (reg =3D=3D HEX_SREG_PCYCLEHI) { + hexagon_set_sys_pcycle_count_high(env, val); + } else if (!handle_pmu_sreg_write(env, reg, val)) { + if (reg >=3D HEX_SREG_GLB_START) { + arch_set_system_reg(env, reg, val); + } else { + arch_set_system_reg(env, reg, val); + } + } +} + +static inline QEMU_ALWAYS_INLINE void +sreg_write_masked(CPUHexagonState *env, uint32_t reg, uint32_t val) + +{ + g_assert(bql_locked()); + if ((reg =3D=3D HEX_SREG_VID) || (reg =3D=3D HEX_SREG_VID1)) { + HexagonCPU *cpu =3D env_archcpu(env); + val =3D hexagon_globalreg_masked_value(cpu, reg, val); + hexagon_set_vid(env, + (reg =3D=3D HEX_SREG_VID) ? L2VIC_VID_0 : L2VIC_VI= D_1, + val); + arch_set_system_reg(env, reg, val); + } else if (reg =3D=3D HEX_SREG_SYSCFG) { + modify_syscfg(env, val); + } else if (reg =3D=3D HEX_SREG_IMASK) { + val =3D GET_FIELD(IMASK_MASK, val); + arch_set_system_reg_masked(env, reg, val); + } else if (reg =3D=3D HEX_SREG_PCYCLELO) { + hexagon_set_sys_pcycle_count_low(env, val); + } else if (reg =3D=3D HEX_SREG_PCYCLEHI) { + hexagon_set_sys_pcycle_count_high(env, val); + } else if (!handle_pmu_sreg_write(env, reg, val)) { + arch_set_system_reg_masked(env, reg, val); + } +} + void HELPER(sreg_write)(CPUHexagonState *env, uint32_t reg, uint32_t val) { - g_assert_not_reached(); + BQL_LOCK_GUARD(); + sreg_write(env, reg, val); } =20 void HELPER(sreg_write_pair)(CPUHexagonState *env, uint32_t reg, uint64_t = val) +{ + BQL_LOCK_GUARD(); + sreg_write(env, reg, val & 0xFFFFFFFF); + sreg_write(env, reg + 1, val >> 32); +} + +void HELPER(sreg_write_pair_masked)(CPUHexagonState *env, uint32_t reg, + uint64_t val) + +{ + BQL_LOCK_GUARD(); + sreg_write_masked(env, reg, val & 0xFFFFFFFF); + sreg_write_masked(env, reg + 1, val >> 32); +} =20 +static inline QEMU_ALWAYS_INLINE uint32_t sreg_read(CPUHexagonState *env, + uint32_t reg) { - g_assert_not_reached(); + g_assert(bql_locked()); + if (reg =3D=3D HEX_SREG_PMUSTID0 || reg =3D=3D HEX_SREG_PMUSTID1 + || reg =3D=3D HEX_SREG_PMUCFG || reg =3D=3D HEX_SREG_PMUEVTCFG + || reg =3D=3D HEX_SREG_PMUEVTCFG1 + || (reg >=3D HEX_SREG_PMUCNT4 && reg <=3D HEX_SREG_PMUCNT3)) { + qemu_log_mask(LOG_UNIMP, "PMU registers not yet implemented"); + return 0; + } + if ((reg =3D=3D HEX_SREG_VID) || (reg =3D=3D HEX_SREG_VID1)) { + const uint32_t vid =3D hexagon_find_last_irq(env, reg); + arch_set_system_reg(env, reg, vid); + } else if ((reg =3D=3D HEX_SREG_TIMERLO) || (reg =3D=3D HEX_SREG_TIMER= HI)) { + uint32_t low =3D 0; + uint32_t high =3D 0; + hexagon_read_timer(env, &low, &high); + arch_set_system_reg(env, HEX_SREG_TIMERLO, low); + arch_set_system_reg(env, HEX_SREG_TIMERHI, high); + } else if (reg =3D=3D HEX_SREG_BADVA) { + target_ulong ssr =3D arch_get_system_reg(env, HEX_SREG_SSR); + if (GET_SSR_FIELD(SSR_BVS, ssr)) { + return arch_get_system_reg(env, HEX_SREG_BADVA1); + } + return arch_get_system_reg(env, HEX_SREG_BADVA0); + } + return arch_get_system_reg(env, reg); } =20 uint32_t HELPER(sreg_read)(CPUHexagonState *env, uint32_t reg) { - g_assert_not_reached(); + BQL_LOCK_GUARD(); + return sreg_read(env, reg); } =20 uint64_t HELPER(sreg_read_pair)(CPUHexagonState *env, uint32_t reg) { - g_assert_not_reached(); + BQL_LOCK_GUARD(); + if (reg =3D=3D HEX_SREG_TIMERLO) { + uint32_t low =3D 0; + uint32_t high =3D 0; + hexagon_read_timer(env, &low, &high); + arch_set_system_reg(env, HEX_SREG_TIMERLO, low); + arch_set_system_reg(env, HEX_SREG_TIMERHI, high); + } else if (reg =3D=3D HEX_SREG_PCYCLELO) { + return hexagon_get_sys_pcycle_count(env); + } + return (uint64_t)sreg_read(env, reg) | + (((uint64_t)sreg_read(env, reg + 1)) << 32); } =20 uint32_t HELPER(greg_read)(CPUHexagonState *env, uint32_t reg) --=20 2.34.1