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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1756785164716124100 From: Brian Cain Define TCG overrides for setprio(), crswap(,sgp{0,1,1:0}). Signed-off-by: Brian Cain --- target/hexagon/cpu_helper.h | 32 ++++++++++++++++++++++++++++ target/hexagon/gen_tcg_sys.h | 41 ++++++++++++++++++++++++++++++++++++ target/hexagon/helper.h | 1 + target/hexagon/cpu_helper.c | 38 +++++++++++++++++++++++++++++++++ target/hexagon/genptr.c | 4 ++++ target/hexagon/op_helper.c | 7 ++++++ target/hexagon/hex_common.py | 2 ++ target/hexagon/meson.build | 14 ++++++------ 8 files changed, 133 insertions(+), 6 deletions(-) create mode 100644 target/hexagon/cpu_helper.h create mode 100644 target/hexagon/gen_tcg_sys.h create mode 100644 target/hexagon/cpu_helper.c diff --git a/target/hexagon/cpu_helper.h b/target/hexagon/cpu_helper.h new file mode 100644 index 0000000000..194bcbf451 --- /dev/null +++ b/target/hexagon/cpu_helper.h @@ -0,0 +1,32 @@ +/* + * Copyright(c) 2019-2025 Qualcomm Innovation Center, Inc. All Rights Rese= rved. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HEXAGON_CPU_HELPER_H +#define HEXAGON_CPU_HELPER_H + +static inline void arch_set_thread_reg(CPUHexagonState *env, uint32_t reg, + uint32_t val) +{ + g_assert(reg < TOTAL_PER_THREAD_REGS); + g_assert_not_reached(); +} + +static inline uint32_t arch_get_thread_reg(CPUHexagonState *env, uint32_t = reg) +{ + g_assert(reg < TOTAL_PER_THREAD_REGS); + g_assert_not_reached(); +} + +static inline void arch_set_system_reg(CPUHexagonState *env, uint32_t reg, + uint32_t val) +{ + g_assert_not_reached(); +} + +uint32_t arch_get_system_reg(CPUHexagonState *env, uint32_t reg); + +#endif + diff --git a/target/hexagon/gen_tcg_sys.h b/target/hexagon/gen_tcg_sys.h new file mode 100644 index 0000000000..362703ab45 --- /dev/null +++ b/target/hexagon/gen_tcg_sys.h @@ -0,0 +1,41 @@ +/* + * Copyright(c) 2022-2025 Qualcomm Innovation Center, Inc. All Rights Rese= rved. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HEXAGON_GEN_TCG_SYS_H +#define HEXAGON_GEN_TCG_SYS_H + +#define fGEN_TCG_Y2_setprio(SHORTCODE) \ + gen_helper_setprio(tcg_env, PtV, RsV) + +#define fGEN_TCG_Y2_crswap0(SHORTCODE) \ + do { \ + TCGv tmp =3D tcg_temp_new(); \ + tcg_gen_mov_tl(tmp, RxV); \ + tcg_gen_mov_tl(RxV, hex_t_sreg[HEX_SREG_SGP0]); \ + tcg_gen_mov_tl(ctx->t_sreg_new_value[HEX_SREG_SGP0], tmp); \ + } while (0) + +#define fGEN_TCG_Y4_crswap1(SHORTCODE) \ + do { \ + TCGv tmp =3D tcg_temp_new(); \ + tcg_gen_mov_tl(tmp, RxV); \ + tcg_gen_mov_tl(RxV, hex_t_sreg[HEX_SREG_SGP1]); \ + tcg_gen_mov_tl(ctx->t_sreg_new_value[HEX_SREG_SGP1], tmp); \ + } while (0) + +#define fGEN_TCG_Y4_crswap10(SHORTCODE) \ + do { \ + g_assert_not_reached(); \ + TCGv_i64 tmp =3D tcg_temp_new_i64(); \ + tcg_gen_mov_i64(tmp, RxxV); \ + tcg_gen_concat_i32_i64(RxxV, \ + hex_t_sreg[HEX_SREG_SGP0], \ + hex_t_sreg[HEX_SREG_SGP1]); \ + tcg_gen_extrl_i64_i32(ctx->t_sreg_new_value[HEX_SREG_SGP0], tmp); \ + tcg_gen_extrh_i64_i32(ctx->t_sreg_new_value[HEX_SREG_SGP1], tmp); \ + } while (0) + +#endif diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h index fddbd99a19..146f4f02e4 100644 --- a/target/hexagon/helper.h +++ b/target/hexagon/helper.h @@ -115,4 +115,5 @@ DEF_HELPER_2(greg_read, i32, env, i32) DEF_HELPER_2(greg_read_pair, i64, env, i32) DEF_HELPER_3(sreg_write, void, env, i32, i32) DEF_HELPER_3(sreg_write_pair, void, env, i32, i64) +DEF_HELPER_3(setprio, void, env, i32, i32) #endif diff --git a/target/hexagon/cpu_helper.c b/target/hexagon/cpu_helper.c new file mode 100644 index 0000000000..01fdd6b28d --- /dev/null +++ b/target/hexagon/cpu_helper.c @@ -0,0 +1,38 @@ +/* + * Copyright(c) 2019-2025 Qualcomm Innovation Center, Inc. All Rights Rese= rved. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "cpu_helper.h" +#include "system/cpus.h" +#ifdef CONFIG_USER_ONLY +#include "qemu.h" +#include "exec/helper-proto.h" +#else +#include "hw/boards.h" +#include "hw/hexagon/hexagon.h" +#endif +#include "exec/cpu-interrupt.h" +#include "exec/target_page.h" +#include "accel/tcg/cpu-ldst.h" +#include "exec/cputlb.h" +#include "qemu/log.h" +#include "tcg/tcg-op.h" +#include "internal.h" +#include "macros.h" +#include "sys_macros.h" +#include "arch.h" + + +#ifndef CONFIG_USER_ONLY + +uint32_t arch_get_system_reg(CPUHexagonState *env, uint32_t reg) +{ + g_assert_not_reached(); +} + + +#endif diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index a474787816..0648daefb6 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -31,6 +31,10 @@ #undef QEMU_GENERATE #include "gen_tcg.h" #include "gen_tcg_hvx.h" +#ifndef CONFIG_USER_ONLY +#include "gen_tcg_sys.h" +#endif + #include "genptr.h" =20 TCGv gen_read_reg(TCGv result, int num) diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index cbbf3048a0..cfd34d8712 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -31,6 +31,7 @@ #include "mmvec/mmvec.h" #include "mmvec/macros.h" #include "op_helper.h" +#include "cpu_helper.h" #include "translate.h" =20 #define SF_BIAS 127 @@ -1366,6 +1367,12 @@ uint64_t HELPER(greg_read_pair)(CPUHexagonState *env= , uint32_t reg) { g_assert_not_reached(); } + +void HELPER(setprio)(CPUHexagonState *env, uint32_t thread, uint32_t prio) +{ + g_assert_not_reached(); +} + #endif =20 =20 diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py index 24139cbe67..009b71f8e6 100755 --- a/target/hexagon/hex_common.py +++ b/target/hexagon/hex_common.py @@ -1361,6 +1361,7 @@ def parse_common_args(desc): parser.add_argument("semantics", help=3D"semantics file") parser.add_argument("overrides", help=3D"overrides file") parser.add_argument("overrides_vec", help=3D"vector overrides file") + parser.add_argument("overrides_sys", help=3D"system overrides file") parser.add_argument("out", help=3D"output file") parser.add_argument("--idef-parser", help=3D"file of instructions translated by idef-pa= rser") @@ -1368,6 +1369,7 @@ def parse_common_args(desc): read_semantics_file(args.semantics) read_overrides_file(args.overrides) read_overrides_file(args.overrides_vec) + read_overrides_file(args.overrides_sys) if args.idef_parser: read_idef_parser_enabled_file(args.idef_parser) calculate_attribs() diff --git a/target/hexagon/meson.build b/target/hexagon/meson.build index bb4ebaae81..3ec53010fa 100644 --- a/target/hexagon/meson.build +++ b/target/hexagon/meson.build @@ -20,6 +20,7 @@ hexagon_ss =3D ss.source_set() hex_common_py =3D 'hex_common.py' gen_tcg_h =3D meson.current_source_dir() / 'gen_tcg.h' gen_tcg_hvx_h =3D meson.current_source_dir() / 'gen_tcg_hvx.h' +gen_tcg_sys_h =3D meson.current_source_dir() / 'gen_tcg_sys.h' idef_parser_dir =3D meson.current_source_dir() / 'idef-parser' =20 # @@ -249,6 +250,7 @@ hexagon_ss.add(files( 'cpu.c', 'translate.c', 'op_helper.c', + 'cpu_helper.c', 'gdbstub.c', 'genptr.c', 'reg_fields.c', @@ -346,12 +348,12 @@ if idef_parser_enabled and 'hexagon-linux-user' in ta= rget_dirs # Setup input and dependencies for the next step, this depends on whet= her or # not idef-parser is enabled helper_dep =3D [semantics_generated, idef_generated_tcg_c, idef_genera= ted_tcg] - helper_in =3D [semantics_generated, gen_tcg_h, gen_tcg_hvx_h, '--idef-= parser', idef_generated_list] + helper_in =3D [semantics_generated, gen_tcg_h, gen_tcg_hvx_h, gen_tcg_= sys_h, '--idef-parser', idef_generated_list] else # Setup input and dependencies for the next step, this depends on whet= her or # not idef-parser is enabled helper_dep =3D [semantics_generated] - helper_in =3D [semantics_generated, gen_tcg_h, gen_tcg_hvx_h] + helper_in =3D [semantics_generated, gen_tcg_h, gen_tcg_hvx_h, gen_tcg_= sys_h] endif =20 # @@ -365,7 +367,7 @@ helper_protos_generated =3D custom_target( 'helper_protos_generated.h.inc', output: 'helper_protos_generated.h.inc', depends: helper_dep, - depend_files: [hex_common_py, gen_tcg_h, gen_tcg_hvx_h], + depend_files: [hex_common_py, gen_tcg_h, gen_tcg_hvx_h, gen_tcg_sys_h], command: [python, files('gen_helper_protos.py'), helper_in, '@OUTPUT@'= ], ) hexagon_ss.add(helper_protos_generated) @@ -374,7 +376,7 @@ helper_funcs_generated =3D custom_target( 'helper_funcs_generated.c.inc', output: 'helper_funcs_generated.c.inc', depends: helper_dep, - depend_files: [hex_common_py, gen_tcg_h, gen_tcg_hvx_h], + depend_files: [hex_common_py, gen_tcg_h, gen_tcg_hvx_h, gen_tcg_sys_h], command: [python, files('gen_helper_funcs.py'), helper_in, '@OUTPUT@'], ) hexagon_ss.add(helper_funcs_generated) @@ -383,7 +385,7 @@ tcg_funcs_generated =3D custom_target( 'tcg_funcs_generated.c.inc', output: 'tcg_funcs_generated.c.inc', depends: helper_dep, - depend_files: [hex_common_py, gen_tcg_h, gen_tcg_hvx_h], + depend_files: [hex_common_py, gen_tcg_h, gen_tcg_hvx_h, gen_tcg_sys_h], command: [python, files('gen_tcg_funcs.py'), helper_in, '@OUTPUT@'], ) hexagon_ss.add(tcg_funcs_generated) @@ -392,7 +394,7 @@ analyze_funcs_generated =3D custom_target( 'analyze_funcs_generated.c.inc', output: 'analyze_funcs_generated.c.inc', depends: helper_dep, - depend_files: [hex_common_py, gen_tcg_h, gen_tcg_hvx_h], + depend_files: [hex_common_py, gen_tcg_h, gen_tcg_hvx_h, gen_tcg_sys_h], command: [python, files('gen_analyze_funcs.py'), helper_in, '@OUTPUT@'= ], ) hexagon_ss.add(analyze_funcs_generated) --=20 2.34.1