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Mon, 01 Sep 2025 05:53:09 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH 4/4] hw/arm: expose Error * to arm_load_dtb Date: Mon, 1 Sep 2025 13:53:04 +0100 Message-ID: <20250901125304.1047624-5-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250901125304.1047624-1-alex.bennee@linaro.org> References: <20250901125304.1047624-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=alex.bennee@linaro.org; helo=mail-ej1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756731291249124100 Currently all calls to arm_load_dtb will result in an exit if we fail. By passing Error * we can use &error_fatal and properly set the error report. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Manos Pitsidianakis --- include/hw/arm/boot.h | 3 ++- hw/arm/boot.c | 35 +++++++++++++++-------------------- hw/arm/virt.c | 6 +++--- 3 files changed, 20 insertions(+), 24 deletions(-) diff --git a/include/hw/arm/boot.h b/include/hw/arm/boot.h index a2e22bda8a5..fdb99c0c1ee 100644 --- a/include/hw/arm/boot.h +++ b/include/hw/arm/boot.h @@ -164,6 +164,7 @@ AddressSpace *arm_boot_address_space(ARMCPU *cpu, * @addr_limit: upper limit of the available memory area at @addr * @as: address space to load image to * @cpu: ARM CPU object + * @errp: Error object, often &error_fatal * * Load a device tree supplied by the machine or by the user with the * '-dtb' command line option, and put it at offset @addr in target @@ -181,7 +182,7 @@ AddressSpace *arm_boot_address_space(ARMCPU *cpu, */ int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo, hwaddr addr_limit, AddressSpace *as, MachineState *ms, - ARMCPU *cpu); + ARMCPU *cpu, Error **errp); =20 /* Write a secure board setup routine with a dummy handler for SMCs */ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, diff --git a/hw/arm/boot.c b/hw/arm/boot.c index f9d0bc7011e..d28ae8b86ab 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -517,7 +517,7 @@ static void fdt_add_psci_node(void *fdt, ARMCPU *armcpu) =20 int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo, hwaddr addr_limit, AddressSpace *as, MachineState *ms, - ARMCPU *cpu) + ARMCPU *cpu, Error **errp) { g_autofree void *fdt =3D NULL; g_auto(GStrv) node_path =3D NULL; @@ -525,25 +525,24 @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_i= nfo *binfo, uint32_t acells, scells; unsigned int i; hwaddr mem_base, mem_len; - Error *err =3D NULL; =20 if (binfo->dtb_filename) { g_autofree char *filename =3D qemu_find_file(QEMU_FILE_TYPE_DTB, binfo->dtb_filename); if (!filename) { - fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_file= name); + error_setg(errp, "Couldn't open dtb file %s", binfo->dtb_filen= ame); return -1; } =20 fdt =3D load_device_tree(filename, &size); if (!fdt) { - fprintf(stderr, "Couldn't open dtb file %s\n", filename); + error_setg(errp, "Couldn't open dtb file %s", filename); return -1; } } else { fdt =3D binfo->get_dtb(binfo, &size); if (!fdt) { - fprintf(stderr, "Board was unable to create a dtb blob\n"); + error_setg(errp, "Board was unable to create a dtb blob"); return -1; } } @@ -561,7 +560,7 @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_inf= o *binfo, scells =3D qemu_fdt_getprop_cell(fdt, "/", "#size-cells", NULL, &error_fatal); if (acells =3D=3D 0 || scells =3D=3D 0) { - fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0= )\n"); + error_setg(errp, "dtb file invalid (#address-cells or #size-cells = 0)"); return -1; } =20 @@ -569,15 +568,13 @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_i= nfo *binfo, /* This is user error so deserves a friendlier error message * than the failure of setprop_sized_cells would provide */ - fprintf(stderr, "qemu: dtb file not compatible with " - "RAM size > 4GB\n"); + error_setg(errp, "qemu: dtb file not compatible with RAM size > 4G= B"); return -1; } =20 /* nop all root nodes matching /memory or /memory@unit-address */ - node_path =3D qemu_fdt_node_unit_path(fdt, "memory", &err); - if (err) { - error_report_err(err); + node_path =3D qemu_fdt_node_unit_path(fdt, "memory", errp); + if (!node_path) { return -1; } while (node_path[n]) { @@ -607,7 +604,7 @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_inf= o *binfo, rc =3D fdt_add_memory_node(fdt, acells, mem_base, scells, mem_len, i); if (rc < 0) { - fprintf(stderr, "couldn't add /memory@%"PRIx64" node\n", + error_setg(errp, "couldn't add /memory@%"PRIx64" node", mem_base); return -1; } @@ -618,7 +615,7 @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_inf= o *binfo, rc =3D fdt_add_memory_node(fdt, acells, binfo->loader_start, scells, binfo->ram_size, -1); if (rc < 0) { - fprintf(stderr, "couldn't add /memory@%"PRIx64" node\n", + error_setg(errp, "couldn't add /memory@%"PRIx64" node", binfo->loader_start); return -1; } @@ -633,7 +630,7 @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_inf= o *binfo, rc =3D qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", ms->kernel_cmdline); if (rc < 0) { - fprintf(stderr, "couldn't set /chosen/bootargs\n"); + error_setg(errp, "couldn't set /chosen/bootargs"); return -1; } } @@ -642,7 +639,7 @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_inf= o *binfo, rc =3D qemu_fdt_setprop_sized_cells(fdt, "/chosen", "linux,initrd-= start", acells, binfo->initrd_start); if (rc < 0) { - fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); + error_setg(errp, "couldn't set /chosen/linux,initrd-start"); return -1; } =20 @@ -651,7 +648,7 @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_inf= o *binfo, binfo->initrd_start + binfo->initrd_size); if (rc < 0) { - fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); + error_setg(errp, "couldn't set /chosen/linux,initrd-end"); return -1; } } @@ -1321,10 +1318,8 @@ void arm_load_kernel(ARMCPU *cpu, MachineState *ms, = struct arm_boot_info *info) * decided whether to enable PSCI and set the psci-conduit CPU propert= ies. */ if (!info->skip_dtb_autoload && have_dtb(info)) { - if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, - as, ms, cpu) < 0) { - exit(1); - } + arm_load_dtb(info->dtb_start, info, info->dtb_limit, + as, ms, cpu, &error_fatal); } } =20 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 9326cfc895f..6061e0ddb50 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1803,9 +1803,9 @@ void virt_machine_done(Notifier *notifier, void *data) vms->memmap[VIRT_PLATFORM_BUS].size, vms->irqmap[VIRT_PLATFORM_BUS]); } - if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms, cpu) = < 0) { - exit(1); - } + + arm_load_dtb(info->dtb_start, info, info->dtb_limit, + as, ms, cpu, &error_fatal); =20 pci_bus_add_fw_cfg_extra_pci_roots(vms->fw_cfg, vms->bus, &error_abort); --=20 2.47.2