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Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 8c73f54e9a..ca1633540f 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -93,7 +93,7 @@ void a64_translate_init(void) } =20 /* - * Return the core mmu_idx to use for A64 load/store insns which + * Return the full arm mmu_idx to use for A64 load/store insns which * have a "unprivileged load/store" variant. Those insns access * EL0 if executed from an EL which has control over EL0 (usually * EL1) but behave like normal loads and stores if executed from @@ -103,7 +103,7 @@ void a64_translate_init(void) * normal encoding (in which case we will return the same * thing as get_mem_index(). */ -static int get_a64_user_mem_index(DisasContext *s, bool unpriv) +static ARMMMUIdx arm_user_mem_index(DisasContext *s, bool unpriv) { /* * If AccType_UNPRIV is not used, the insn uses AccType_NORMAL, @@ -130,7 +130,13 @@ static int get_a64_user_mem_index(DisasContext *s, boo= l unpriv) g_assert_not_reached(); } } - return arm_to_core_mmu_idx(useridx); + return useridx; +} + +/* Return the core mmu_idx per above. */ +static int core_user_mem_index(DisasContext *s, bool unpriv) +{ + return arm_to_core_mmu_idx(arm_user_mem_index(s, unpriv)); } =20 static void set_btype_raw(int val) @@ -3539,7 +3545,7 @@ static void op_addr_ldst_imm_pre(DisasContext *s, arg= _ldst_imm *a, if (!a->p) { tcg_gen_addi_i64(*dirty_addr, *dirty_addr, offset); } - memidx =3D get_a64_user_mem_index(s, a->unpriv); + memidx =3D core_user_mem_index(s, a->unpriv); *clean_addr =3D gen_mte_check1_mmuidx(s, *dirty_addr, is_store, a->w || a->rn !=3D 31, mop, a->unpriv, memidx); @@ -3560,7 +3566,7 @@ static bool trans_STR_i(DisasContext *s, arg_ldst_imm= *a) { bool iss_sf, iss_valid =3D !a->w; TCGv_i64 clean_addr, dirty_addr, tcg_rt; - int memidx =3D get_a64_user_mem_index(s, a->unpriv); + int memidx =3D core_user_mem_index(s, a->unpriv); MemOp mop =3D finalize_memop(s, a->sz + a->sign * MO_SIGN); =20 op_addr_ldst_imm_pre(s, a, &clean_addr, &dirty_addr, a->imm, true, mop= ); @@ -3578,7 +3584,7 @@ static bool trans_LDR_i(DisasContext *s, arg_ldst_imm= *a) { bool iss_sf, iss_valid =3D !a->w; TCGv_i64 clean_addr, dirty_addr, tcg_rt; - int memidx =3D get_a64_user_mem_index(s, a->unpriv); + int memidx =3D core_user_mem_index(s, a->unpriv); MemOp mop =3D finalize_memop(s, a->sz + a->sign * MO_SIGN); =20 op_addr_ldst_imm_pre(s, a, &clean_addr, &dirty_addr, a->imm, false, mo= p); @@ -4476,7 +4482,7 @@ static bool do_SET(DisasContext *s, arg_set *a, bool = is_epilogue, return false; } =20 - memidx =3D get_a64_user_mem_index(s, a->unpriv); + memidx =3D core_user_mem_index(s, a->unpriv); =20 /* * We pass option_a =3D=3D true, matching our implementation; @@ -4530,8 +4536,8 @@ static bool do_CPY(DisasContext *s, arg_cpy *a, bool = is_epilogue, CpyFn fn) return false; } =20 - rmemidx =3D get_a64_user_mem_index(s, runpriv); - wmemidx =3D get_a64_user_mem_index(s, wunpriv); + rmemidx =3D core_user_mem_index(s, runpriv); + wmemidx =3D core_user_mem_index(s, wunpriv); =20 /* * We pass option_a =3D=3D true, matching our implementation; --=20 2.43.0