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Since PSTATE.EXLOCK cannot be set without GCS being present and enabled, no explicit check for GCS is required. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/cpregs.h | 3 ++ target/arm/cpu.h | 1 + target/arm/helper.c | 83 +++++++++++++++++++++++++++++++++++--- target/arm/tcg/op_helper.c | 4 ++ 4 files changed, 85 insertions(+), 6 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index bc6adf5956..15894332b2 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -346,6 +346,9 @@ typedef enum CPAccessResult { * specified target EL. */ CP_ACCESS_UNDEFINED =3D (2 << 2), + + /* Access fails with EXLOCK, a GCS exception syndrome. */ + CP_ACCESS_EXLOCK =3D (3 << 2), } CPAccessResult; =20 /* Indexes into fgt_read[] */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d5a5152a9c..17902eb40d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1511,6 +1511,7 @@ void pmu_init(ARMCPU *cpu); #define PSTATE_C (1U << 29) #define PSTATE_Z (1U << 30) #define PSTATE_N (1U << 31) +#define PSTATE_EXLOCK (1ULL << 34) #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) diff --git a/target/arm/helper.c b/target/arm/helper.c index 83a7d6ae36..2f19695d82 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3432,6 +3432,77 @@ static CPAccessResult access_nv1(CPUARMState *env, c= onst ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 +static CPAccessResult access_exlock_el1(CPUARMState *env, + const ARMCPRegInfo *ri, bool isrea= d) +{ + int el =3D arm_current_el(env); + + if (el =3D=3D 1) { + uint64_t hcr =3D arm_hcr_el2_eff(env); + + /* + * EXLOCK check is disabled for NVx in 'x11'. + * Since we have to diagnose that, dispatch NV1 trap too. + */ + if ((hcr & HCR_NV) && (hcr & HCR_NV1)) { + if (hcr & HCR_NV2) { + return CP_ACCESS_OK; + } + return CP_ACCESS_TRAP_EL2; + } + } + + if (!isread && + (env->pstate & PSTATE_EXLOCK) && + (el_is_in_host(env, el) ? el =3D=3D 2 : el =3D=3D 1) && + (env->cp15.gcscr_el[el] & GCSCR_EXLOCKEN)) { + return CP_ACCESS_EXLOCK; + } + return CP_ACCESS_OK; +} + +static CPAccessResult access_exlock_el2(CPUARMState *env, + const ARMCPRegInfo *ri, bool isrea= d) +{ + int el =3D arm_current_el(env); + + if (el =3D=3D 3) { + return CP_ACCESS_OK; + } + if (el =3D=3D 1) { + uint64_t hcr =3D arm_hcr_el2_eff(env); + + /* + * EXLOCK check is disabled for NVx in 'xx1'. + * Since we have to diagnose that, dispatch NV1 trap too. + */ + if (hcr & HCR_NV) { + if (hcr & HCR_NV2) { + return CP_ACCESS_OK; + } + return CP_ACCESS_TRAP_EL2; + } + } + + if (!isread && + (env->pstate & PSTATE_EXLOCK) && + (env->cp15.gcscr_el[el] & GCSCR_EXLOCKEN)) { + return CP_ACCESS_EXLOCK; + } + return CP_ACCESS_OK; +} + +static CPAccessResult access_exlock_el3(CPUARMState *env, + const ARMCPRegInfo *ri, bool isrea= d) +{ + if (!isread && + (env->pstate & PSTATE_EXLOCK) && + (env->cp15.gcscr_el[3] & GCSCR_EXLOCKEN)) { + return CP_ACCESS_EXLOCK; + } + return CP_ACCESS_OK; +} + #ifdef CONFIG_USER_ONLY /* * `IC IVAU` is handled to improve compatibility with JITs that dual-map t= heir @@ -3603,13 +3674,13 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "ELR_EL1", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_ALIAS, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 0, .opc2 =3D 1, - .access =3D PL1_RW, .accessfn =3D access_nv1, + .access =3D PL1_RW, .accessfn =3D access_exlock_el1, .nv2_redirect_offset =3D 0x230 | NV2_REDIR_NV1, .fieldoffset =3D offsetof(CPUARMState, elr_el[1]) }, { .name =3D "SPSR_EL1", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_ALIAS, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .accessfn =3D access_nv1, + .access =3D PL1_RW, .accessfn =3D access_exlock_el1, .nv2_redirect_offset =3D 0x160 | NV2_REDIR_NV1, .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_SVC]) }, /* @@ -4080,7 +4151,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { { .name =3D "ELR_EL2", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_ALIAS | ARM_CP_NV2_REDIRECT, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 0, .opc2 =3D 1, - .access =3D PL2_RW, + .access =3D PL2_RW, .accessfn =3D access_exlock_el2, .fieldoffset =3D offsetof(CPUARMState, elr_el[2]) }, { .name =3D "ESR_EL2", .state =3D ARM_CP_STATE_BOTH, .type =3D ARM_CP_NV2_REDIRECT, @@ -4098,7 +4169,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { { .name =3D "SPSR_EL2", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_ALIAS | ARM_CP_NV2_REDIRECT, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, + .access =3D PL2_RW, .accessfn =3D access_exlock_el2, .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_HYP]) }, { .name =3D "VBAR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 0, .opc2 =3D 0, @@ -4380,7 +4451,7 @@ static const ARMCPRegInfo el3_cp_reginfo[] =3D { { .name =3D "ELR_EL3", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_ALIAS, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 4, .crm =3D 0, .opc2 =3D 1, - .access =3D PL3_RW, + .access =3D PL3_RW, .accessfn =3D access_exlock_el3, .fieldoffset =3D offsetof(CPUARMState, elr_el[3]) }, { .name =3D "ESR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 5, .crm =3D 2, .opc2 =3D 0, @@ -4391,7 +4462,7 @@ static const ARMCPRegInfo el3_cp_reginfo[] =3D { { .name =3D "SPSR_EL3", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_ALIAS, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 4, .crm =3D 0, .opc2 =3D 0, - .access =3D PL3_RW, + .access =3D PL3_RW, .accessfn =3D access_exlock_el3, .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_MON]) }, { .name =3D "VBAR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 12, .crm =3D 0, .opc2 =3D 0, diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 46a3b911ec..56e117c01e 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -887,6 +887,10 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *e= nv, uint32_t key, } syndrome =3D syn_uncategorized(); break; + case CP_ACCESS_EXLOCK: + /* CP_ACCESS_EXLOCK is always directed to the current EL */ + syndrome =3D syn_gcs_exlock(); + break; default: g_assert_not_reached(); } --=20 2.43.0