From nobody Mon Sep 8 12:46:52 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756574170; cv=none; d=zohomail.com; s=zohoarc; b=hPqUd+4UzeNSeb1adN2UBBciPV9mo7H21RdMKekhHAg+oG1kNSQMwzotAyh2qb3qZn737kNUHEpiWfR+ZkqaT0PNt9SMA+EyQHHQN5FDG+emtzUvs7/oRj3Jp7DZO+Ehl0KL2bc9rSJE8YzuvPKCjf4PhtW+QD+zKsI+MNrb1hY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756574170; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=APFM5mjm/10n5J+KtKVCrzvfw+w3wn4sm2ZqcCK7Dck=; b=L4ktkl7DEhXaJsS7++/cT2hjDlBeQWZj2UHt9I7XTukZJrqMvzqfK4wiYC51CnDN2uTriI68JQ+bZyoWO4HNO4NcQ8zhfTUoHlNfuRu2rTqFF05pTtdAjcNo5Mo2qkYSXIckdXyjTcra01ylAiFyH4WEJnBAA+0O+ehZHh1HE40= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756574170206704.8837205544373; Sat, 30 Aug 2025 10:16:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1usODV-0003TA-Ft; Sat, 30 Aug 2025 12:14:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1usEQb-0007Fd-V9 for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:47:08 -0400 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1usEQW-0004qk-6X for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:47:03 -0400 Received: by mail-pg1-x52a.google.com with SMTP id 41be03b00d2f7-b47175d02dcso2347612a12.3 for ; Fri, 29 Aug 2025 22:46:59 -0700 (PDT) Received: from stoup.. (122-150-204-179.dyn.ip.vocus.au. [122.150.204.179]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2490658999fsm40852715ad.112.2025.08.29.22.46.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Aug 2025 22:46:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1756532818; x=1757137618; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=APFM5mjm/10n5J+KtKVCrzvfw+w3wn4sm2ZqcCK7Dck=; b=t7s/W9/uErsJL9HQ9OYlZvacEnmXVBzmbXqf3jd+2u8eHHg4/NMbfooUH9IrjmQqkN oLQM5v1ezLTzfh0n4Jljs5wlBAB2ngeUpo0Dj9ifx27kdORK7rQI6SXnKrIsRc90zkcK I+t0VnDEKYf2W2dvQkrzoCXkqyLRx0zxNhdgk52eqxtbGcDGSX7yuq8m7WBGHKsvrLAQ 7XNkTQHd3RGRPSuvpawvrMAanPq/jNCHfVZkYqIf3jJnLF8egkVs1onREwH3jWr3GLjN OielGbtyuLgxmxoxVZ1zfF7IaQkDAYt3GKtWh8pj8hkhsVfbvx6tqnjg0lMMhGfu2t2P GkzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756532818; x=1757137618; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=APFM5mjm/10n5J+KtKVCrzvfw+w3wn4sm2ZqcCK7Dck=; b=BvyEmmJe0+QCtjVkECANBANkVf3i/eHS7DxXd6VqLaGUSerp5A384wtM55ZrlDGi/R otrI2owt39BwH6WRKTEivMSzVsfIdyDQp9ZLA2HF9JfwEAhacgiiZD4tGQEkzfsMBqQl FVr7euPBWhYAZgs0T6DdIUSjjAS/hRcO8MLzEhYoSxtC9JJceA7ulphLcnw5g+z8qxSy f8fqWW7jxq1fqUmyOuZyolz0EszGWD9Xv3sfCIylDhC93ySurpj7G+cOY87lCL59S3gt GOse0Vy6qpkvYD85soIqF7vBDj+S1oGRboK0rkrVF7xZ2bV39fyebhIn7zuMIJujvwO6 y3zQ== X-Gm-Message-State: AOJu0YzaMN8O+ZhK2XY0Z/ja8DQ0Zasn60RCD+GP7dgyjBoqBKsSYUC1 PL48YeaQP4tawBQDufX+w+Pb6uGkSqHTyAG0O7qoMbs4Yuy4V5/fNugsh/+XNCmQp6CyJOQp37K QutRVmcE= X-Gm-Gg: ASbGncuckecf1/LSSulLoBmxYyWs7X1HAyiuo74YPq6vfSK1KwJwPU+QJkzMbsEiVGg ccY8uBbMP/t9FQyBByQRsf3s8TupGYMXfr2TOp6bDzGcgkjt3Q/TA6V4Rmw1qNLuleq3QXkv4EK 8VMIhB3lZl/Mi3eVAs2NtNcRmL/Eg4Ty8Jw8ptgGJbUHOfUK4U/dU9wfK9CPhsqwPbdEDUJu+fA u1Ybe2LivCdsk0Pm3xhhqmDHzJigQiE1PZjG22lFow8/GcnYoksrD7S04yO8URTIqA1YnPf7/Sy lv2TNh87J505foQb0+66hF+9sfVuvMYWMl2IKjuIgI/Wp0yBJUTjAXc9mPmTs56uT9xxD58+Ev9 hSy1GerYNQl7ojYRObCzIdmt1xQ1btNadNG+XBD3hQmhnnwrpexm3l/vQfOKS6gmbGD/V18mt8g == X-Google-Smtp-Source: AGHT+IGOpRhE9pQLGDhZcr2o6Z6SojgAcyfqYi6vsTQdOqpj+tDYl93J6/UoPZpvt6pTlxxcgq6Ktg== X-Received: by 2002:a17:903:2cf:b0:248:9e56:e806 with SMTP id d9443c01a7336-24944870a36mr17350975ad.12.1756532818082; Fri, 29 Aug 2025 22:46:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v4 50/84] target/arm: Expand pstate to 64 bits Date: Sat, 30 Aug 2025 15:40:54 +1000 Message-ID: <20250830054128.448363-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756574171451116600 Content-Type: text/plain; charset="utf-8" The ARM now defines 36 bits in SPSR_ELx in aarch64 mode, so it's time to bite the bullet and extend PSTATE to match. Most changes are straightforward, adjusting printf formats, changing local variable types. More complex is migration, where to maintain backward compatibility a new pstate64 record is introduced, and only when one of the extensions that sets bits 32-35 are active. The fate of gdbstub is left undecided for the moment. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/cpu.h | 8 +++--- target/arm/tcg/translate.h | 20 ++++++------- target/arm/cpu.c | 6 ++-- target/arm/gdbstub64.c | 2 ++ target/arm/helper.c | 11 ++++---- target/arm/machine.c | 56 +++++++++++++++++++++++++++++++++++++ target/arm/tcg/helper-a64.c | 2 +- 7 files changed, 82 insertions(+), 23 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6568bca5f9..d5a5152a9c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -268,7 +268,7 @@ typedef struct CPUArchState { uint64_t xregs[32]; uint64_t pc; /* PSTATE isn't an architectural register for ARMv8. However, it is - * convenient for us to assemble the underlying state into a 32 bit fo= rmat + * convenient for us to assemble the underlying state into a 64 bit fo= rmat * identical to the architectural format used for the SPSR. (This is a= lso * what the Linux kernel's 'pstate' field in signal handlers and KVM's * 'pstate' register are.) Of the PSTATE bits: @@ -280,7 +280,7 @@ typedef struct CPUArchState { * SM and ZA are kept in env->svcr * all other bits are stored in their correct places in env->pstate */ - uint32_t pstate; + uint64_t pstate; bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nR= W */ bool thumb; /* True if CPU is in thumb mode; cpsr[5] */ =20 @@ -1547,7 +1547,7 @@ static inline unsigned int aarch64_pstate_mode(unsign= ed int el, bool handler) * interprocessing, so we don't attempt to sync with the cpsr state used by * the 32 bit decoder. */ -static inline uint32_t pstate_read(CPUARMState *env) +static inline uint64_t pstate_read(CPUARMState *env) { int ZF; =20 @@ -1557,7 +1557,7 @@ static inline uint32_t pstate_read(CPUARMState *env) | env->pstate | env->daif | (env->btype << 10); } =20 -static inline void pstate_write(CPUARMState *env, uint32_t val) +static inline void pstate_write(CPUARMState *env, uint64_t val) { env->ZF =3D (~val) & PSTATE_Z; env->NF =3D val; diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 3e63dad2b6..1479f5bf74 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -378,27 +378,27 @@ static inline TCGv_i32 get_ahp_flag(void) } =20 /* Set bits within PSTATE. */ -static inline void set_pstate_bits(uint32_t bits) +static inline void set_pstate_bits(uint64_t bits) { - TCGv_i32 p =3D tcg_temp_new_i32(); + TCGv_i64 p =3D tcg_temp_new_i64(); =20 tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); =20 - tcg_gen_ld_i32(p, tcg_env, offsetof(CPUARMState, pstate)); - tcg_gen_ori_i32(p, p, bits); - tcg_gen_st_i32(p, tcg_env, offsetof(CPUARMState, pstate)); + tcg_gen_ld_i64(p, tcg_env, offsetof(CPUARMState, pstate)); + tcg_gen_ori_i64(p, p, bits); + tcg_gen_st_i64(p, tcg_env, offsetof(CPUARMState, pstate)); } =20 /* Clear bits within PSTATE. */ -static inline void clear_pstate_bits(uint32_t bits) +static inline void clear_pstate_bits(uint64_t bits) { - TCGv_i32 p =3D tcg_temp_new_i32(); + TCGv_i64 p =3D tcg_temp_new_i64(); =20 tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); =20 - tcg_gen_ld_i32(p, tcg_env, offsetof(CPUARMState, pstate)); - tcg_gen_andi_i32(p, p, ~bits); - tcg_gen_st_i32(p, tcg_env, offsetof(CPUARMState, pstate)); + tcg_gen_ld_i64(p, tcg_env, offsetof(CPUARMState, pstate)); + tcg_gen_andi_i64(p, p, ~bits); + tcg_gen_st_i64(p, tcg_env, offsetof(CPUARMState, pstate)); } =20 /* If the singlestep state is Active-not-pending, advance to Active-pendin= g. */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6673d536bf..1c2ff87b89 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1205,7 +1205,7 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE= *f, int flags) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; - uint32_t psr =3D pstate_read(env); + uint64_t psr =3D pstate_read(env); int i, j; int el =3D arm_current_el(env); uint64_t hcr =3D arm_hcr_el2_eff(env); @@ -1227,7 +1227,7 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE= *f, int flags) } else { ns_status =3D ""; } - qemu_fprintf(f, "PSTATE=3D%08x %c%c%c%c %sEL%d%c", + qemu_fprintf(f, "PSTATE=3D%016" PRIx64 " %c%c%c%c %sEL%d%c", psr, psr & PSTATE_N ? 'N' : '-', psr & PSTATE_Z ? 'Z' : '-', @@ -1244,7 +1244,7 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE= *f, int flags) (FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-')); } if (cpu_isar_feature(aa64_bti, cpu)) { - qemu_fprintf(f, " BTYPE=3D%d", (psr & PSTATE_BTYPE) >> 10); + qemu_fprintf(f, " BTYPE=3D%d", (int)(psr & PSTATE_BTYPE) >> 10); } qemu_fprintf(f, "%s%s%s", (hcr & HCR_NV) ? " NV" : "", diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 08e2858539..d0d769df53 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -47,6 +47,7 @@ int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArra= y *mem_buf, int n) case 32: return gdb_get_reg64(mem_buf, env->pc); case 33: + /* pstate is now a 64-bit value; can we simply adjust the xml? */ return gdb_get_reg32(mem_buf, pstate_read(env)); } /* Unknown register. */ @@ -75,6 +76,7 @@ int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t = *mem_buf, int n) return 8; case 33: /* CPSR */ + /* pstate is now a 64-bit value; can we simply adjust the xml? */ pstate_write(env, tmp); return 4; } diff --git a/target/arm/helper.c b/target/arm/helper.c index 7a23730299..83a7d6ae36 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9079,8 +9079,8 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) CPUARMState *env =3D &cpu->env; unsigned int new_el =3D env->exception.target_el; vaddr addr =3D env->cp15.vbar_el[new_el]; - unsigned int new_mode =3D aarch64_pstate_mode(new_el, true); - unsigned int old_mode; + uint64_t new_mode =3D aarch64_pstate_mode(new_el, true); + uint64_t old_mode; unsigned int cur_el =3D arm_current_el(env); int rt; =20 @@ -9228,7 +9228,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) * If NV2 is disabled, change SPSR when NV,NV1 =3D=3D 1,0 = (I_ZJRNN) * If NV2 is enabled, change SPSR when NV is 1 (I_DBTLM) */ - old_mode =3D deposit32(old_mode, 2, 2, 2); + old_mode =3D deposit64(old_mode, 2, 2, 2); } } } else { @@ -9241,7 +9241,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) } env->banked_spsr[aarch64_banked_spsr_index(new_el)] =3D old_mode; =20 - qemu_log_mask(CPU_LOG_INT, "...with SPSR 0x%x\n", old_mode); + qemu_log_mask(CPU_LOG_INT, "...with SPSR 0x%" PRIx64 "\n", old_mode); qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", env->elr_el[new_el]); =20 @@ -9295,7 +9295,8 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) =20 env->pc =3D addr; =20 - qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n", + qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 + " PSTATE 0x%" PRIx64 "\n", new_el, env->pc, pstate_read(env)); } =20 diff --git a/target/arm/machine.c b/target/arm/machine.c index 8dbeca2867..9b00c14b4a 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -836,6 +836,61 @@ static const VMStateInfo vmstate_cpsr =3D { .put =3D put_cpsr, }; =20 +static int get_pstate64_1(QEMUFile *f, void *opaque, size_t size, + const VMStateField *field) +{ + ARMCPU *cpu =3D opaque; + CPUARMState *env =3D &cpu->env; + uint64_t val =3D qemu_get_be64(f); + + env->aarch64 =3D ((val & PSTATE_nRW) =3D=3D 0); + pstate_write(env, val); + return 0; +} + +static int put_pstate64_1(QEMUFile *f, void *opaque, size_t size, + const VMStateField *field, JSONWriter *vmdesc) +{ + ARMCPU *cpu =3D opaque; + CPUARMState *env =3D &cpu->env; + uint64_t val =3D pstate_read(env); + + qemu_put_be64(f, val); + return 0; +} + +static const VMStateInfo vmstate_pstate64_1 =3D { + .name =3D "pstate64", + .get =3D get_pstate64_1, + .put =3D put_pstate64_1, +}; + +static bool pstate64_needed(void *opaque) +{ + ARMCPU *cpu =3D opaque; + CPUARMState *env =3D &cpu->env; + + return is_a64(env) && pstate_read(env) > UINT32_MAX; +} + +static const VMStateDescription vmstate_pstate64 =3D { + .name =3D "cpu/pstate64", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D pstate64_needed, + .fields =3D (const VMStateField[]) { + { + .name =3D "pstate64", + .version_id =3D 0, + .size =3D sizeof(uint64_t), + .info =3D &vmstate_pstate64_1, + .flags =3D VMS_SINGLE, + .offset =3D 0, + }, + VMSTATE_END_OF_LIST() + }, +}; + static int get_power(QEMUFile *f, void *opaque, size_t size, const VMStateField *field) { @@ -1119,6 +1174,7 @@ const VMStateDescription vmstate_arm_cpu =3D { &vmstate_serror, &vmstate_irq_line_state, &vmstate_wfxt_timer, + &vmstate_pstate64, NULL } }; diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 71c6c44ee8..f61adf1f80 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -639,7 +639,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_= t new_pc) ARMCPU *cpu =3D env_archcpu(env); int cur_el =3D arm_current_el(env); unsigned int spsr_idx =3D aarch64_banked_spsr_index(cur_el); - uint32_t spsr =3D env->banked_spsr[spsr_idx]; + uint64_t spsr =3D env->banked_spsr[spsr_idx]; int new_el; bool return_to_aa64 =3D (spsr & PSTATE_nRW) =3D=3D 0; =20 --=20 2.43.0